Revision 80337b66 hw/integratorcp.c
| b/hw/integratorcp.c | ||
|---|---|---|
| 305 | 305 |
int parent_irq; |
| 306 | 306 |
} icp_pic_state; |
| 307 | 307 |
|
| 308 |
static void icp_pic_set_level(icp_pic_state *, int, int); |
|
| 309 |
|
|
| 310 | 308 |
static void icp_pic_update(icp_pic_state *s) |
| 311 | 309 |
{
|
| 312 | 310 |
CPUState *env; |
| ... | ... | |
| 314 | 312 |
uint32_t flags; |
| 315 | 313 |
|
| 316 | 314 |
flags = (s->level & s->irq_enabled); |
| 317 |
icp_pic_set_level((icp_pic_state *)s->parent, s->parent_irq,
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|
| 318 |
flags != 0);
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| 315 |
pic_set_irq_new(s->parent, s->parent_irq,
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| 316 |
flags != 0); |
|
| 319 | 317 |
return; |
| 320 | 318 |
} |
| 321 | 319 |
/* Raise CPU interrupt. */ |
| ... | ... | |
| 332 | 330 |
} |
| 333 | 331 |
} |
| 334 | 332 |
|
| 335 |
static void icp_pic_set_level(icp_pic_state *s, int n, int level)
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| 333 |
void pic_set_irq_new(void *opaque, int irq, int level)
|
|
| 336 | 334 |
{
|
| 335 |
icp_pic_state *s = (icp_pic_state *)opaque; |
|
| 337 | 336 |
if (level) |
| 338 |
s->level |= 1 << n;
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| 337 |
s->level |= 1 << irq;
|
|
| 339 | 338 |
else |
| 340 |
s->level &= ~(1 << n);
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| 339 |
s->level &= ~(1 << irq);
|
|
| 341 | 340 |
icp_pic_update(s); |
| 342 | 341 |
} |
| 343 | 342 |
|
| ... | ... | |
| 385 | 384 |
break; |
| 386 | 385 |
case 4: /* INT_SOFTSET */ |
| 387 | 386 |
if (value & 1) |
| 388 |
icp_pic_set_level(s, 0, 1);
|
|
| 387 |
pic_set_irq_new(s, 0, 1);
|
|
| 389 | 388 |
break; |
| 390 | 389 |
case 5: /* INT_SOFTCLR */ |
| 391 | 390 |
if (value & 1) |
| 392 |
icp_pic_set_level(s, 0, 0);
|
|
| 391 |
pic_set_irq_new(s, 0, 0);
|
|
| 393 | 392 |
break; |
| 394 | 393 |
case 10: /* FRQ_ENABLESET */ |
| 395 | 394 |
s->fiq_enabled |= value; |
| ... | ... | |
| 513 | 512 |
/* Update interrupts. */ |
| 514 | 513 |
for (n = 0; n < 3; n++) {
|
| 515 | 514 |
if (s->int_level[n] && (s->control[n] & 0x20)) {
|
| 516 |
icp_pic_set_level(s->pic, 5 + n, 1);
|
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| 515 |
pic_set_irq_new(s->pic, 5 + n, 1);
|
|
| 517 | 516 |
} else {
|
| 518 |
icp_pic_set_level(s->pic, 5 + n, 0);
|
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| 517 |
pic_set_irq_new(s->pic, 5 + n, 0);
|
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| 519 | 518 |
} |
| 520 | 519 |
if (next - s->expires[n] < 0) |
| 521 | 520 |
next = s->expires[n]; |
| ... | ... | |
| 731 | 730 |
uint32_t flags; |
| 732 | 731 |
|
| 733 | 732 |
flags = s->int_level & s->int_enabled; |
| 734 |
icp_pic_set_level(s->pic, s->irq, flags != 0);
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| 733 |
pic_set_irq_new(s->pic, s->irq, flags != 0);
|
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| 735 | 734 |
} |
| 736 | 735 |
|
| 737 | 736 |
static uint32_t pl011_read(void *opaque, target_phys_addr_t offset) |
| ... | ... | |
| 1020 | 1019 |
s->pending = level; |
| 1021 | 1020 |
raise = (s->pending && (s->cr & 0x10) != 0) |
| 1022 | 1021 |
|| (s->cr & 0x08) != 0; |
| 1023 |
icp_pic_set_level(s->pic, s->irq, raise);
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| 1022 |
pic_set_irq_new(s->pic, s->irq, raise);
|
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| 1024 | 1023 |
} |
| 1025 | 1024 |
|
| 1026 | 1025 |
static uint32_t icp_kmi_read(void *opaque, target_phys_addr_t offset) |
| ... | ... | |
| 1196 | 1195 |
icp_control_init(0xcb000000); |
| 1197 | 1196 |
icp_kmi_init(0x18000000, pic, 3, 0); |
| 1198 | 1197 |
icp_kmi_init(0x19000000, pic, 4, 1); |
| 1198 |
if (nd_table[0].vlan) |
|
| 1199 |
smc91c111_init(&nd_table[0], 0xc8000000, pic, 27); |
|
| 1199 | 1200 |
|
| 1200 | 1201 |
/* Load the kernel. */ |
| 1201 | 1202 |
if (!kernel_filename) {
|
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