Archipelago » qemu

typedef struct {

    uint32_t value;

    qemu_irq irq;

    QEMUTimer *qtimer;

    int num;

        s->irq_enabled = value & 0xfff;

        break;

    case OSSR:	/* Status register */

        s->events &= ~value;

                qemu_irq_lower(s->timer[i].irq);

        break;

    case OWER:	/* XXX: Reset on OSMR3 match? */

        s->reset3 = value;

    PXA2xxTimerInfo *i = t->info;

    if (i->irq_enabled & (1 << t->num)) {

        i->events |= 1 << t->num;

        qemu_irq_raise(t->irq);

    }

        sysbus_init_irq(dev, &s->timer[i].irq);

        s->timer[i].info = s;

        s->timer[i].num = i;

        s->timer[i].qtimer = qemu_new_timer(vm_clock,

                        pxa2xx_timer_tick, &s->timer[i]);

    }

            s->tm4[i].tm.value = 0;

            s->tm4[i].tm.info = s;

            s->tm4[i].tm.num = i + 4;

            s->tm4[i].freq = 0;

            s->tm4[i].control = 0x0;

            s->tm4[i].tm.qtimer = qemu_new_timer(vm_clock,

static const VMStateDescription vmstate_pxa2xx_timer0_regs = {

    .name = "pxa2xx_timer0",

    .fields = (VMStateField[]) {

        VMSTATE_UINT32(value, PXA2xxTimer0),

        VMSTATE_END_OF_LIST(),

    },

};