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/*
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* pcie.c
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*
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* Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "sysemu.h" |
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#include "range.h" |
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#include "pci_bridge.h" |
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#include "pcie.h" |
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#include "msix.h" |
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#include "msi.h" |
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#include "pci_internals.h" |
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#include "pcie_regs.h" |
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#include "range.h" |
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//#define DEBUG_PCIE
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#ifdef DEBUG_PCIE
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# define PCIE_DPRINTF(fmt, ...) \
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fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__) |
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#else
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# define PCIE_DPRINTF(fmt, ...) do {} while (0) |
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#endif
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#define PCIE_DEV_PRINTF(dev, fmt, ...) \
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PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__) |
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/***************************************************************************
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* pci express capability helper functions
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*/
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int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
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{ |
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int pos;
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uint8_t *exp_cap; |
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assert(pci_is_express(dev)); |
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pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, |
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PCI_EXP_VER2_SIZEOF); |
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if (pos < 0) { |
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return pos;
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} |
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dev->exp.exp_cap = pos; |
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exp_cap = dev->config + pos; |
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/* capability register
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interrupt message number defaults to 0 */
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pci_set_word(exp_cap + PCI_EXP_FLAGS, |
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((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) | |
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PCI_EXP_FLAGS_VER2); |
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/* device capability register
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* table 7-12:
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* roll based error reporting bit must be set by all
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* Functions conforming to the ECN, PCI Express Base
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* Specification, Revision 1.1., or subsequent PCI Express Base
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* Specification revisions.
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*/
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pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER); |
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pci_set_long(exp_cap + PCI_EXP_LNKCAP, |
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(port << PCI_EXP_LNKCAP_PN_SHIFT) | |
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PCI_EXP_LNKCAP_ASPMS_0S | |
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PCI_EXP_LNK_MLW_1 | |
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PCI_EXP_LNK_LS_25); |
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pci_set_word(exp_cap + PCI_EXP_LNKSTA, |
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PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25); |
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pci_set_long(exp_cap + PCI_EXP_DEVCAP2, |
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PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP); |
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pci_set_word(dev->wmask + pos, PCI_EXP_DEVCTL2_EETLPPB); |
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return pos;
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} |
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void pcie_cap_exit(PCIDevice *dev)
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{ |
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pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF); |
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} |
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uint8_t pcie_cap_get_type(const PCIDevice *dev)
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{ |
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uint32_t pos = dev->exp.exp_cap; |
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assert(pos > 0);
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return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) &
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PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT; |
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} |
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/* MSI/MSI-X */
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/* pci express interrupt message number */
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/* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */
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void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector)
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{ |
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uint8_t *exp_cap = dev->config + dev->exp.exp_cap; |
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assert(vector < 32);
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pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ); |
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pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS, |
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vector << PCI_EXP_FLAGS_IRQ_SHIFT); |
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} |
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uint8_t pcie_cap_flags_get_vector(PCIDevice *dev) |
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{ |
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return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) &
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PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT; |
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} |
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void pcie_cap_deverr_init(PCIDevice *dev)
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{ |
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uint32_t pos = dev->exp.exp_cap; |
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pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP, |
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PCI_EXP_DEVCAP_RBER); |
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pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL, |
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PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | |
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PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); |
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pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA, |
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PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED | |
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PCI_EXP_DEVSTA_URD | PCI_EXP_DEVSTA_URD); |
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} |
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void pcie_cap_deverr_reset(PCIDevice *dev)
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{ |
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uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; |
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pci_long_test_and_clear_mask(devctl, |
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PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | |
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PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); |
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} |
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static void hotplug_event_update_event_status(PCIDevice *dev) |
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{ |
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uint32_t pos = dev->exp.exp_cap; |
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uint8_t *exp_cap = dev->config + pos; |
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uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); |
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uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); |
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dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) && |
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(sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED); |
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} |
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static void hotplug_event_notify(PCIDevice *dev) |
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{ |
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bool prev = dev->exp.hpev_notified;
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hotplug_event_update_event_status(dev); |
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if (prev == dev->exp.hpev_notified) {
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return;
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} |
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/* Note: the logic above does not take into account whether interrupts
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* are masked. The result is that interrupt will be sent when it is
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* subsequently unmasked. This appears to be legal: Section 6.7.3.4:
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* The Port may optionally send an MSI when there are hot-plug events that
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* occur while interrupt generation is disabled, and interrupt generation is
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* subsequently enabled. */
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if (!pci_msi_enabled(dev)) {
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qemu_set_irq(dev->irq[dev->exp.hpev_intx], dev->exp.hpev_notified); |
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} else if (dev->exp.hpev_notified) { |
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pci_msi_notify(dev, pcie_cap_flags_get_vector(dev)); |
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} |
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} |
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/*
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* A PCI Express Hot-Plug Event has occured, so update slot status register
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* and notify OS of the event if necessary.
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*
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* 6.7.3 PCI Express Hot-Plug Events
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* 6.7.3.4 Software Notification of Hot-Plug Events
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*/
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static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event) |
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{ |
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/* Minor optimization: if nothing changed - no event is needed. */
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if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap +
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PCI_EXP_SLTSTA, event)) { |
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return;
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} |
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hotplug_event_notify(dev); |
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} |
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static int pcie_cap_slot_hotplug(DeviceState *qdev, |
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PCIDevice *pci_dev, int state)
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{ |
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PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev); |
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uint8_t *exp_cap = d->config + d->exp.exp_cap; |
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uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); |
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if (!pci_dev->qdev.hotplugged) {
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assert(state); /* this case only happens at machine creation. */
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pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, |
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PCI_EXP_SLTSTA_PDS); |
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return 0; |
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} |
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PCIE_DEV_PRINTF(pci_dev, "hotplug state: %d\n", state);
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if (sltsta & PCI_EXP_SLTSTA_EIS) {
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/* the slot is electromechanically locked.
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* This error is propagated up to qdev and then to HMP/QMP.
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*/
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return -EBUSY;
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} |
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/* TODO: multifunction hot-plug.
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* Right now, only a device of function = 0 is allowed to be
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* hot plugged/unplugged.
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*/
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assert(PCI_FUNC(pci_dev->devfn) == 0);
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if (state) {
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pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, |
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PCI_EXP_SLTSTA_PDS); |
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pcie_cap_slot_event(d, PCI_EXP_HP_EV_PDC); |
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} else {
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qdev_free(&pci_dev->qdev); |
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pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, |
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PCI_EXP_SLTSTA_PDS); |
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pcie_cap_slot_event(d, PCI_EXP_HP_EV_PDC); |
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} |
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return 0; |
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} |
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/* pci express slot for pci express root/downstream port
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PCI express capability slot registers */
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void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot)
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{ |
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uint32_t pos = dev->exp.exp_cap; |
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pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS, |
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PCI_EXP_FLAGS_SLOT); |
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pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP, |
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~PCI_EXP_SLTCAP_PSN); |
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pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, |
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(slot << PCI_EXP_SLTCAP_PSN_SHIFT) | |
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PCI_EXP_SLTCAP_EIP | |
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PCI_EXP_SLTCAP_HPS | |
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PCI_EXP_SLTCAP_HPC | |
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PCI_EXP_SLTCAP_PIP | |
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PCI_EXP_SLTCAP_AIP | |
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PCI_EXP_SLTCAP_ABP); |
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pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, |
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PCI_EXP_SLTCTL_PIC | |
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PCI_EXP_SLTCTL_AIC); |
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pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL, |
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PCI_EXP_SLTCTL_PIC_OFF | |
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PCI_EXP_SLTCTL_AIC_OFF); |
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pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, |
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PCI_EXP_SLTCTL_PIC | |
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PCI_EXP_SLTCTL_AIC | |
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PCI_EXP_SLTCTL_HPIE | |
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PCI_EXP_SLTCTL_CCIE | |
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PCI_EXP_SLTCTL_PDCE | |
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PCI_EXP_SLTCTL_ABPE); |
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/* Although reading PCI_EXP_SLTCTL_EIC returns always 0,
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* make the bit writable here in order to detect 1b is written.
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* pcie_cap_slot_write_config() test-and-clear the bit, so
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* this bit always returns 0 to the guest.
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*/
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pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, |
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PCI_EXP_SLTCTL_EIC); |
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pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA, |
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PCI_EXP_HP_EV_SUPPORTED); |
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dev->exp.hpev_notified = false;
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pci_bus_hotplug(pci_bridge_get_sec_bus(DO_UPCAST(PCIBridge, dev, dev)), |
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pcie_cap_slot_hotplug, &dev->qdev); |
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} |
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void pcie_cap_slot_reset(PCIDevice *dev)
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{ |
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uint8_t *exp_cap = dev->config + dev->exp.exp_cap; |
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PCIE_DEV_PRINTF(dev, "reset\n");
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pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, |
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PCI_EXP_SLTCTL_EIC | |
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PCI_EXP_SLTCTL_PIC | |
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PCI_EXP_SLTCTL_AIC | |
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PCI_EXP_SLTCTL_HPIE | |
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PCI_EXP_SLTCTL_CCIE | |
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PCI_EXP_SLTCTL_PDCE | |
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PCI_EXP_SLTCTL_ABPE); |
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pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, |
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PCI_EXP_SLTCTL_PIC_OFF | |
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PCI_EXP_SLTCTL_AIC_OFF); |
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pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, |
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PCI_EXP_SLTSTA_EIS |/* on reset,
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the lock is released */
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PCI_EXP_SLTSTA_CC | |
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PCI_EXP_SLTSTA_PDC | |
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PCI_EXP_SLTSTA_ABP); |
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hotplug_event_update_event_status(dev); |
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} |
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void pcie_cap_slot_write_config(PCIDevice *dev,
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uint32_t addr, uint32_t val, int len)
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{ |
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uint32_t pos = dev->exp.exp_cap; |
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uint8_t *exp_cap = dev->config + pos; |
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uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); |
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|
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if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) { |
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return;
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} |
323 |
|
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if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
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PCI_EXP_SLTCTL_EIC)) { |
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sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */
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pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta); |
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PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: "
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"sltsta -> 0x%02"PRIx16"\n", |
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sltsta); |
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} |
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hotplug_event_notify(dev); |
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|
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/*
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* 6.7.3.2 Command Completed Events
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*
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* Software issues a command to a hot-plug capable Downstream Port by
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* issuing a write transaction that targets any portion of the Port’s Slot
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* Control register. A single write to the Slot Control register is
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* considered to be a single command, even if the write affects more than
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* one field in the Slot Control register. In response to this transaction,
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* the Port must carry out the requested actions and then set the
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* associated status field for the command completed event. */
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|
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/* Real hardware might take a while to complete requested command because
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* physical movement would be involved like locking the electromechanical
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* lock. However in our case, command is completed instantaneously above,
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* so send a command completion event right now.
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*/
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pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI); |
352 |
} |
353 |
|
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int pcie_cap_slot_post_load(void *opaque, int version_id) |
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{ |
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PCIDevice *dev = opaque; |
357 |
hotplug_event_update_event_status(dev); |
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return 0; |
359 |
} |
360 |
|
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void pcie_cap_slot_push_attention_button(PCIDevice *dev)
|
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{ |
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pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP); |
364 |
} |
365 |
|
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/* root control/capabilities/status. PME isn't emulated for now */
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void pcie_cap_root_init(PCIDevice *dev)
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{ |
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pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL, |
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PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | |
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PCI_EXP_RTCTL_SEFEE); |
372 |
} |
373 |
|
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void pcie_cap_root_reset(PCIDevice *dev)
|
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{ |
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pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0);
|
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} |
378 |
|
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/*
|
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* TODO: implement FLR:
|
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* Right now sets the bit which indicates FLR is supported.
|
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*/
|
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/* function level reset(FLR) */
|
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void pcie_cap_flr_init(PCIDevice *dev)
|
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{ |
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pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP, |
387 |
PCI_EXP_DEVCAP_FLR); |
388 |
|
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/* Although reading BCR_FLR returns always 0,
|
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* the bit is made writable here in order to detect the 1b is written
|
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* pcie_cap_flr_write_config() test-and-clear the bit, so
|
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* this bit always returns 0 to the guest.
|
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*/
|
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pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL, |
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PCI_EXP_DEVCTL_BCR_FLR); |
396 |
} |
397 |
|
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void pcie_cap_flr_write_config(PCIDevice *dev,
|
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uint32_t addr, uint32_t val, int len)
|
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{ |
401 |
uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; |
402 |
if (pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR)) {
|
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/* TODO: implement FLR */
|
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} |
405 |
} |
406 |
|
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/* Alternative Routing-ID Interpretation (ARI) */
|
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/* ari forwarding support for down stream port */
|
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void pcie_cap_ari_init(PCIDevice *dev)
|
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{ |
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uint32_t pos = dev->exp.exp_cap; |
412 |
pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2, |
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PCI_EXP_DEVCAP2_ARI); |
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pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2, |
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PCI_EXP_DEVCTL2_ARI); |
416 |
} |
417 |
|
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void pcie_cap_ari_reset(PCIDevice *dev)
|
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{ |
420 |
uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2; |
421 |
pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI); |
422 |
} |
423 |
|
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bool pcie_cap_is_ari_enabled(const PCIDevice *dev) |
425 |
{ |
426 |
if (!pci_is_express(dev)) {
|
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return false; |
428 |
} |
429 |
if (!dev->exp.exp_cap) {
|
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return false; |
431 |
} |
432 |
|
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return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) &
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PCI_EXP_DEVCTL2_ARI; |
435 |
} |
436 |
|
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/**************************************************************************
|
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* pci express extended capability allocation functions
|
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* uint16_t ext_cap_id (16 bit)
|
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* uint8_t cap_ver (4 bit)
|
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* uint16_t cap_offset (12 bit)
|
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* uint16_t ext_cap_size
|
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*/
|
444 |
|
445 |
static uint16_t pcie_find_capability_list(PCIDevice *dev, uint16_t cap_id,
|
446 |
uint16_t *prev_p) |
447 |
{ |
448 |
uint16_t prev = 0;
|
449 |
uint16_t next; |
450 |
uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE); |
451 |
|
452 |
if (!header) {
|
453 |
/* no extended capability */
|
454 |
next = 0;
|
455 |
goto out;
|
456 |
} |
457 |
for (next = PCI_CONFIG_SPACE_SIZE; next;
|
458 |
prev = next, next = PCI_EXT_CAP_NEXT(header)) { |
459 |
|
460 |
assert(next >= PCI_CONFIG_SPACE_SIZE); |
461 |
assert(next <= PCIE_CONFIG_SPACE_SIZE - 8);
|
462 |
|
463 |
header = pci_get_long(dev->config + next); |
464 |
if (PCI_EXT_CAP_ID(header) == cap_id) {
|
465 |
break;
|
466 |
} |
467 |
} |
468 |
|
469 |
out:
|
470 |
if (prev_p) {
|
471 |
*prev_p = prev; |
472 |
} |
473 |
return next;
|
474 |
} |
475 |
|
476 |
uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id) |
477 |
{ |
478 |
return pcie_find_capability_list(dev, cap_id, NULL); |
479 |
} |
480 |
|
481 |
static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next) |
482 |
{ |
483 |
uint16_t header = pci_get_long(dev->config + pos); |
484 |
assert(!(next & (PCI_EXT_CAP_ALIGN - 1)));
|
485 |
header = (header & ~PCI_EXT_CAP_NEXT_MASK) | |
486 |
((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK); |
487 |
pci_set_long(dev->config + pos, header); |
488 |
} |
489 |
|
490 |
/*
|
491 |
* caller must supply valid (offset, size) * such that the range shouldn't
|
492 |
* overlap with other capability or other registers.
|
493 |
* This function doesn't check it.
|
494 |
*/
|
495 |
void pcie_add_capability(PCIDevice *dev,
|
496 |
uint16_t cap_id, uint8_t cap_ver, |
497 |
uint16_t offset, uint16_t size) |
498 |
{ |
499 |
uint32_t header; |
500 |
uint16_t next; |
501 |
|
502 |
assert(offset >= PCI_CONFIG_SPACE_SIZE); |
503 |
assert(offset < offset + size); |
504 |
assert(offset + size < PCIE_CONFIG_SPACE_SIZE); |
505 |
assert(size >= 8);
|
506 |
assert(pci_is_express(dev)); |
507 |
|
508 |
if (offset == PCI_CONFIG_SPACE_SIZE) {
|
509 |
header = pci_get_long(dev->config + offset); |
510 |
next = PCI_EXT_CAP_NEXT(header); |
511 |
} else {
|
512 |
uint16_t prev; |
513 |
|
514 |
/* 0 is reserved cap id. use internally to find the last capability
|
515 |
in the linked list */
|
516 |
next = pcie_find_capability_list(dev, 0, &prev);
|
517 |
|
518 |
assert(prev >= PCI_CONFIG_SPACE_SIZE); |
519 |
assert(next == 0);
|
520 |
pcie_ext_cap_set_next(dev, prev, offset); |
521 |
} |
522 |
pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, next)); |
523 |
|
524 |
/* Make capability read-only by default */
|
525 |
memset(dev->wmask + offset, 0, size);
|
526 |
memset(dev->w1cmask + offset, 0, size);
|
527 |
/* Check capability by default */
|
528 |
memset(dev->cmask + offset, 0xFF, size);
|
529 |
} |
530 |
|
531 |
/**************************************************************************
|
532 |
* pci express extended capability helper functions
|
533 |
*/
|
534 |
|
535 |
/* ARI */
|
536 |
void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn)
|
537 |
{ |
538 |
pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER, |
539 |
offset, PCI_ARI_SIZEOF); |
540 |
pci_set_long(dev->config + offset + PCI_ARI_CAP, PCI_ARI_CAP_NFN(nextfn)); |
541 |
} |