root / hw / vga.c @ 80cabfad
History | View | Annotate | Download (47 kB)
1 | e89f66ec | bellard | /*
|
---|---|---|---|
2 | 4fa0f5d2 | bellard | * QEMU VGA Emulator.
|
3 | e89f66ec | bellard | *
|
4 | e89f66ec | bellard | * Copyright (c) 2003 Fabrice Bellard
|
5 | e89f66ec | bellard | *
|
6 | e89f66ec | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | e89f66ec | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | e89f66ec | bellard | * in the Software without restriction, including without limitation the rights
|
9 | e89f66ec | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | e89f66ec | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | e89f66ec | bellard | * furnished to do so, subject to the following conditions:
|
12 | e89f66ec | bellard | *
|
13 | e89f66ec | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | e89f66ec | bellard | * all copies or substantial portions of the Software.
|
15 | e89f66ec | bellard | *
|
16 | e89f66ec | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | e89f66ec | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | e89f66ec | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | e89f66ec | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | e89f66ec | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | e89f66ec | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | e89f66ec | bellard | * THE SOFTWARE.
|
23 | e89f66ec | bellard | */
|
24 | e89f66ec | bellard | #include <stdlib.h> |
25 | e89f66ec | bellard | #include <stdio.h> |
26 | e89f66ec | bellard | #include <stdarg.h> |
27 | e89f66ec | bellard | #include <string.h> |
28 | e89f66ec | bellard | #include <getopt.h> |
29 | e89f66ec | bellard | #include <inttypes.h> |
30 | e89f66ec | bellard | #include <unistd.h> |
31 | e89f66ec | bellard | #include <sys/mman.h> |
32 | e89f66ec | bellard | #include <fcntl.h> |
33 | e89f66ec | bellard | #include <signal.h> |
34 | e89f66ec | bellard | #include <time.h> |
35 | e89f66ec | bellard | #include <sys/time.h> |
36 | e89f66ec | bellard | #include <malloc.h> |
37 | e89f66ec | bellard | #include <termios.h> |
38 | e89f66ec | bellard | #include <sys/poll.h> |
39 | e89f66ec | bellard | #include <errno.h> |
40 | e89f66ec | bellard | #include <sys/wait.h> |
41 | e89f66ec | bellard | #include <netinet/in.h> |
42 | e89f66ec | bellard | |
43 | b9f19507 | bellard | #define NO_THUNK_TYPE_SIZE
|
44 | b9f19507 | bellard | #include "thunk.h" |
45 | b9f19507 | bellard | |
46 | 6180a181 | bellard | #include "cpu.h" |
47 | 6180a181 | bellard | #include "exec-all.h" |
48 | e89f66ec | bellard | |
49 | e89f66ec | bellard | #include "vl.h" |
50 | e89f66ec | bellard | |
51 | e89f66ec | bellard | //#define DEBUG_VGA
|
52 | 17b0018b | bellard | //#define DEBUG_VGA_MEM
|
53 | a41bc9af | bellard | //#define DEBUG_VGA_REG
|
54 | a41bc9af | bellard | |
55 | a41bc9af | bellard | //#define DEBUG_S3
|
56 | 4fa0f5d2 | bellard | //#define DEBUG_BOCHS_VBE
|
57 | 4fa0f5d2 | bellard | |
58 | a41bc9af | bellard | #define CONFIG_S3VGA
|
59 | e89f66ec | bellard | |
60 | e89f66ec | bellard | #define MSR_COLOR_EMULATION 0x01 |
61 | e89f66ec | bellard | #define MSR_PAGE_SELECT 0x20 |
62 | e89f66ec | bellard | |
63 | e89f66ec | bellard | #define ST01_V_RETRACE 0x08 |
64 | e89f66ec | bellard | #define ST01_DISP_ENABLE 0x01 |
65 | e89f66ec | bellard | |
66 | 4fa0f5d2 | bellard | /* bochs VBE support */
|
67 | 4fa0f5d2 | bellard | #define CONFIG_BOCHS_VBE
|
68 | 4fa0f5d2 | bellard | |
69 | 4fa0f5d2 | bellard | #define VBE_DISPI_MAX_XRES 1024 |
70 | 4fa0f5d2 | bellard | #define VBE_DISPI_MAX_YRES 768 |
71 | 4fa0f5d2 | bellard | |
72 | 4fa0f5d2 | bellard | #define VBE_DISPI_INDEX_ID 0x0 |
73 | 4fa0f5d2 | bellard | #define VBE_DISPI_INDEX_XRES 0x1 |
74 | 4fa0f5d2 | bellard | #define VBE_DISPI_INDEX_YRES 0x2 |
75 | 4fa0f5d2 | bellard | #define VBE_DISPI_INDEX_BPP 0x3 |
76 | 4fa0f5d2 | bellard | #define VBE_DISPI_INDEX_ENABLE 0x4 |
77 | 4fa0f5d2 | bellard | #define VBE_DISPI_INDEX_BANK 0x5 |
78 | 4fa0f5d2 | bellard | #define VBE_DISPI_INDEX_VIRT_WIDTH 0x6 |
79 | 4fa0f5d2 | bellard | #define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7 |
80 | 4fa0f5d2 | bellard | #define VBE_DISPI_INDEX_X_OFFSET 0x8 |
81 | 4fa0f5d2 | bellard | #define VBE_DISPI_INDEX_Y_OFFSET 0x9 |
82 | 4fa0f5d2 | bellard | #define VBE_DISPI_INDEX_NB 0xa |
83 | 4fa0f5d2 | bellard | |
84 | 4fa0f5d2 | bellard | #define VBE_DISPI_ID0 0xB0C0 |
85 | 4fa0f5d2 | bellard | #define VBE_DISPI_ID1 0xB0C1 |
86 | 4fa0f5d2 | bellard | #define VBE_DISPI_ID2 0xB0C2 |
87 | 4fa0f5d2 | bellard | |
88 | 4fa0f5d2 | bellard | #define VBE_DISPI_DISABLED 0x00 |
89 | 4fa0f5d2 | bellard | #define VBE_DISPI_ENABLED 0x01 |
90 | 4fa0f5d2 | bellard | #define VBE_DISPI_LFB_ENABLED 0x40 |
91 | 4fa0f5d2 | bellard | #define VBE_DISPI_NOCLEARMEM 0x80 |
92 | 4fa0f5d2 | bellard | |
93 | 4fa0f5d2 | bellard | #define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000 |
94 | 4fa0f5d2 | bellard | |
95 | e89f66ec | bellard | typedef struct VGAState { |
96 | e89f66ec | bellard | uint8_t *vram_ptr; |
97 | e89f66ec | bellard | unsigned long vram_offset; |
98 | e89f66ec | bellard | unsigned int vram_size; |
99 | e89f66ec | bellard | uint32_t latch; |
100 | e89f66ec | bellard | uint8_t sr_index; |
101 | e89f66ec | bellard | uint8_t sr[8];
|
102 | e89f66ec | bellard | uint8_t gr_index; |
103 | e89f66ec | bellard | uint8_t gr[16];
|
104 | e89f66ec | bellard | uint8_t ar_index; |
105 | e89f66ec | bellard | uint8_t ar[21];
|
106 | e89f66ec | bellard | int ar_flip_flop;
|
107 | e89f66ec | bellard | uint8_t cr_index; |
108 | e89f66ec | bellard | uint8_t cr[256]; /* CRT registers */ |
109 | e89f66ec | bellard | uint8_t msr; /* Misc Output Register */
|
110 | e89f66ec | bellard | uint8_t fcr; /* Feature Control Register */
|
111 | e89f66ec | bellard | uint8_t st00; /* status 0 */
|
112 | e89f66ec | bellard | uint8_t st01; /* status 1 */
|
113 | e89f66ec | bellard | uint8_t dac_state; |
114 | e89f66ec | bellard | uint8_t dac_sub_index; |
115 | e89f66ec | bellard | uint8_t dac_read_index; |
116 | e89f66ec | bellard | uint8_t dac_write_index; |
117 | e89f66ec | bellard | uint8_t dac_cache[3]; /* used when writing */ |
118 | e89f66ec | bellard | uint8_t palette[768];
|
119 | cae61cef | bellard | uint32_t bank_offset; |
120 | 4fa0f5d2 | bellard | #ifdef CONFIG_BOCHS_VBE
|
121 | 4fa0f5d2 | bellard | uint16_t vbe_index; |
122 | 4fa0f5d2 | bellard | uint16_t vbe_regs[VBE_DISPI_INDEX_NB]; |
123 | 4fa0f5d2 | bellard | uint32_t vbe_start_addr; |
124 | 4fa0f5d2 | bellard | uint32_t vbe_line_offset; |
125 | cae61cef | bellard | uint32_t vbe_bank_mask; |
126 | 4fa0f5d2 | bellard | #endif
|
127 | e89f66ec | bellard | /* display refresh support */
|
128 | e89f66ec | bellard | DisplayState *ds; |
129 | e89f66ec | bellard | uint32_t font_offsets[2];
|
130 | e89f66ec | bellard | int graphic_mode;
|
131 | 17b0018b | bellard | uint8_t shift_control; |
132 | 17b0018b | bellard | uint8_t double_scan; |
133 | e89f66ec | bellard | uint32_t line_offset; |
134 | e89f66ec | bellard | uint32_t line_compare; |
135 | e89f66ec | bellard | uint32_t start_addr; |
136 | e89f66ec | bellard | uint8_t last_cw, last_ch; |
137 | e89f66ec | bellard | uint32_t last_width, last_height; |
138 | e89f66ec | bellard | uint8_t cursor_start, cursor_end; |
139 | e89f66ec | bellard | uint32_t cursor_offset; |
140 | 17b0018b | bellard | unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned b); |
141 | 39cf7803 | bellard | /* tell for each page if it has been updated since the last time */
|
142 | e89f66ec | bellard | uint32_t last_palette[256];
|
143 | 17b0018b | bellard | #define CH_ATTR_SIZE (160 * 100) |
144 | e89f66ec | bellard | uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
|
145 | e89f66ec | bellard | } VGAState; |
146 | e89f66ec | bellard | |
147 | e89f66ec | bellard | /* force some bits to zero */
|
148 | e89f66ec | bellard | static const uint8_t sr_mask[8] = { |
149 | e89f66ec | bellard | (uint8_t)~0xfc,
|
150 | e89f66ec | bellard | (uint8_t)~0xc2,
|
151 | e89f66ec | bellard | (uint8_t)~0xf0,
|
152 | e89f66ec | bellard | (uint8_t)~0xc0,
|
153 | e89f66ec | bellard | (uint8_t)~0xf1,
|
154 | e89f66ec | bellard | (uint8_t)~0xff,
|
155 | e89f66ec | bellard | (uint8_t)~0xff,
|
156 | e89f66ec | bellard | (uint8_t)~0x00,
|
157 | e89f66ec | bellard | }; |
158 | e89f66ec | bellard | |
159 | e89f66ec | bellard | static const uint8_t gr_mask[16] = { |
160 | e89f66ec | bellard | (uint8_t)~0xf0, /* 0x00 */ |
161 | e89f66ec | bellard | (uint8_t)~0xf0, /* 0x01 */ |
162 | e89f66ec | bellard | (uint8_t)~0xf0, /* 0x02 */ |
163 | e89f66ec | bellard | (uint8_t)~0xe0, /* 0x03 */ |
164 | e89f66ec | bellard | (uint8_t)~0xfc, /* 0x04 */ |
165 | e89f66ec | bellard | (uint8_t)~0x84, /* 0x05 */ |
166 | e89f66ec | bellard | (uint8_t)~0xf0, /* 0x06 */ |
167 | e89f66ec | bellard | (uint8_t)~0xf0, /* 0x07 */ |
168 | e89f66ec | bellard | (uint8_t)~0x00, /* 0x08 */ |
169 | e89f66ec | bellard | (uint8_t)~0xff, /* 0x09 */ |
170 | e89f66ec | bellard | (uint8_t)~0xff, /* 0x0a */ |
171 | e89f66ec | bellard | (uint8_t)~0xff, /* 0x0b */ |
172 | e89f66ec | bellard | (uint8_t)~0xff, /* 0x0c */ |
173 | e89f66ec | bellard | (uint8_t)~0xff, /* 0x0d */ |
174 | e89f66ec | bellard | (uint8_t)~0xff, /* 0x0e */ |
175 | e89f66ec | bellard | (uint8_t)~0xff, /* 0x0f */ |
176 | e89f66ec | bellard | }; |
177 | e89f66ec | bellard | |
178 | e89f66ec | bellard | #define cbswap_32(__x) \
|
179 | e89f66ec | bellard | ((uint32_t)( \ |
180 | e89f66ec | bellard | (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \ |
181 | e89f66ec | bellard | (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \ |
182 | e89f66ec | bellard | (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \ |
183 | e89f66ec | bellard | (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) )) |
184 | e89f66ec | bellard | |
185 | b8ed223b | bellard | #ifdef WORDS_BIGENDIAN
|
186 | e89f66ec | bellard | #define PAT(x) cbswap_32(x)
|
187 | e89f66ec | bellard | #else
|
188 | e89f66ec | bellard | #define PAT(x) (x)
|
189 | e89f66ec | bellard | #endif
|
190 | e89f66ec | bellard | |
191 | b8ed223b | bellard | #ifdef WORDS_BIGENDIAN
|
192 | b8ed223b | bellard | #define BIG 1 |
193 | b8ed223b | bellard | #else
|
194 | b8ed223b | bellard | #define BIG 0 |
195 | b8ed223b | bellard | #endif
|
196 | b8ed223b | bellard | |
197 | b8ed223b | bellard | #ifdef WORDS_BIGENDIAN
|
198 | b8ed223b | bellard | #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff) |
199 | b8ed223b | bellard | #else
|
200 | b8ed223b | bellard | #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff) |
201 | b8ed223b | bellard | #endif
|
202 | b8ed223b | bellard | |
203 | e89f66ec | bellard | static const uint32_t mask16[16] = { |
204 | e89f66ec | bellard | PAT(0x00000000),
|
205 | e89f66ec | bellard | PAT(0x000000ff),
|
206 | e89f66ec | bellard | PAT(0x0000ff00),
|
207 | e89f66ec | bellard | PAT(0x0000ffff),
|
208 | e89f66ec | bellard | PAT(0x00ff0000),
|
209 | e89f66ec | bellard | PAT(0x00ff00ff),
|
210 | e89f66ec | bellard | PAT(0x00ffff00),
|
211 | e89f66ec | bellard | PAT(0x00ffffff),
|
212 | e89f66ec | bellard | PAT(0xff000000),
|
213 | e89f66ec | bellard | PAT(0xff0000ff),
|
214 | e89f66ec | bellard | PAT(0xff00ff00),
|
215 | e89f66ec | bellard | PAT(0xff00ffff),
|
216 | e89f66ec | bellard | PAT(0xffff0000),
|
217 | e89f66ec | bellard | PAT(0xffff00ff),
|
218 | e89f66ec | bellard | PAT(0xffffff00),
|
219 | e89f66ec | bellard | PAT(0xffffffff),
|
220 | e89f66ec | bellard | }; |
221 | e89f66ec | bellard | |
222 | e89f66ec | bellard | #undef PAT
|
223 | e89f66ec | bellard | |
224 | b8ed223b | bellard | #ifdef WORDS_BIGENDIAN
|
225 | e89f66ec | bellard | #define PAT(x) (x)
|
226 | e89f66ec | bellard | #else
|
227 | e89f66ec | bellard | #define PAT(x) cbswap_32(x)
|
228 | e89f66ec | bellard | #endif
|
229 | e89f66ec | bellard | |
230 | e89f66ec | bellard | static const uint32_t dmask16[16] = { |
231 | e89f66ec | bellard | PAT(0x00000000),
|
232 | e89f66ec | bellard | PAT(0x000000ff),
|
233 | e89f66ec | bellard | PAT(0x0000ff00),
|
234 | e89f66ec | bellard | PAT(0x0000ffff),
|
235 | e89f66ec | bellard | PAT(0x00ff0000),
|
236 | e89f66ec | bellard | PAT(0x00ff00ff),
|
237 | e89f66ec | bellard | PAT(0x00ffff00),
|
238 | e89f66ec | bellard | PAT(0x00ffffff),
|
239 | e89f66ec | bellard | PAT(0xff000000),
|
240 | e89f66ec | bellard | PAT(0xff0000ff),
|
241 | e89f66ec | bellard | PAT(0xff00ff00),
|
242 | e89f66ec | bellard | PAT(0xff00ffff),
|
243 | e89f66ec | bellard | PAT(0xffff0000),
|
244 | e89f66ec | bellard | PAT(0xffff00ff),
|
245 | e89f66ec | bellard | PAT(0xffffff00),
|
246 | e89f66ec | bellard | PAT(0xffffffff),
|
247 | e89f66ec | bellard | }; |
248 | e89f66ec | bellard | |
249 | e89f66ec | bellard | static const uint32_t dmask4[4] = { |
250 | e89f66ec | bellard | PAT(0x00000000),
|
251 | e89f66ec | bellard | PAT(0x0000ffff),
|
252 | e89f66ec | bellard | PAT(0xffff0000),
|
253 | e89f66ec | bellard | PAT(0xffffffff),
|
254 | e89f66ec | bellard | }; |
255 | e89f66ec | bellard | |
256 | e89f66ec | bellard | static uint32_t expand4[256]; |
257 | e89f66ec | bellard | static uint16_t expand2[256]; |
258 | 17b0018b | bellard | static uint8_t expand4to8[16]; |
259 | e89f66ec | bellard | |
260 | e89f66ec | bellard | VGAState vga_state; |
261 | e89f66ec | bellard | int vga_io_memory;
|
262 | e89f66ec | bellard | |
263 | 7138fcfb | bellard | static uint32_t vga_ioport_read(CPUState *env, uint32_t addr)
|
264 | e89f66ec | bellard | { |
265 | e89f66ec | bellard | VGAState *s = &vga_state; |
266 | e89f66ec | bellard | int val, index;
|
267 | e89f66ec | bellard | |
268 | e89f66ec | bellard | /* check port range access depending on color/monochrome mode */
|
269 | e89f66ec | bellard | if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) || |
270 | e89f66ec | bellard | (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION))) { |
271 | e89f66ec | bellard | val = 0xff;
|
272 | e89f66ec | bellard | } else {
|
273 | e89f66ec | bellard | switch(addr) {
|
274 | e89f66ec | bellard | case 0x3c0: |
275 | e89f66ec | bellard | if (s->ar_flip_flop == 0) { |
276 | e89f66ec | bellard | val = s->ar_index; |
277 | e89f66ec | bellard | } else {
|
278 | e89f66ec | bellard | val = 0;
|
279 | e89f66ec | bellard | } |
280 | e89f66ec | bellard | break;
|
281 | e89f66ec | bellard | case 0x3c1: |
282 | e89f66ec | bellard | index = s->ar_index & 0x1f;
|
283 | e89f66ec | bellard | if (index < 21) |
284 | e89f66ec | bellard | val = s->ar[index]; |
285 | e89f66ec | bellard | else
|
286 | e89f66ec | bellard | val = 0;
|
287 | e89f66ec | bellard | break;
|
288 | e89f66ec | bellard | case 0x3c2: |
289 | e89f66ec | bellard | val = s->st00; |
290 | e89f66ec | bellard | break;
|
291 | e89f66ec | bellard | case 0x3c4: |
292 | e89f66ec | bellard | val = s->sr_index; |
293 | e89f66ec | bellard | break;
|
294 | e89f66ec | bellard | case 0x3c5: |
295 | e89f66ec | bellard | val = s->sr[s->sr_index]; |
296 | a41bc9af | bellard | #ifdef DEBUG_VGA_REG
|
297 | a41bc9af | bellard | printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
|
298 | a41bc9af | bellard | #endif
|
299 | e89f66ec | bellard | break;
|
300 | e89f66ec | bellard | case 0x3c7: |
301 | e89f66ec | bellard | val = s->dac_state; |
302 | e89f66ec | bellard | break;
|
303 | e89f66ec | bellard | case 0x3c9: |
304 | e89f66ec | bellard | val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
|
305 | e89f66ec | bellard | if (++s->dac_sub_index == 3) { |
306 | e89f66ec | bellard | s->dac_sub_index = 0;
|
307 | e89f66ec | bellard | s->dac_read_index++; |
308 | e89f66ec | bellard | } |
309 | e89f66ec | bellard | break;
|
310 | e89f66ec | bellard | case 0x3ca: |
311 | e89f66ec | bellard | val = s->fcr; |
312 | e89f66ec | bellard | break;
|
313 | e89f66ec | bellard | case 0x3cc: |
314 | e89f66ec | bellard | val = s->msr; |
315 | e89f66ec | bellard | break;
|
316 | e89f66ec | bellard | case 0x3ce: |
317 | e89f66ec | bellard | val = s->gr_index; |
318 | e89f66ec | bellard | break;
|
319 | e89f66ec | bellard | case 0x3cf: |
320 | e89f66ec | bellard | val = s->gr[s->gr_index]; |
321 | a41bc9af | bellard | #ifdef DEBUG_VGA_REG
|
322 | a41bc9af | bellard | printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
|
323 | a41bc9af | bellard | #endif
|
324 | e89f66ec | bellard | break;
|
325 | e89f66ec | bellard | case 0x3b4: |
326 | e89f66ec | bellard | case 0x3d4: |
327 | e89f66ec | bellard | val = s->cr_index; |
328 | e89f66ec | bellard | break;
|
329 | e89f66ec | bellard | case 0x3b5: |
330 | e89f66ec | bellard | case 0x3d5: |
331 | e89f66ec | bellard | val = s->cr[s->cr_index]; |
332 | a41bc9af | bellard | #ifdef DEBUG_VGA_REG
|
333 | a41bc9af | bellard | printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
|
334 | a41bc9af | bellard | #endif
|
335 | a41bc9af | bellard | #ifdef DEBUG_S3
|
336 | a41bc9af | bellard | if (s->cr_index >= 0x20) |
337 | a41bc9af | bellard | printf("S3: CR read index=0x%x val=0x%x\n",
|
338 | a41bc9af | bellard | s->cr_index, val); |
339 | a41bc9af | bellard | #endif
|
340 | e89f66ec | bellard | break;
|
341 | e89f66ec | bellard | case 0x3ba: |
342 | e89f66ec | bellard | case 0x3da: |
343 | e89f66ec | bellard | /* just toggle to fool polling */
|
344 | e89f66ec | bellard | s->st01 ^= ST01_V_RETRACE | ST01_DISP_ENABLE; |
345 | e89f66ec | bellard | val = s->st01; |
346 | e89f66ec | bellard | s->ar_flip_flop = 0;
|
347 | e89f66ec | bellard | break;
|
348 | e89f66ec | bellard | default:
|
349 | e89f66ec | bellard | val = 0x00;
|
350 | e89f66ec | bellard | break;
|
351 | e89f66ec | bellard | } |
352 | e89f66ec | bellard | } |
353 | 4fa0f5d2 | bellard | #if defined(DEBUG_VGA)
|
354 | e89f66ec | bellard | printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
|
355 | e89f66ec | bellard | #endif
|
356 | e89f66ec | bellard | return val;
|
357 | e89f66ec | bellard | } |
358 | e89f66ec | bellard | |
359 | 7138fcfb | bellard | static void vga_ioport_write(CPUState *env, uint32_t addr, uint32_t val) |
360 | e89f66ec | bellard | { |
361 | e89f66ec | bellard | VGAState *s = &vga_state; |
362 | e89f66ec | bellard | int index, v;
|
363 | e89f66ec | bellard | |
364 | e89f66ec | bellard | /* check port range access depending on color/monochrome mode */
|
365 | e89f66ec | bellard | if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) || |
366 | e89f66ec | bellard | (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION))) |
367 | e89f66ec | bellard | return;
|
368 | e89f66ec | bellard | |
369 | e89f66ec | bellard | #ifdef DEBUG_VGA
|
370 | e89f66ec | bellard | printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
|
371 | e89f66ec | bellard | #endif
|
372 | e89f66ec | bellard | |
373 | e89f66ec | bellard | switch(addr) {
|
374 | e89f66ec | bellard | case 0x3c0: |
375 | e89f66ec | bellard | if (s->ar_flip_flop == 0) { |
376 | e89f66ec | bellard | val &= 0x3f;
|
377 | e89f66ec | bellard | s->ar_index = val; |
378 | e89f66ec | bellard | } else {
|
379 | e89f66ec | bellard | index = s->ar_index & 0x1f;
|
380 | e89f66ec | bellard | switch(index) {
|
381 | e89f66ec | bellard | case 0x00 ... 0x0f: |
382 | e89f66ec | bellard | s->ar[index] = val & 0x3f;
|
383 | e89f66ec | bellard | break;
|
384 | e89f66ec | bellard | case 0x10: |
385 | e89f66ec | bellard | s->ar[index] = val & ~0x10;
|
386 | e89f66ec | bellard | break;
|
387 | e89f66ec | bellard | case 0x11: |
388 | e89f66ec | bellard | s->ar[index] = val; |
389 | e89f66ec | bellard | break;
|
390 | e89f66ec | bellard | case 0x12: |
391 | e89f66ec | bellard | s->ar[index] = val & ~0xc0;
|
392 | e89f66ec | bellard | break;
|
393 | e89f66ec | bellard | case 0x13: |
394 | e89f66ec | bellard | s->ar[index] = val & ~0xf0;
|
395 | e89f66ec | bellard | break;
|
396 | e89f66ec | bellard | case 0x14: |
397 | e89f66ec | bellard | s->ar[index] = val & ~0xf0;
|
398 | e89f66ec | bellard | break;
|
399 | e89f66ec | bellard | default:
|
400 | e89f66ec | bellard | break;
|
401 | e89f66ec | bellard | } |
402 | e89f66ec | bellard | } |
403 | e89f66ec | bellard | s->ar_flip_flop ^= 1;
|
404 | e89f66ec | bellard | break;
|
405 | e89f66ec | bellard | case 0x3c2: |
406 | e89f66ec | bellard | s->msr = val & ~0x10;
|
407 | e89f66ec | bellard | break;
|
408 | e89f66ec | bellard | case 0x3c4: |
409 | e89f66ec | bellard | s->sr_index = val & 7;
|
410 | e89f66ec | bellard | break;
|
411 | e89f66ec | bellard | case 0x3c5: |
412 | a41bc9af | bellard | #ifdef DEBUG_VGA_REG
|
413 | a41bc9af | bellard | printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
|
414 | a41bc9af | bellard | #endif
|
415 | e89f66ec | bellard | s->sr[s->sr_index] = val & sr_mask[s->sr_index]; |
416 | e89f66ec | bellard | break;
|
417 | e89f66ec | bellard | case 0x3c7: |
418 | e89f66ec | bellard | s->dac_read_index = val; |
419 | e89f66ec | bellard | s->dac_sub_index = 0;
|
420 | e89f66ec | bellard | s->dac_state = 3;
|
421 | e89f66ec | bellard | break;
|
422 | e89f66ec | bellard | case 0x3c8: |
423 | e89f66ec | bellard | s->dac_write_index = val; |
424 | e89f66ec | bellard | s->dac_sub_index = 0;
|
425 | e89f66ec | bellard | s->dac_state = 0;
|
426 | e89f66ec | bellard | break;
|
427 | e89f66ec | bellard | case 0x3c9: |
428 | e89f66ec | bellard | s->dac_cache[s->dac_sub_index] = val; |
429 | e89f66ec | bellard | if (++s->dac_sub_index == 3) { |
430 | e89f66ec | bellard | memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3); |
431 | e89f66ec | bellard | s->dac_sub_index = 0;
|
432 | e89f66ec | bellard | s->dac_write_index++; |
433 | e89f66ec | bellard | } |
434 | e89f66ec | bellard | break;
|
435 | e89f66ec | bellard | case 0x3ce: |
436 | e89f66ec | bellard | s->gr_index = val & 0x0f;
|
437 | e89f66ec | bellard | break;
|
438 | e89f66ec | bellard | case 0x3cf: |
439 | a41bc9af | bellard | #ifdef DEBUG_VGA_REG
|
440 | a41bc9af | bellard | printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
|
441 | a41bc9af | bellard | #endif
|
442 | e89f66ec | bellard | s->gr[s->gr_index] = val & gr_mask[s->gr_index]; |
443 | e89f66ec | bellard | break;
|
444 | e89f66ec | bellard | case 0x3b4: |
445 | e89f66ec | bellard | case 0x3d4: |
446 | e89f66ec | bellard | s->cr_index = val; |
447 | e89f66ec | bellard | break;
|
448 | e89f66ec | bellard | case 0x3b5: |
449 | e89f66ec | bellard | case 0x3d5: |
450 | a41bc9af | bellard | #ifdef DEBUG_VGA_REG
|
451 | a41bc9af | bellard | printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
|
452 | a41bc9af | bellard | #endif
|
453 | e89f66ec | bellard | /* handle CR0-7 protection */
|
454 | e89f66ec | bellard | if ((s->cr[11] & 0x80) && s->cr_index <= 7) { |
455 | e89f66ec | bellard | /* can always write bit 4 of CR7 */
|
456 | e89f66ec | bellard | if (s->cr_index == 7) |
457 | e89f66ec | bellard | s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10); |
458 | e89f66ec | bellard | return;
|
459 | e89f66ec | bellard | } |
460 | e89f66ec | bellard | switch(s->cr_index) {
|
461 | e89f66ec | bellard | case 0x01: /* horizontal display end */ |
462 | e89f66ec | bellard | case 0x07: |
463 | e89f66ec | bellard | case 0x09: |
464 | e89f66ec | bellard | case 0x0c: |
465 | e89f66ec | bellard | case 0x0d: |
466 | e89f66ec | bellard | case 0x12: /* veritcal display end */ |
467 | e89f66ec | bellard | s->cr[s->cr_index] = val; |
468 | e89f66ec | bellard | break;
|
469 | e89f66ec | bellard | |
470 | a41bc9af | bellard | #ifdef CONFIG_S3VGA
|
471 | e89f66ec | bellard | /* S3 registers */
|
472 | e89f66ec | bellard | case 0x2d: |
473 | e89f66ec | bellard | case 0x2e: |
474 | e89f66ec | bellard | case 0x2f: |
475 | e89f66ec | bellard | case 0x30: |
476 | e89f66ec | bellard | /* chip ID, cannot write */
|
477 | e89f66ec | bellard | break;
|
478 | e89f66ec | bellard | case 0x31: |
479 | e89f66ec | bellard | /* update start address */
|
480 | e89f66ec | bellard | s->cr[s->cr_index] = val; |
481 | e89f66ec | bellard | v = (val >> 4) & 3; |
482 | e89f66ec | bellard | s->cr[0x69] = (s->cr[69] & ~0x03) | v; |
483 | e89f66ec | bellard | break;
|
484 | e89f66ec | bellard | case 0x51: |
485 | e89f66ec | bellard | /* update start address */
|
486 | e89f66ec | bellard | s->cr[s->cr_index] = val; |
487 | e89f66ec | bellard | v = val & 3;
|
488 | e89f66ec | bellard | s->cr[0x69] = (s->cr[69] & ~0x0c) | (v << 2); |
489 | e89f66ec | bellard | break;
|
490 | a41bc9af | bellard | #endif
|
491 | e89f66ec | bellard | default:
|
492 | e89f66ec | bellard | s->cr[s->cr_index] = val; |
493 | e89f66ec | bellard | break;
|
494 | e89f66ec | bellard | } |
495 | a41bc9af | bellard | #ifdef DEBUG_S3
|
496 | a41bc9af | bellard | if (s->cr_index >= 0x20) |
497 | a41bc9af | bellard | printf("S3: CR write index=0x%x val=0x%x\n",
|
498 | a41bc9af | bellard | s->cr_index, val); |
499 | a41bc9af | bellard | #endif
|
500 | e89f66ec | bellard | break;
|
501 | e89f66ec | bellard | case 0x3ba: |
502 | e89f66ec | bellard | case 0x3da: |
503 | e89f66ec | bellard | s->fcr = val & 0x10;
|
504 | e89f66ec | bellard | break;
|
505 | e89f66ec | bellard | } |
506 | e89f66ec | bellard | } |
507 | e89f66ec | bellard | |
508 | 4fa0f5d2 | bellard | #ifdef CONFIG_BOCHS_VBE
|
509 | 4fa0f5d2 | bellard | static uint32_t vbe_ioport_read(CPUState *env, uint32_t addr)
|
510 | 4fa0f5d2 | bellard | { |
511 | 4fa0f5d2 | bellard | VGAState *s = &vga_state; |
512 | 4fa0f5d2 | bellard | uint32_t val; |
513 | 4fa0f5d2 | bellard | |
514 | 4fa0f5d2 | bellard | addr &= 1;
|
515 | 4fa0f5d2 | bellard | if (addr == 0) { |
516 | 4fa0f5d2 | bellard | val = s->vbe_index; |
517 | 4fa0f5d2 | bellard | } else {
|
518 | 4fa0f5d2 | bellard | if (s->vbe_index <= VBE_DISPI_INDEX_NB)
|
519 | 4fa0f5d2 | bellard | val = s->vbe_regs[s->vbe_index]; |
520 | 4fa0f5d2 | bellard | else
|
521 | 4fa0f5d2 | bellard | val = 0;
|
522 | 4fa0f5d2 | bellard | #ifdef DEBUG_BOCHS_VBE
|
523 | 4fa0f5d2 | bellard | printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
|
524 | 4fa0f5d2 | bellard | #endif
|
525 | 4fa0f5d2 | bellard | } |
526 | 4fa0f5d2 | bellard | return val;
|
527 | 4fa0f5d2 | bellard | } |
528 | 4fa0f5d2 | bellard | |
529 | 4fa0f5d2 | bellard | static void vbe_ioport_write(CPUState *env, uint32_t addr, uint32_t val) |
530 | 4fa0f5d2 | bellard | { |
531 | 4fa0f5d2 | bellard | VGAState *s = &vga_state; |
532 | 4fa0f5d2 | bellard | |
533 | 4fa0f5d2 | bellard | addr &= 1;
|
534 | 4fa0f5d2 | bellard | if (addr == 0) { |
535 | 4fa0f5d2 | bellard | s->vbe_index = val; |
536 | 4fa0f5d2 | bellard | } else if (s->vbe_index <= VBE_DISPI_INDEX_NB) { |
537 | 4fa0f5d2 | bellard | #ifdef DEBUG_BOCHS_VBE
|
538 | 4fa0f5d2 | bellard | printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
|
539 | 4fa0f5d2 | bellard | #endif
|
540 | 4fa0f5d2 | bellard | switch(s->vbe_index) {
|
541 | 4fa0f5d2 | bellard | case VBE_DISPI_INDEX_ID:
|
542 | cae61cef | bellard | if (val == VBE_DISPI_ID0 ||
|
543 | cae61cef | bellard | val == VBE_DISPI_ID1 || |
544 | cae61cef | bellard | val == VBE_DISPI_ID2) { |
545 | cae61cef | bellard | s->vbe_regs[s->vbe_index] = val; |
546 | cae61cef | bellard | } |
547 | 4fa0f5d2 | bellard | break;
|
548 | 4fa0f5d2 | bellard | case VBE_DISPI_INDEX_XRES:
|
549 | cae61cef | bellard | if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) { |
550 | cae61cef | bellard | s->vbe_regs[s->vbe_index] = val; |
551 | cae61cef | bellard | } |
552 | 4fa0f5d2 | bellard | break;
|
553 | 4fa0f5d2 | bellard | case VBE_DISPI_INDEX_YRES:
|
554 | cae61cef | bellard | if (val <= VBE_DISPI_MAX_YRES) {
|
555 | cae61cef | bellard | s->vbe_regs[s->vbe_index] = val; |
556 | cae61cef | bellard | } |
557 | 4fa0f5d2 | bellard | break;
|
558 | 4fa0f5d2 | bellard | case VBE_DISPI_INDEX_BPP:
|
559 | 4fa0f5d2 | bellard | if (val == 0) |
560 | 4fa0f5d2 | bellard | val = 8;
|
561 | cae61cef | bellard | if (val == 4 || val == 8 || val == 15 || |
562 | cae61cef | bellard | val == 16 || val == 24 || val == 32) { |
563 | cae61cef | bellard | s->vbe_regs[s->vbe_index] = val; |
564 | cae61cef | bellard | } |
565 | 4fa0f5d2 | bellard | break;
|
566 | 4fa0f5d2 | bellard | case VBE_DISPI_INDEX_BANK:
|
567 | cae61cef | bellard | val &= s->vbe_bank_mask; |
568 | cae61cef | bellard | s->vbe_regs[s->vbe_index] = val; |
569 | cae61cef | bellard | s->bank_offset = (val << 16) - 0xa0000; |
570 | 4fa0f5d2 | bellard | break;
|
571 | 4fa0f5d2 | bellard | case VBE_DISPI_INDEX_ENABLE:
|
572 | 4fa0f5d2 | bellard | if (val & VBE_DISPI_ENABLED) {
|
573 | 4fa0f5d2 | bellard | int h, shift_control;
|
574 | 4fa0f5d2 | bellard | |
575 | 4fa0f5d2 | bellard | s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = |
576 | 4fa0f5d2 | bellard | s->vbe_regs[VBE_DISPI_INDEX_XRES]; |
577 | 4fa0f5d2 | bellard | s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = |
578 | 4fa0f5d2 | bellard | s->vbe_regs[VBE_DISPI_INDEX_YRES]; |
579 | 4fa0f5d2 | bellard | s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
|
580 | 4fa0f5d2 | bellard | s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
|
581 | 4fa0f5d2 | bellard | |
582 | 4fa0f5d2 | bellard | if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) |
583 | 4fa0f5d2 | bellard | s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
|
584 | 4fa0f5d2 | bellard | else
|
585 | 4fa0f5d2 | bellard | s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] * |
586 | 4fa0f5d2 | bellard | ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3); |
587 | 4fa0f5d2 | bellard | s->vbe_start_addr = 0;
|
588 | 4fa0f5d2 | bellard | |
589 | 4fa0f5d2 | bellard | /* clear the screen (should be done in BIOS) */
|
590 | 4fa0f5d2 | bellard | if (!(val & VBE_DISPI_NOCLEARMEM)) {
|
591 | 4fa0f5d2 | bellard | memset(s->vram_ptr, 0,
|
592 | 4fa0f5d2 | bellard | s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset); |
593 | 4fa0f5d2 | bellard | } |
594 | 4fa0f5d2 | bellard | |
595 | cae61cef | bellard | /* we initialize the VGA graphic mode (should be done
|
596 | cae61cef | bellard | in BIOS) */
|
597 | cae61cef | bellard | s->gr[0x06] = (s->gr[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */ |
598 | 4fa0f5d2 | bellard | s->cr[0x17] |= 3; /* no CGA modes */ |
599 | 4fa0f5d2 | bellard | s->cr[0x13] = s->vbe_line_offset >> 3; |
600 | 4fa0f5d2 | bellard | /* width */
|
601 | 4fa0f5d2 | bellard | s->cr[0x01] = (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1; |
602 | 4fa0f5d2 | bellard | /* height */
|
603 | 4fa0f5d2 | bellard | h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
|
604 | 4fa0f5d2 | bellard | s->cr[0x12] = h;
|
605 | 4fa0f5d2 | bellard | s->cr[0x07] = (s->cr[0x07] & ~0x42) | |
606 | 4fa0f5d2 | bellard | ((h >> 7) & 0x02) | ((h >> 3) & 0x40); |
607 | 4fa0f5d2 | bellard | /* line compare to 1023 */
|
608 | 4fa0f5d2 | bellard | s->cr[0x18] = 0xff; |
609 | 4fa0f5d2 | bellard | s->cr[0x07] |= 0x10; |
610 | 4fa0f5d2 | bellard | s->cr[0x09] |= 0x40; |
611 | 4fa0f5d2 | bellard | |
612 | 4fa0f5d2 | bellard | if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) { |
613 | 4fa0f5d2 | bellard | shift_control = 0;
|
614 | 4fa0f5d2 | bellard | s->sr[0x01] &= ~8; /* no double line */ |
615 | 4fa0f5d2 | bellard | } else {
|
616 | 4fa0f5d2 | bellard | shift_control = 2;
|
617 | 4fa0f5d2 | bellard | } |
618 | 4fa0f5d2 | bellard | s->gr[0x05] = (s->gr[0x05] & ~0x60) | (shift_control << 5); |
619 | 4fa0f5d2 | bellard | s->cr[0x09] &= ~0x9f; /* no double scan */ |
620 | cae61cef | bellard | s->vbe_regs[s->vbe_index] = val; |
621 | cae61cef | bellard | } else {
|
622 | cae61cef | bellard | /* XXX: the bios should do that */
|
623 | cae61cef | bellard | s->bank_offset = -0xa0000;
|
624 | cae61cef | bellard | } |
625 | cae61cef | bellard | break;
|
626 | cae61cef | bellard | case VBE_DISPI_INDEX_VIRT_WIDTH:
|
627 | cae61cef | bellard | { |
628 | cae61cef | bellard | int w, h, line_offset;
|
629 | cae61cef | bellard | |
630 | cae61cef | bellard | if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
|
631 | cae61cef | bellard | return;
|
632 | cae61cef | bellard | w = val; |
633 | cae61cef | bellard | if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) |
634 | cae61cef | bellard | line_offset = w >> 1;
|
635 | cae61cef | bellard | else
|
636 | cae61cef | bellard | line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3); |
637 | cae61cef | bellard | h = s->vram_size / line_offset; |
638 | cae61cef | bellard | /* XXX: support weird bochs semantics ? */
|
639 | cae61cef | bellard | if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
|
640 | cae61cef | bellard | return;
|
641 | cae61cef | bellard | s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w; |
642 | cae61cef | bellard | s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h; |
643 | cae61cef | bellard | s->vbe_line_offset = line_offset; |
644 | cae61cef | bellard | } |
645 | cae61cef | bellard | break;
|
646 | cae61cef | bellard | case VBE_DISPI_INDEX_X_OFFSET:
|
647 | cae61cef | bellard | case VBE_DISPI_INDEX_Y_OFFSET:
|
648 | cae61cef | bellard | { |
649 | cae61cef | bellard | int x;
|
650 | cae61cef | bellard | s->vbe_regs[s->vbe_index] = val; |
651 | cae61cef | bellard | s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET]; |
652 | cae61cef | bellard | x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET]; |
653 | cae61cef | bellard | if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) |
654 | cae61cef | bellard | s->vbe_start_addr += x >> 1;
|
655 | cae61cef | bellard | else
|
656 | cae61cef | bellard | s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3); |
657 | cae61cef | bellard | s->vbe_start_addr >>= 2;
|
658 | 4fa0f5d2 | bellard | } |
659 | 4fa0f5d2 | bellard | break;
|
660 | 4fa0f5d2 | bellard | default:
|
661 | 4fa0f5d2 | bellard | break;
|
662 | 4fa0f5d2 | bellard | } |
663 | 4fa0f5d2 | bellard | } |
664 | 4fa0f5d2 | bellard | } |
665 | 4fa0f5d2 | bellard | #endif
|
666 | 4fa0f5d2 | bellard | |
667 | e89f66ec | bellard | /* called for accesses between 0xa0000 and 0xc0000 */
|
668 | e89f66ec | bellard | static uint32_t vga_mem_readb(uint32_t addr)
|
669 | e89f66ec | bellard | { |
670 | e89f66ec | bellard | VGAState *s = &vga_state; |
671 | e89f66ec | bellard | int memory_map_mode, plane;
|
672 | e89f66ec | bellard | uint32_t ret; |
673 | e89f66ec | bellard | |
674 | e89f66ec | bellard | /* convert to VGA memory offset */
|
675 | e89f66ec | bellard | memory_map_mode = (s->gr[6] >> 2) & 3; |
676 | e89f66ec | bellard | switch(memory_map_mode) {
|
677 | e89f66ec | bellard | case 0: |
678 | e89f66ec | bellard | addr -= 0xa0000;
|
679 | e89f66ec | bellard | break;
|
680 | e89f66ec | bellard | case 1: |
681 | cae61cef | bellard | if (addr >= 0xb0000) |
682 | e89f66ec | bellard | return 0xff; |
683 | cae61cef | bellard | addr += s->bank_offset; |
684 | e89f66ec | bellard | break;
|
685 | e89f66ec | bellard | case 2: |
686 | e89f66ec | bellard | addr -= 0xb0000;
|
687 | e89f66ec | bellard | if (addr >= 0x8000) |
688 | e89f66ec | bellard | return 0xff; |
689 | e89f66ec | bellard | break;
|
690 | e89f66ec | bellard | default:
|
691 | e89f66ec | bellard | case 3: |
692 | e89f66ec | bellard | addr -= 0xb8000;
|
693 | c92b2e84 | bellard | if (addr >= 0x8000) |
694 | c92b2e84 | bellard | return 0xff; |
695 | e89f66ec | bellard | break;
|
696 | e89f66ec | bellard | } |
697 | e89f66ec | bellard | |
698 | e89f66ec | bellard | if (s->sr[4] & 0x08) { |
699 | e89f66ec | bellard | /* chain 4 mode : simplest access */
|
700 | e89f66ec | bellard | ret = s->vram_ptr[addr]; |
701 | e89f66ec | bellard | } else if (s->gr[5] & 0x10) { |
702 | e89f66ec | bellard | /* odd/even mode (aka text mode mapping) */
|
703 | e89f66ec | bellard | plane = (s->gr[4] & 2) | (addr & 1); |
704 | e89f66ec | bellard | ret = s->vram_ptr[((addr & ~1) << 1) | plane]; |
705 | e89f66ec | bellard | } else {
|
706 | e89f66ec | bellard | /* standard VGA latched access */
|
707 | e89f66ec | bellard | s->latch = ((uint32_t *)s->vram_ptr)[addr]; |
708 | e89f66ec | bellard | |
709 | e89f66ec | bellard | if (!(s->gr[5] & 0x08)) { |
710 | e89f66ec | bellard | /* read mode 0 */
|
711 | e89f66ec | bellard | plane = s->gr[4];
|
712 | b8ed223b | bellard | ret = GET_PLANE(s->latch, plane); |
713 | e89f66ec | bellard | } else {
|
714 | e89f66ec | bellard | /* read mode 1 */
|
715 | e89f66ec | bellard | ret = (s->latch ^ mask16[s->gr[2]]) & mask16[s->gr[7]]; |
716 | e89f66ec | bellard | ret |= ret >> 16;
|
717 | e89f66ec | bellard | ret |= ret >> 8;
|
718 | e89f66ec | bellard | ret = (~ret) & 0xff;
|
719 | e89f66ec | bellard | } |
720 | e89f66ec | bellard | } |
721 | e89f66ec | bellard | return ret;
|
722 | e89f66ec | bellard | } |
723 | e89f66ec | bellard | |
724 | e89f66ec | bellard | static uint32_t vga_mem_readw(uint32_t addr)
|
725 | e89f66ec | bellard | { |
726 | e89f66ec | bellard | uint32_t v; |
727 | e89f66ec | bellard | v = vga_mem_readb(addr); |
728 | e89f66ec | bellard | v |= vga_mem_readb(addr + 1) << 8; |
729 | e89f66ec | bellard | return v;
|
730 | e89f66ec | bellard | } |
731 | e89f66ec | bellard | |
732 | e89f66ec | bellard | static uint32_t vga_mem_readl(uint32_t addr)
|
733 | e89f66ec | bellard | { |
734 | e89f66ec | bellard | uint32_t v; |
735 | e89f66ec | bellard | v = vga_mem_readb(addr); |
736 | e89f66ec | bellard | v |= vga_mem_readb(addr + 1) << 8; |
737 | e89f66ec | bellard | v |= vga_mem_readb(addr + 2) << 16; |
738 | e89f66ec | bellard | v |= vga_mem_readb(addr + 3) << 24; |
739 | e89f66ec | bellard | return v;
|
740 | e89f66ec | bellard | } |
741 | e89f66ec | bellard | |
742 | e89f66ec | bellard | /* called for accesses between 0xa0000 and 0xc0000 */
|
743 | 4fa0f5d2 | bellard | void vga_mem_writeb(uint32_t addr, uint32_t val, uint32_t vaddr)
|
744 | e89f66ec | bellard | { |
745 | e89f66ec | bellard | VGAState *s = &vga_state; |
746 | e89f66ec | bellard | int memory_map_mode, plane, write_mode, b, func_select;
|
747 | e89f66ec | bellard | uint32_t write_mask, bit_mask, set_mask; |
748 | e89f66ec | bellard | |
749 | 17b0018b | bellard | #ifdef DEBUG_VGA_MEM
|
750 | e89f66ec | bellard | printf("vga: [0x%x] = 0x%02x\n", addr, val);
|
751 | e89f66ec | bellard | #endif
|
752 | e89f66ec | bellard | /* convert to VGA memory offset */
|
753 | e89f66ec | bellard | memory_map_mode = (s->gr[6] >> 2) & 3; |
754 | e89f66ec | bellard | switch(memory_map_mode) {
|
755 | e89f66ec | bellard | case 0: |
756 | e89f66ec | bellard | addr -= 0xa0000;
|
757 | e89f66ec | bellard | break;
|
758 | e89f66ec | bellard | case 1: |
759 | cae61cef | bellard | if (addr >= 0xb0000) |
760 | e89f66ec | bellard | return;
|
761 | cae61cef | bellard | addr += s->bank_offset; |
762 | e89f66ec | bellard | break;
|
763 | e89f66ec | bellard | case 2: |
764 | e89f66ec | bellard | addr -= 0xb0000;
|
765 | e89f66ec | bellard | if (addr >= 0x8000) |
766 | e89f66ec | bellard | return;
|
767 | e89f66ec | bellard | break;
|
768 | e89f66ec | bellard | default:
|
769 | e89f66ec | bellard | case 3: |
770 | e89f66ec | bellard | addr -= 0xb8000;
|
771 | c92b2e84 | bellard | if (addr >= 0x8000) |
772 | c92b2e84 | bellard | return;
|
773 | e89f66ec | bellard | break;
|
774 | e89f66ec | bellard | } |
775 | e89f66ec | bellard | |
776 | e89f66ec | bellard | if (s->sr[4] & 0x08) { |
777 | e89f66ec | bellard | /* chain 4 mode : simplest access */
|
778 | e89f66ec | bellard | plane = addr & 3;
|
779 | e89f66ec | bellard | if (s->sr[2] & (1 << plane)) { |
780 | e89f66ec | bellard | s->vram_ptr[addr] = val; |
781 | 17b0018b | bellard | #ifdef DEBUG_VGA_MEM
|
782 | e89f66ec | bellard | printf("vga: chain4: [0x%x]\n", addr);
|
783 | e89f66ec | bellard | #endif
|
784 | 4fa0f5d2 | bellard | cpu_physical_memory_set_dirty(s->vram_offset + addr); |
785 | e89f66ec | bellard | } |
786 | e89f66ec | bellard | } else if (s->gr[5] & 0x10) { |
787 | e89f66ec | bellard | /* odd/even mode (aka text mode mapping) */
|
788 | e89f66ec | bellard | plane = (s->gr[4] & 2) | (addr & 1); |
789 | e89f66ec | bellard | if (s->sr[2] & (1 << plane)) { |
790 | e89f66ec | bellard | addr = ((addr & ~1) << 1) | plane; |
791 | e89f66ec | bellard | s->vram_ptr[addr] = val; |
792 | 17b0018b | bellard | #ifdef DEBUG_VGA_MEM
|
793 | e89f66ec | bellard | printf("vga: odd/even: [0x%x]\n", addr);
|
794 | e89f66ec | bellard | #endif
|
795 | 4fa0f5d2 | bellard | cpu_physical_memory_set_dirty(s->vram_offset + addr); |
796 | e89f66ec | bellard | } |
797 | e89f66ec | bellard | } else {
|
798 | e89f66ec | bellard | /* standard VGA latched access */
|
799 | e89f66ec | bellard | write_mode = s->gr[5] & 3; |
800 | e89f66ec | bellard | switch(write_mode) {
|
801 | e89f66ec | bellard | default:
|
802 | e89f66ec | bellard | case 0: |
803 | e89f66ec | bellard | /* rotate */
|
804 | e89f66ec | bellard | b = s->gr[3] & 7; |
805 | e89f66ec | bellard | val = ((val >> b) | (val << (8 - b))) & 0xff; |
806 | e89f66ec | bellard | val |= val << 8;
|
807 | e89f66ec | bellard | val |= val << 16;
|
808 | e89f66ec | bellard | |
809 | e89f66ec | bellard | /* apply set/reset mask */
|
810 | e89f66ec | bellard | set_mask = mask16[s->gr[1]];
|
811 | e89f66ec | bellard | val = (val & ~set_mask) | (mask16[s->gr[0]] & set_mask);
|
812 | e89f66ec | bellard | bit_mask = s->gr[8];
|
813 | e89f66ec | bellard | break;
|
814 | e89f66ec | bellard | case 1: |
815 | e89f66ec | bellard | val = s->latch; |
816 | e89f66ec | bellard | goto do_write;
|
817 | e89f66ec | bellard | case 2: |
818 | e89f66ec | bellard | val = mask16[val & 0x0f];
|
819 | e89f66ec | bellard | bit_mask = s->gr[8];
|
820 | e89f66ec | bellard | break;
|
821 | e89f66ec | bellard | case 3: |
822 | e89f66ec | bellard | /* rotate */
|
823 | e89f66ec | bellard | b = s->gr[3] & 7; |
824 | a41bc9af | bellard | val = (val >> b) | (val << (8 - b));
|
825 | e89f66ec | bellard | |
826 | e89f66ec | bellard | bit_mask = s->gr[8] & val;
|
827 | e89f66ec | bellard | val = mask16[s->gr[0]];
|
828 | e89f66ec | bellard | break;
|
829 | e89f66ec | bellard | } |
830 | e89f66ec | bellard | |
831 | e89f66ec | bellard | /* apply logical operation */
|
832 | e89f66ec | bellard | func_select = s->gr[3] >> 3; |
833 | e89f66ec | bellard | switch(func_select) {
|
834 | e89f66ec | bellard | case 0: |
835 | e89f66ec | bellard | default:
|
836 | e89f66ec | bellard | /* nothing to do */
|
837 | e89f66ec | bellard | break;
|
838 | e89f66ec | bellard | case 1: |
839 | e89f66ec | bellard | /* and */
|
840 | e89f66ec | bellard | val &= s->latch; |
841 | e89f66ec | bellard | break;
|
842 | e89f66ec | bellard | case 2: |
843 | e89f66ec | bellard | /* or */
|
844 | e89f66ec | bellard | val |= s->latch; |
845 | e89f66ec | bellard | break;
|
846 | e89f66ec | bellard | case 3: |
847 | e89f66ec | bellard | /* xor */
|
848 | e89f66ec | bellard | val ^= s->latch; |
849 | e89f66ec | bellard | break;
|
850 | e89f66ec | bellard | } |
851 | e89f66ec | bellard | |
852 | e89f66ec | bellard | /* apply bit mask */
|
853 | e89f66ec | bellard | bit_mask |= bit_mask << 8;
|
854 | e89f66ec | bellard | bit_mask |= bit_mask << 16;
|
855 | e89f66ec | bellard | val = (val & bit_mask) | (s->latch & ~bit_mask); |
856 | e89f66ec | bellard | |
857 | e89f66ec | bellard | do_write:
|
858 | e89f66ec | bellard | /* mask data according to sr[2] */
|
859 | e89f66ec | bellard | write_mask = mask16[s->sr[2]];
|
860 | e89f66ec | bellard | ((uint32_t *)s->vram_ptr)[addr] = |
861 | e89f66ec | bellard | (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) | |
862 | e89f66ec | bellard | (val & write_mask); |
863 | 17b0018b | bellard | #ifdef DEBUG_VGA_MEM
|
864 | e89f66ec | bellard | printf("vga: latch: [0x%x] mask=0x%08x val=0x%08x\n",
|
865 | e89f66ec | bellard | addr * 4, write_mask, val);
|
866 | e89f66ec | bellard | #endif
|
867 | 4fa0f5d2 | bellard | cpu_physical_memory_set_dirty(s->vram_offset + (addr << 2));
|
868 | e89f66ec | bellard | } |
869 | e89f66ec | bellard | } |
870 | e89f66ec | bellard | |
871 | 4fa0f5d2 | bellard | void vga_mem_writew(uint32_t addr, uint32_t val, uint32_t vaddr)
|
872 | e89f66ec | bellard | { |
873 | 4fa0f5d2 | bellard | vga_mem_writeb(addr, val & 0xff, vaddr);
|
874 | 4fa0f5d2 | bellard | vga_mem_writeb(addr + 1, (val >> 8) & 0xff, vaddr); |
875 | e89f66ec | bellard | } |
876 | e89f66ec | bellard | |
877 | 4fa0f5d2 | bellard | void vga_mem_writel(uint32_t addr, uint32_t val, uint32_t vaddr)
|
878 | e89f66ec | bellard | { |
879 | 4fa0f5d2 | bellard | vga_mem_writeb(addr, val & 0xff, vaddr);
|
880 | 4fa0f5d2 | bellard | vga_mem_writeb(addr + 1, (val >> 8) & 0xff, vaddr); |
881 | 4fa0f5d2 | bellard | vga_mem_writeb(addr + 2, (val >> 16) & 0xff, vaddr); |
882 | 4fa0f5d2 | bellard | vga_mem_writeb(addr + 3, (val >> 24) & 0xff, vaddr); |
883 | e89f66ec | bellard | } |
884 | e89f66ec | bellard | |
885 | e89f66ec | bellard | typedef void vga_draw_glyph8_func(uint8_t *d, int linesize, |
886 | e89f66ec | bellard | const uint8_t *font_ptr, int h, |
887 | e89f66ec | bellard | uint32_t fgcol, uint32_t bgcol); |
888 | e89f66ec | bellard | typedef void vga_draw_glyph9_func(uint8_t *d, int linesize, |
889 | e89f66ec | bellard | const uint8_t *font_ptr, int h, |
890 | e89f66ec | bellard | uint32_t fgcol, uint32_t bgcol, int dup9);
|
891 | e89f66ec | bellard | typedef void vga_draw_line_func(VGAState *s1, uint8_t *d, |
892 | e89f66ec | bellard | const uint8_t *s, int width); |
893 | e89f66ec | bellard | |
894 | e89f66ec | bellard | static inline unsigned int rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b) |
895 | e89f66ec | bellard | { |
896 | e89f66ec | bellard | /* XXX: TODO */
|
897 | e89f66ec | bellard | return 0; |
898 | e89f66ec | bellard | } |
899 | e89f66ec | bellard | |
900 | e89f66ec | bellard | static inline unsigned int rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b) |
901 | e89f66ec | bellard | { |
902 | e89f66ec | bellard | return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3); |
903 | e89f66ec | bellard | } |
904 | e89f66ec | bellard | |
905 | e89f66ec | bellard | static inline unsigned int rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b) |
906 | e89f66ec | bellard | { |
907 | e89f66ec | bellard | return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3); |
908 | e89f66ec | bellard | } |
909 | e89f66ec | bellard | |
910 | e89f66ec | bellard | static inline unsigned int rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b) |
911 | e89f66ec | bellard | { |
912 | e89f66ec | bellard | return (r << 16) | (g << 8) | b; |
913 | e89f66ec | bellard | } |
914 | e89f66ec | bellard | |
915 | e89f66ec | bellard | #define DEPTH 8 |
916 | e89f66ec | bellard | #include "vga_template.h" |
917 | e89f66ec | bellard | |
918 | e89f66ec | bellard | #define DEPTH 15 |
919 | e89f66ec | bellard | #include "vga_template.h" |
920 | e89f66ec | bellard | |
921 | e89f66ec | bellard | #define DEPTH 16 |
922 | e89f66ec | bellard | #include "vga_template.h" |
923 | e89f66ec | bellard | |
924 | e89f66ec | bellard | #define DEPTH 32 |
925 | e89f66ec | bellard | #include "vga_template.h" |
926 | e89f66ec | bellard | |
927 | e89f66ec | bellard | static inline int c6_to_8(int v) |
928 | e89f66ec | bellard | { |
929 | e89f66ec | bellard | int b;
|
930 | e89f66ec | bellard | v &= 0x3f;
|
931 | e89f66ec | bellard | b = v & 1;
|
932 | e89f66ec | bellard | return (v << 2) | (b << 1) | b; |
933 | e89f66ec | bellard | } |
934 | e89f66ec | bellard | |
935 | 17b0018b | bellard | static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b) |
936 | 17b0018b | bellard | { |
937 | 17b0018b | bellard | unsigned int col; |
938 | 17b0018b | bellard | col = rgb_to_pixel8(r, g, b); |
939 | 17b0018b | bellard | col |= col << 8;
|
940 | 17b0018b | bellard | col |= col << 16;
|
941 | 17b0018b | bellard | return col;
|
942 | 17b0018b | bellard | } |
943 | 17b0018b | bellard | |
944 | 17b0018b | bellard | static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b) |
945 | 17b0018b | bellard | { |
946 | 17b0018b | bellard | unsigned int col; |
947 | 17b0018b | bellard | col = rgb_to_pixel15(r, g, b); |
948 | 17b0018b | bellard | col |= col << 16;
|
949 | 17b0018b | bellard | return col;
|
950 | 17b0018b | bellard | } |
951 | 17b0018b | bellard | |
952 | 17b0018b | bellard | static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b) |
953 | 17b0018b | bellard | { |
954 | 17b0018b | bellard | unsigned int col; |
955 | 17b0018b | bellard | col = rgb_to_pixel16(r, g, b); |
956 | 17b0018b | bellard | col |= col << 16;
|
957 | 17b0018b | bellard | return col;
|
958 | 17b0018b | bellard | } |
959 | 17b0018b | bellard | |
960 | 17b0018b | bellard | static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b) |
961 | 17b0018b | bellard | { |
962 | 17b0018b | bellard | unsigned int col; |
963 | 17b0018b | bellard | col = rgb_to_pixel32(r, g, b); |
964 | 17b0018b | bellard | return col;
|
965 | 17b0018b | bellard | } |
966 | 17b0018b | bellard | |
967 | e89f66ec | bellard | /* return true if the palette was modified */
|
968 | e89f66ec | bellard | static int update_palette16(VGAState *s) |
969 | e89f66ec | bellard | { |
970 | 17b0018b | bellard | int full_update, i;
|
971 | e89f66ec | bellard | uint32_t v, col, *palette; |
972 | e89f66ec | bellard | |
973 | e89f66ec | bellard | full_update = 0;
|
974 | e89f66ec | bellard | palette = s->last_palette; |
975 | e89f66ec | bellard | for(i = 0; i < 16; i++) { |
976 | e89f66ec | bellard | v = s->ar[i]; |
977 | e89f66ec | bellard | if (s->ar[0x10] & 0x80) |
978 | e89f66ec | bellard | v = ((s->ar[0x14] & 0xf) << 4) | (v & 0xf); |
979 | e89f66ec | bellard | else
|
980 | e89f66ec | bellard | v = ((s->ar[0x14] & 0xc) << 4) | (v & 0x3f); |
981 | e89f66ec | bellard | v = v * 3;
|
982 | 17b0018b | bellard | col = s->rgb_to_pixel(c6_to_8(s->palette[v]), |
983 | 17b0018b | bellard | c6_to_8(s->palette[v + 1]),
|
984 | 17b0018b | bellard | c6_to_8(s->palette[v + 2]));
|
985 | 17b0018b | bellard | if (col != palette[i]) {
|
986 | 17b0018b | bellard | full_update = 1;
|
987 | 17b0018b | bellard | palette[i] = col; |
988 | e89f66ec | bellard | } |
989 | 17b0018b | bellard | } |
990 | 17b0018b | bellard | return full_update;
|
991 | 17b0018b | bellard | } |
992 | 17b0018b | bellard | |
993 | 17b0018b | bellard | /* return true if the palette was modified */
|
994 | 17b0018b | bellard | static int update_palette256(VGAState *s) |
995 | 17b0018b | bellard | { |
996 | 17b0018b | bellard | int full_update, i;
|
997 | 17b0018b | bellard | uint32_t v, col, *palette; |
998 | 17b0018b | bellard | |
999 | 17b0018b | bellard | full_update = 0;
|
1000 | 17b0018b | bellard | palette = s->last_palette; |
1001 | 17b0018b | bellard | v = 0;
|
1002 | 17b0018b | bellard | for(i = 0; i < 256; i++) { |
1003 | 17b0018b | bellard | col = s->rgb_to_pixel(c6_to_8(s->palette[v]), |
1004 | 17b0018b | bellard | c6_to_8(s->palette[v + 1]),
|
1005 | 17b0018b | bellard | c6_to_8(s->palette[v + 2]));
|
1006 | e89f66ec | bellard | if (col != palette[i]) {
|
1007 | e89f66ec | bellard | full_update = 1;
|
1008 | e89f66ec | bellard | palette[i] = col; |
1009 | e89f66ec | bellard | } |
1010 | 17b0018b | bellard | v += 3;
|
1011 | e89f66ec | bellard | } |
1012 | e89f66ec | bellard | return full_update;
|
1013 | e89f66ec | bellard | } |
1014 | e89f66ec | bellard | |
1015 | e89f66ec | bellard | /* update start_addr and line_offset. Return TRUE if modified */
|
1016 | e89f66ec | bellard | static int update_basic_params(VGAState *s) |
1017 | e89f66ec | bellard | { |
1018 | e89f66ec | bellard | int full_update;
|
1019 | e89f66ec | bellard | uint32_t start_addr, line_offset, line_compare, v; |
1020 | e89f66ec | bellard | |
1021 | e89f66ec | bellard | full_update = 0;
|
1022 | 4fa0f5d2 | bellard | |
1023 | 4fa0f5d2 | bellard | #ifdef CONFIG_BOCHS_VBE
|
1024 | 4fa0f5d2 | bellard | if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
|
1025 | 4fa0f5d2 | bellard | line_offset = s->vbe_line_offset; |
1026 | 4fa0f5d2 | bellard | start_addr = s->vbe_start_addr; |
1027 | 4fa0f5d2 | bellard | } else
|
1028 | 4fa0f5d2 | bellard | #endif
|
1029 | 4fa0f5d2 | bellard | { |
1030 | 4fa0f5d2 | bellard | /* compute line_offset in bytes */
|
1031 | 4fa0f5d2 | bellard | line_offset = s->cr[0x13];
|
1032 | a41bc9af | bellard | #ifdef CONFIG_S3VGA
|
1033 | 4fa0f5d2 | bellard | v = (s->cr[0x51] >> 4) & 3; /* S3 extension */ |
1034 | 4fa0f5d2 | bellard | if (v == 0) |
1035 | 4fa0f5d2 | bellard | v = (s->cr[0x43] >> 2) & 1; /* S3 extension */ |
1036 | 4fa0f5d2 | bellard | line_offset |= (v << 8);
|
1037 | a41bc9af | bellard | #endif
|
1038 | 4fa0f5d2 | bellard | line_offset <<= 3;
|
1039 | 4fa0f5d2 | bellard | |
1040 | 4fa0f5d2 | bellard | /* starting address */
|
1041 | 4fa0f5d2 | bellard | start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8); |
1042 | a41bc9af | bellard | #ifdef CONFIG_S3VGA
|
1043 | 4fa0f5d2 | bellard | start_addr |= (s->cr[0x69] & 0x1f) << 16; /* S3 extension */ |
1044 | a41bc9af | bellard | #endif
|
1045 | 4fa0f5d2 | bellard | } |
1046 | 4fa0f5d2 | bellard | |
1047 | e89f66ec | bellard | /* line compare */
|
1048 | e89f66ec | bellard | line_compare = s->cr[0x18] |
|
1049 | e89f66ec | bellard | ((s->cr[0x07] & 0x10) << 4) | |
1050 | e89f66ec | bellard | ((s->cr[0x09] & 0x40) << 3); |
1051 | e89f66ec | bellard | |
1052 | e89f66ec | bellard | if (line_offset != s->line_offset ||
|
1053 | e89f66ec | bellard | start_addr != s->start_addr || |
1054 | e89f66ec | bellard | line_compare != s->line_compare) { |
1055 | e89f66ec | bellard | s->line_offset = line_offset; |
1056 | e89f66ec | bellard | s->start_addr = start_addr; |
1057 | e89f66ec | bellard | s->line_compare = line_compare; |
1058 | e89f66ec | bellard | full_update = 1;
|
1059 | e89f66ec | bellard | } |
1060 | e89f66ec | bellard | return full_update;
|
1061 | e89f66ec | bellard | } |
1062 | e89f66ec | bellard | |
1063 | e89f66ec | bellard | static inline int get_depth_index(int depth) |
1064 | e89f66ec | bellard | { |
1065 | e89f66ec | bellard | switch(depth) {
|
1066 | e89f66ec | bellard | default:
|
1067 | e89f66ec | bellard | case 8: |
1068 | e89f66ec | bellard | return 0; |
1069 | e89f66ec | bellard | case 15: |
1070 | e89f66ec | bellard | return 1; |
1071 | e89f66ec | bellard | case 16: |
1072 | e89f66ec | bellard | return 2; |
1073 | e89f66ec | bellard | case 32: |
1074 | e89f66ec | bellard | return 3; |
1075 | e89f66ec | bellard | } |
1076 | e89f66ec | bellard | } |
1077 | e89f66ec | bellard | |
1078 | e89f66ec | bellard | static vga_draw_glyph8_func *vga_draw_glyph8_table[4] = { |
1079 | e89f66ec | bellard | vga_draw_glyph8_8, |
1080 | e89f66ec | bellard | vga_draw_glyph8_16, |
1081 | e89f66ec | bellard | vga_draw_glyph8_16, |
1082 | e89f66ec | bellard | vga_draw_glyph8_32, |
1083 | e89f66ec | bellard | }; |
1084 | e89f66ec | bellard | |
1085 | 17b0018b | bellard | static vga_draw_glyph8_func *vga_draw_glyph16_table[4] = { |
1086 | 17b0018b | bellard | vga_draw_glyph16_8, |
1087 | 17b0018b | bellard | vga_draw_glyph16_16, |
1088 | 17b0018b | bellard | vga_draw_glyph16_16, |
1089 | 17b0018b | bellard | vga_draw_glyph16_32, |
1090 | 17b0018b | bellard | }; |
1091 | 17b0018b | bellard | |
1092 | e89f66ec | bellard | static vga_draw_glyph9_func *vga_draw_glyph9_table[4] = { |
1093 | e89f66ec | bellard | vga_draw_glyph9_8, |
1094 | e89f66ec | bellard | vga_draw_glyph9_16, |
1095 | e89f66ec | bellard | vga_draw_glyph9_16, |
1096 | e89f66ec | bellard | vga_draw_glyph9_32, |
1097 | e89f66ec | bellard | }; |
1098 | e89f66ec | bellard | |
1099 | e89f66ec | bellard | static const uint8_t cursor_glyph[32 * 4] = { |
1100 | e89f66ec | bellard | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, |
1101 | e89f66ec | bellard | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, |
1102 | e89f66ec | bellard | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, |
1103 | e89f66ec | bellard | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, |
1104 | e89f66ec | bellard | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, |
1105 | e89f66ec | bellard | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, |
1106 | e89f66ec | bellard | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, |
1107 | e89f66ec | bellard | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, |
1108 | e89f66ec | bellard | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, |
1109 | e89f66ec | bellard | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, |
1110 | e89f66ec | bellard | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, |
1111 | e89f66ec | bellard | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, |
1112 | e89f66ec | bellard | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, |
1113 | e89f66ec | bellard | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, |
1114 | e89f66ec | bellard | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, |
1115 | e89f66ec | bellard | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, |
1116 | e89f66ec | bellard | }; |
1117 | e89f66ec | bellard | |
1118 | e89f66ec | bellard | /*
|
1119 | e89f66ec | bellard | * Text mode update
|
1120 | e89f66ec | bellard | * Missing:
|
1121 | e89f66ec | bellard | * - double scan
|
1122 | e89f66ec | bellard | * - double width
|
1123 | e89f66ec | bellard | * - underline
|
1124 | e89f66ec | bellard | * - flashing
|
1125 | e89f66ec | bellard | */
|
1126 | e89f66ec | bellard | static void vga_draw_text(VGAState *s, int full_update) |
1127 | e89f66ec | bellard | { |
1128 | e89f66ec | bellard | int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
|
1129 | e89f66ec | bellard | int cx_min, cx_max, linesize, x_incr;
|
1130 | e89f66ec | bellard | uint32_t offset, fgcol, bgcol, v, cursor_offset; |
1131 | e89f66ec | bellard | uint8_t *d1, *d, *src, *s1, *dest, *cursor_ptr; |
1132 | e89f66ec | bellard | const uint8_t *font_ptr, *font_base[2]; |
1133 | e89f66ec | bellard | int dup9, line_offset, depth_index;
|
1134 | e89f66ec | bellard | uint32_t *palette; |
1135 | e89f66ec | bellard | uint32_t *ch_attr_ptr; |
1136 | e89f66ec | bellard | vga_draw_glyph8_func *vga_draw_glyph8; |
1137 | e89f66ec | bellard | vga_draw_glyph9_func *vga_draw_glyph9; |
1138 | e89f66ec | bellard | |
1139 | e89f66ec | bellard | full_update |= update_palette16(s); |
1140 | e89f66ec | bellard | palette = s->last_palette; |
1141 | e89f66ec | bellard | |
1142 | e89f66ec | bellard | /* compute font data address (in plane 2) */
|
1143 | e89f66ec | bellard | v = s->sr[3];
|
1144 | e89f66ec | bellard | offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2; |
1145 | e89f66ec | bellard | if (offset != s->font_offsets[0]) { |
1146 | e89f66ec | bellard | s->font_offsets[0] = offset;
|
1147 | e89f66ec | bellard | full_update = 1;
|
1148 | e89f66ec | bellard | } |
1149 | e89f66ec | bellard | font_base[0] = s->vram_ptr + offset;
|
1150 | e89f66ec | bellard | |
1151 | e89f66ec | bellard | offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2; |
1152 | e89f66ec | bellard | font_base[1] = s->vram_ptr + offset;
|
1153 | e89f66ec | bellard | if (offset != s->font_offsets[1]) { |
1154 | e89f66ec | bellard | s->font_offsets[1] = offset;
|
1155 | e89f66ec | bellard | full_update = 1;
|
1156 | e89f66ec | bellard | } |
1157 | e89f66ec | bellard | |
1158 | e89f66ec | bellard | full_update |= update_basic_params(s); |
1159 | e89f66ec | bellard | |
1160 | e89f66ec | bellard | line_offset = s->line_offset; |
1161 | e89f66ec | bellard | s1 = s->vram_ptr + (s->start_addr * 4);
|
1162 | e89f66ec | bellard | |
1163 | e89f66ec | bellard | /* total width & height */
|
1164 | e89f66ec | bellard | cheight = (s->cr[9] & 0x1f) + 1; |
1165 | e89f66ec | bellard | cw = 8;
|
1166 | e89f66ec | bellard | if (s->sr[1] & 0x01) |
1167 | e89f66ec | bellard | cw = 9;
|
1168 | 17b0018b | bellard | if (s->sr[1] & 0x08) |
1169 | 17b0018b | bellard | cw = 16; /* NOTE: no 18 pixel wide */ |
1170 | e89f66ec | bellard | x_incr = cw * ((s->ds->depth + 7) >> 3); |
1171 | e89f66ec | bellard | width = (s->cr[0x01] + 1); |
1172 | 17b0018b | bellard | if (s->cr[0x06] == 100) { |
1173 | 17b0018b | bellard | /* ugly hack for CGA 160x100x16 - explain me the logic */
|
1174 | 17b0018b | bellard | height = 100;
|
1175 | 17b0018b | bellard | } else {
|
1176 | 17b0018b | bellard | height = s->cr[0x12] |
|
1177 | 17b0018b | bellard | ((s->cr[0x07] & 0x02) << 7) | |
1178 | 17b0018b | bellard | ((s->cr[0x07] & 0x40) << 3); |
1179 | 17b0018b | bellard | height = (height + 1) / cheight;
|
1180 | 17b0018b | bellard | } |
1181 | e89f66ec | bellard | if (width != s->last_width || height != s->last_height ||
|
1182 | e89f66ec | bellard | cw != s->last_cw || cw != s->last_cw) { |
1183 | e89f66ec | bellard | dpy_resize(s->ds, width * cw, height * cheight); |
1184 | e89f66ec | bellard | s->last_width = width; |
1185 | e89f66ec | bellard | s->last_height = height; |
1186 | e89f66ec | bellard | s->last_ch = cheight; |
1187 | e89f66ec | bellard | s->last_cw = cw; |
1188 | e89f66ec | bellard | full_update = 1;
|
1189 | e89f66ec | bellard | } |
1190 | e89f66ec | bellard | cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr; |
1191 | e89f66ec | bellard | if (cursor_offset != s->cursor_offset ||
|
1192 | e89f66ec | bellard | s->cr[0xa] != s->cursor_start ||
|
1193 | e89f66ec | bellard | s->cr[0xb] != s->cursor_end) {
|
1194 | e89f66ec | bellard | /* if the cursor position changed, we update the old and new
|
1195 | e89f66ec | bellard | chars */
|
1196 | e89f66ec | bellard | if (s->cursor_offset < CH_ATTR_SIZE)
|
1197 | e89f66ec | bellard | s->last_ch_attr[s->cursor_offset] = -1;
|
1198 | e89f66ec | bellard | if (cursor_offset < CH_ATTR_SIZE)
|
1199 | e89f66ec | bellard | s->last_ch_attr[cursor_offset] = -1;
|
1200 | e89f66ec | bellard | s->cursor_offset = cursor_offset; |
1201 | e89f66ec | bellard | s->cursor_start = s->cr[0xa];
|
1202 | e89f66ec | bellard | s->cursor_end = s->cr[0xb];
|
1203 | e89f66ec | bellard | } |
1204 | 39cf7803 | bellard | cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
|
1205 | e89f66ec | bellard | |
1206 | e89f66ec | bellard | depth_index = get_depth_index(s->ds->depth); |
1207 | 17b0018b | bellard | if (cw == 16) |
1208 | 17b0018b | bellard | vga_draw_glyph8 = vga_draw_glyph16_table[depth_index]; |
1209 | 17b0018b | bellard | else
|
1210 | 17b0018b | bellard | vga_draw_glyph8 = vga_draw_glyph8_table[depth_index]; |
1211 | e89f66ec | bellard | vga_draw_glyph9 = vga_draw_glyph9_table[depth_index]; |
1212 | e89f66ec | bellard | |
1213 | e89f66ec | bellard | dest = s->ds->data; |
1214 | e89f66ec | bellard | linesize = s->ds->linesize; |
1215 | e89f66ec | bellard | ch_attr_ptr = s->last_ch_attr; |
1216 | e89f66ec | bellard | for(cy = 0; cy < height; cy++) { |
1217 | e89f66ec | bellard | d1 = dest; |
1218 | e89f66ec | bellard | src = s1; |
1219 | e89f66ec | bellard | cx_min = width; |
1220 | e89f66ec | bellard | cx_max = -1;
|
1221 | e89f66ec | bellard | for(cx = 0; cx < width; cx++) { |
1222 | e89f66ec | bellard | ch_attr = *(uint16_t *)src; |
1223 | e89f66ec | bellard | if (full_update || ch_attr != *ch_attr_ptr) {
|
1224 | e89f66ec | bellard | if (cx < cx_min)
|
1225 | e89f66ec | bellard | cx_min = cx; |
1226 | e89f66ec | bellard | if (cx > cx_max)
|
1227 | e89f66ec | bellard | cx_max = cx; |
1228 | e89f66ec | bellard | *ch_attr_ptr = ch_attr; |
1229 | e89f66ec | bellard | #ifdef WORDS_BIGENDIAN
|
1230 | e89f66ec | bellard | ch = ch_attr >> 8;
|
1231 | e89f66ec | bellard | cattr = ch_attr & 0xff;
|
1232 | e89f66ec | bellard | #else
|
1233 | e89f66ec | bellard | ch = ch_attr & 0xff;
|
1234 | e89f66ec | bellard | cattr = ch_attr >> 8;
|
1235 | e89f66ec | bellard | #endif
|
1236 | e89f66ec | bellard | font_ptr = font_base[(cattr >> 3) & 1]; |
1237 | e89f66ec | bellard | font_ptr += 32 * 4 * ch; |
1238 | e89f66ec | bellard | bgcol = palette[cattr >> 4];
|
1239 | e89f66ec | bellard | fgcol = palette[cattr & 0x0f];
|
1240 | 17b0018b | bellard | if (cw != 9) { |
1241 | e89f66ec | bellard | vga_draw_glyph8(d1, linesize, |
1242 | e89f66ec | bellard | font_ptr, cheight, fgcol, bgcol); |
1243 | e89f66ec | bellard | } else {
|
1244 | e89f66ec | bellard | dup9 = 0;
|
1245 | e89f66ec | bellard | if (ch >= 0xb0 && ch <= 0xdf && (s->ar[0x10] & 0x04)) |
1246 | e89f66ec | bellard | dup9 = 1;
|
1247 | e89f66ec | bellard | vga_draw_glyph9(d1, linesize, |
1248 | e89f66ec | bellard | font_ptr, cheight, fgcol, bgcol, dup9); |
1249 | e89f66ec | bellard | } |
1250 | e89f66ec | bellard | if (src == cursor_ptr &&
|
1251 | e89f66ec | bellard | !(s->cr[0x0a] & 0x20)) { |
1252 | e89f66ec | bellard | int line_start, line_last, h;
|
1253 | e89f66ec | bellard | /* draw the cursor */
|
1254 | e89f66ec | bellard | line_start = s->cr[0x0a] & 0x1f; |
1255 | e89f66ec | bellard | line_last = s->cr[0x0b] & 0x1f; |
1256 | e89f66ec | bellard | /* XXX: check that */
|
1257 | e89f66ec | bellard | if (line_last > cheight - 1) |
1258 | e89f66ec | bellard | line_last = cheight - 1;
|
1259 | e89f66ec | bellard | if (line_last >= line_start && line_start < cheight) {
|
1260 | e89f66ec | bellard | h = line_last - line_start + 1;
|
1261 | e89f66ec | bellard | d = d1 + linesize * line_start; |
1262 | 17b0018b | bellard | if (cw != 9) { |
1263 | e89f66ec | bellard | vga_draw_glyph8(d, linesize, |
1264 | e89f66ec | bellard | cursor_glyph, h, fgcol, bgcol); |
1265 | e89f66ec | bellard | } else {
|
1266 | e89f66ec | bellard | vga_draw_glyph9(d, linesize, |
1267 | e89f66ec | bellard | cursor_glyph, h, fgcol, bgcol, 1);
|
1268 | e89f66ec | bellard | } |
1269 | e89f66ec | bellard | } |
1270 | e89f66ec | bellard | } |
1271 | e89f66ec | bellard | } |
1272 | e89f66ec | bellard | d1 += x_incr; |
1273 | e89f66ec | bellard | src += 4;
|
1274 | e89f66ec | bellard | ch_attr_ptr++; |
1275 | e89f66ec | bellard | } |
1276 | e89f66ec | bellard | if (cx_max != -1) { |
1277 | e89f66ec | bellard | dpy_update(s->ds, cx_min * cw, cy * cheight, |
1278 | e89f66ec | bellard | (cx_max - cx_min + 1) * cw, cheight);
|
1279 | e89f66ec | bellard | } |
1280 | e89f66ec | bellard | dest += linesize * cheight; |
1281 | e89f66ec | bellard | s1 += line_offset; |
1282 | e89f66ec | bellard | } |
1283 | e89f66ec | bellard | } |
1284 | e89f66ec | bellard | |
1285 | 17b0018b | bellard | enum {
|
1286 | 17b0018b | bellard | VGA_DRAW_LINE2, |
1287 | 17b0018b | bellard | VGA_DRAW_LINE2D2, |
1288 | 17b0018b | bellard | VGA_DRAW_LINE4, |
1289 | 17b0018b | bellard | VGA_DRAW_LINE4D2, |
1290 | 17b0018b | bellard | VGA_DRAW_LINE8D2, |
1291 | 17b0018b | bellard | VGA_DRAW_LINE8, |
1292 | 17b0018b | bellard | VGA_DRAW_LINE15, |
1293 | 17b0018b | bellard | VGA_DRAW_LINE16, |
1294 | 4fa0f5d2 | bellard | VGA_DRAW_LINE24, |
1295 | 17b0018b | bellard | VGA_DRAW_LINE32, |
1296 | 17b0018b | bellard | VGA_DRAW_LINE_NB, |
1297 | 17b0018b | bellard | }; |
1298 | 17b0018b | bellard | |
1299 | 17b0018b | bellard | static vga_draw_line_func *vga_draw_line_table[4 * VGA_DRAW_LINE_NB] = { |
1300 | e89f66ec | bellard | vga_draw_line2_8, |
1301 | e89f66ec | bellard | vga_draw_line2_16, |
1302 | e89f66ec | bellard | vga_draw_line2_16, |
1303 | e89f66ec | bellard | vga_draw_line2_32, |
1304 | e89f66ec | bellard | |
1305 | 17b0018b | bellard | vga_draw_line2d2_8, |
1306 | 17b0018b | bellard | vga_draw_line2d2_16, |
1307 | 17b0018b | bellard | vga_draw_line2d2_16, |
1308 | 17b0018b | bellard | vga_draw_line2d2_32, |
1309 | 17b0018b | bellard | |
1310 | e89f66ec | bellard | vga_draw_line4_8, |
1311 | e89f66ec | bellard | vga_draw_line4_16, |
1312 | e89f66ec | bellard | vga_draw_line4_16, |
1313 | e89f66ec | bellard | vga_draw_line4_32, |
1314 | e89f66ec | bellard | |
1315 | 17b0018b | bellard | vga_draw_line4d2_8, |
1316 | 17b0018b | bellard | vga_draw_line4d2_16, |
1317 | 17b0018b | bellard | vga_draw_line4d2_16, |
1318 | 17b0018b | bellard | vga_draw_line4d2_32, |
1319 | 17b0018b | bellard | |
1320 | 17b0018b | bellard | vga_draw_line8d2_8, |
1321 | 17b0018b | bellard | vga_draw_line8d2_16, |
1322 | 17b0018b | bellard | vga_draw_line8d2_16, |
1323 | 17b0018b | bellard | vga_draw_line8d2_32, |
1324 | 17b0018b | bellard | |
1325 | e89f66ec | bellard | vga_draw_line8_8, |
1326 | e89f66ec | bellard | vga_draw_line8_16, |
1327 | e89f66ec | bellard | vga_draw_line8_16, |
1328 | e89f66ec | bellard | vga_draw_line8_32, |
1329 | e89f66ec | bellard | |
1330 | e89f66ec | bellard | vga_draw_line15_8, |
1331 | e89f66ec | bellard | vga_draw_line15_15, |
1332 | e89f66ec | bellard | vga_draw_line15_16, |
1333 | e89f66ec | bellard | vga_draw_line15_32, |
1334 | e89f66ec | bellard | |
1335 | e89f66ec | bellard | vga_draw_line16_8, |
1336 | e89f66ec | bellard | vga_draw_line16_15, |
1337 | e89f66ec | bellard | vga_draw_line16_16, |
1338 | e89f66ec | bellard | vga_draw_line16_32, |
1339 | e89f66ec | bellard | |
1340 | 4fa0f5d2 | bellard | vga_draw_line24_8, |
1341 | 4fa0f5d2 | bellard | vga_draw_line24_15, |
1342 | 4fa0f5d2 | bellard | vga_draw_line24_16, |
1343 | 4fa0f5d2 | bellard | vga_draw_line24_32, |
1344 | 4fa0f5d2 | bellard | |
1345 | e89f66ec | bellard | vga_draw_line32_8, |
1346 | e89f66ec | bellard | vga_draw_line32_15, |
1347 | e89f66ec | bellard | vga_draw_line32_16, |
1348 | e89f66ec | bellard | vga_draw_line32_32, |
1349 | e89f66ec | bellard | }; |
1350 | e89f66ec | bellard | |
1351 | e89f66ec | bellard | /*
|
1352 | e89f66ec | bellard | * graphic modes
|
1353 | e89f66ec | bellard | * Missing:
|
1354 | e89f66ec | bellard | * - double scan
|
1355 | e89f66ec | bellard | * - double width
|
1356 | e89f66ec | bellard | */
|
1357 | e89f66ec | bellard | static void vga_draw_graphic(VGAState *s, int full_update) |
1358 | e89f66ec | bellard | { |
1359 | 17b0018b | bellard | int y1, y, update, page_min, page_max, linesize, y_start, double_scan, mask;
|
1360 | 39cf7803 | bellard | int width, height, shift_control, line_offset, page0, page1, bwidth;
|
1361 | a07cf92a | bellard | int disp_width, multi_scan, multi_run;
|
1362 | e89f66ec | bellard | uint8_t *d; |
1363 | 39cf7803 | bellard | uint32_t v, addr1, addr; |
1364 | e89f66ec | bellard | vga_draw_line_func *vga_draw_line; |
1365 | 17b0018b | bellard | |
1366 | e89f66ec | bellard | full_update |= update_basic_params(s); |
1367 | e89f66ec | bellard | |
1368 | 39cf7803 | bellard | width = (s->cr[0x01] + 1) * 8; |
1369 | e89f66ec | bellard | height = s->cr[0x12] |
|
1370 | e89f66ec | bellard | ((s->cr[0x07] & 0x02) << 7) | |
1371 | e89f66ec | bellard | ((s->cr[0x07] & 0x40) << 3); |
1372 | e89f66ec | bellard | height = (height + 1);
|
1373 | 17b0018b | bellard | disp_width = width; |
1374 | 17b0018b | bellard | |
1375 | e89f66ec | bellard | shift_control = (s->gr[0x05] >> 5) & 3; |
1376 | a07cf92a | bellard | double_scan = (s->cr[0x09] & 0x80); |
1377 | a07cf92a | bellard | if (shift_control > 1) { |
1378 | a07cf92a | bellard | multi_scan = (s->cr[0x09] & 0x1f); |
1379 | a07cf92a | bellard | } else {
|
1380 | a07cf92a | bellard | multi_scan = 0;
|
1381 | a07cf92a | bellard | } |
1382 | a07cf92a | bellard | multi_run = multi_scan; |
1383 | 17b0018b | bellard | if (shift_control != s->shift_control ||
|
1384 | 17b0018b | bellard | double_scan != s->double_scan) { |
1385 | e89f66ec | bellard | full_update = 1;
|
1386 | e89f66ec | bellard | s->shift_control = shift_control; |
1387 | 17b0018b | bellard | s->double_scan = double_scan; |
1388 | e89f66ec | bellard | } |
1389 | e89f66ec | bellard | |
1390 | 17b0018b | bellard | if (shift_control == 0) { |
1391 | 17b0018b | bellard | full_update |= update_palette16(s); |
1392 | 17b0018b | bellard | if (s->sr[0x01] & 8) { |
1393 | 17b0018b | bellard | v = VGA_DRAW_LINE4D2; |
1394 | 17b0018b | bellard | disp_width <<= 1;
|
1395 | 17b0018b | bellard | } else {
|
1396 | 17b0018b | bellard | v = VGA_DRAW_LINE4; |
1397 | 17b0018b | bellard | } |
1398 | 17b0018b | bellard | } else if (shift_control == 1) { |
1399 | 17b0018b | bellard | full_update |= update_palette16(s); |
1400 | 17b0018b | bellard | if (s->sr[0x01] & 8) { |
1401 | 17b0018b | bellard | v = VGA_DRAW_LINE2D2; |
1402 | 17b0018b | bellard | disp_width <<= 1;
|
1403 | 17b0018b | bellard | } else {
|
1404 | 17b0018b | bellard | v = VGA_DRAW_LINE2; |
1405 | 17b0018b | bellard | } |
1406 | 17b0018b | bellard | } else {
|
1407 | 4fa0f5d2 | bellard | #ifdef CONFIG_BOCHS_VBE
|
1408 | 4fa0f5d2 | bellard | if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
|
1409 | 4fa0f5d2 | bellard | switch(s->vbe_regs[VBE_DISPI_INDEX_BPP]) {
|
1410 | 4fa0f5d2 | bellard | default:
|
1411 | 4fa0f5d2 | bellard | case 8: |
1412 | 4fa0f5d2 | bellard | full_update |= update_palette256(s); |
1413 | 4fa0f5d2 | bellard | v = VGA_DRAW_LINE8; |
1414 | 4fa0f5d2 | bellard | break;
|
1415 | 4fa0f5d2 | bellard | case 15: |
1416 | 4fa0f5d2 | bellard | v = VGA_DRAW_LINE15; |
1417 | 4fa0f5d2 | bellard | break;
|
1418 | 4fa0f5d2 | bellard | case 16: |
1419 | 4fa0f5d2 | bellard | v = VGA_DRAW_LINE16; |
1420 | 4fa0f5d2 | bellard | break;
|
1421 | 4fa0f5d2 | bellard | case 24: |
1422 | 4fa0f5d2 | bellard | v = VGA_DRAW_LINE24; |
1423 | 4fa0f5d2 | bellard | break;
|
1424 | 4fa0f5d2 | bellard | case 32: |
1425 | 4fa0f5d2 | bellard | v = VGA_DRAW_LINE32; |
1426 | 4fa0f5d2 | bellard | break;
|
1427 | 4fa0f5d2 | bellard | } |
1428 | 4fa0f5d2 | bellard | } else
|
1429 | 4fa0f5d2 | bellard | #endif
|
1430 | 4fa0f5d2 | bellard | { |
1431 | 4fa0f5d2 | bellard | full_update |= update_palette256(s); |
1432 | 4fa0f5d2 | bellard | v = VGA_DRAW_LINE8D2; |
1433 | 4fa0f5d2 | bellard | } |
1434 | 17b0018b | bellard | } |
1435 | e89f66ec | bellard | vga_draw_line = vga_draw_line_table[v * 4 + get_depth_index(s->ds->depth)];
|
1436 | 17b0018b | bellard | |
1437 | 17b0018b | bellard | if (disp_width != s->last_width ||
|
1438 | 17b0018b | bellard | height != s->last_height) { |
1439 | 17b0018b | bellard | dpy_resize(s->ds, disp_width, height); |
1440 | 17b0018b | bellard | s->last_width = disp_width; |
1441 | 17b0018b | bellard | s->last_height = height; |
1442 | 17b0018b | bellard | full_update = 1;
|
1443 | 17b0018b | bellard | } |
1444 | 17b0018b | bellard | |
1445 | e89f66ec | bellard | line_offset = s->line_offset; |
1446 | 17b0018b | bellard | #if 0
|
1447 | 17b0018b | bellard | printf("w=%d h=%d v=%d line_offset=%d double_scan=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=%02x\n",
|
1448 | 17b0018b | bellard | width, height, v, line_offset, s->cr[9], s->cr[0x17], s->line_compare, s->sr[0x01]);
|
1449 | 17b0018b | bellard | #endif
|
1450 | e89f66ec | bellard | addr1 = (s->start_addr * 4);
|
1451 | 39cf7803 | bellard | bwidth = width * 4;
|
1452 | 39cf7803 | bellard | y_start = -1;
|
1453 | e89f66ec | bellard | page_min = 0x7fffffff;
|
1454 | e89f66ec | bellard | page_max = -1;
|
1455 | e89f66ec | bellard | d = s->ds->data; |
1456 | e89f66ec | bellard | linesize = s->ds->linesize; |
1457 | 17b0018b | bellard | y1 = 0;
|
1458 | e89f66ec | bellard | for(y = 0; y < height; y++) { |
1459 | e89f66ec | bellard | addr = addr1; |
1460 | 39cf7803 | bellard | if (!(s->cr[0x17] & 1)) { |
1461 | 17b0018b | bellard | int shift;
|
1462 | e89f66ec | bellard | /* CGA compatibility handling */
|
1463 | 17b0018b | bellard | shift = 14 + ((s->cr[0x17] >> 6) & 1); |
1464 | 17b0018b | bellard | addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift); |
1465 | e89f66ec | bellard | } |
1466 | 39cf7803 | bellard | if (!(s->cr[0x17] & 2)) { |
1467 | 17b0018b | bellard | addr = (addr & ~0x8000) | ((y1 & 2) << 14); |
1468 | e89f66ec | bellard | } |
1469 | 4fa0f5d2 | bellard | page0 = s->vram_offset + (addr & TARGET_PAGE_MASK); |
1470 | 4fa0f5d2 | bellard | page1 = s->vram_offset + ((addr + bwidth - 1) & TARGET_PAGE_MASK);
|
1471 | 4fa0f5d2 | bellard | update = full_update | cpu_physical_memory_is_dirty(page0) | |
1472 | 4fa0f5d2 | bellard | cpu_physical_memory_is_dirty(page1); |
1473 | 4fa0f5d2 | bellard | if ((page1 - page0) > TARGET_PAGE_SIZE) {
|
1474 | 39cf7803 | bellard | /* if wide line, can use another page */
|
1475 | 4fa0f5d2 | bellard | update |= cpu_physical_memory_is_dirty(page0 + TARGET_PAGE_SIZE); |
1476 | 39cf7803 | bellard | } |
1477 | e89f66ec | bellard | if (update) {
|
1478 | 39cf7803 | bellard | if (y_start < 0) |
1479 | 39cf7803 | bellard | y_start = y; |
1480 | e89f66ec | bellard | if (page0 < page_min)
|
1481 | e89f66ec | bellard | page_min = page0; |
1482 | e89f66ec | bellard | if (page1 > page_max)
|
1483 | e89f66ec | bellard | page_max = page1; |
1484 | e89f66ec | bellard | vga_draw_line(s, d, s->vram_ptr + addr, width); |
1485 | 39cf7803 | bellard | } else {
|
1486 | 39cf7803 | bellard | if (y_start >= 0) { |
1487 | 39cf7803 | bellard | /* flush to display */
|
1488 | 39cf7803 | bellard | dpy_update(s->ds, 0, y_start,
|
1489 | 17b0018b | bellard | disp_width, y - y_start); |
1490 | 39cf7803 | bellard | y_start = -1;
|
1491 | 39cf7803 | bellard | } |
1492 | e89f66ec | bellard | } |
1493 | a07cf92a | bellard | if (!multi_run) {
|
1494 | a07cf92a | bellard | if (!double_scan || (y & 1) != 0) { |
1495 | a07cf92a | bellard | if (y1 == s->line_compare) {
|
1496 | a07cf92a | bellard | addr1 = 0;
|
1497 | a07cf92a | bellard | } else {
|
1498 | a07cf92a | bellard | mask = (s->cr[0x17] & 3) ^ 3; |
1499 | a07cf92a | bellard | if ((y1 & mask) == mask)
|
1500 | a07cf92a | bellard | addr1 += line_offset; |
1501 | a07cf92a | bellard | } |
1502 | a07cf92a | bellard | y1++; |
1503 | 17b0018b | bellard | } |
1504 | a07cf92a | bellard | multi_run = multi_scan; |
1505 | a07cf92a | bellard | } else {
|
1506 | a07cf92a | bellard | multi_run--; |
1507 | 17b0018b | bellard | y1++; |
1508 | e89f66ec | bellard | } |
1509 | e89f66ec | bellard | d += linesize; |
1510 | e89f66ec | bellard | } |
1511 | 39cf7803 | bellard | if (y_start >= 0) { |
1512 | 39cf7803 | bellard | /* flush to display */
|
1513 | 39cf7803 | bellard | dpy_update(s->ds, 0, y_start,
|
1514 | 17b0018b | bellard | disp_width, y - y_start); |
1515 | 39cf7803 | bellard | } |
1516 | e89f66ec | bellard | /* reset modified pages */
|
1517 | e89f66ec | bellard | if (page_max != -1) { |
1518 | 4fa0f5d2 | bellard | cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE); |
1519 | e89f66ec | bellard | } |
1520 | e89f66ec | bellard | } |
1521 | e89f66ec | bellard | |
1522 | e89f66ec | bellard | /* draw text terminal (very limited, just for simple boot debug
|
1523 | e89f66ec | bellard | messages) */
|
1524 | e89f66ec | bellard | static int last_cursor_pos; |
1525 | e89f66ec | bellard | |
1526 | e89f66ec | bellard | void vga_draw_dumb(VGAState *s)
|
1527 | e89f66ec | bellard | { |
1528 | e89f66ec | bellard | int c, i, cursor_pos, eol;
|
1529 | e89f66ec | bellard | |
1530 | e89f66ec | bellard | cursor_pos = s->cr[0x0f] | (s->cr[0x0e] << 8); |
1531 | e89f66ec | bellard | eol = 0;
|
1532 | e89f66ec | bellard | for(i = last_cursor_pos; i < cursor_pos; i++) {
|
1533 | e89f66ec | bellard | /* XXX: should use vga RAM */
|
1534 | e89f66ec | bellard | c = phys_ram_base[0xb8000 + (i) * 2]; |
1535 | e89f66ec | bellard | if (c >= ' ') { |
1536 | e89f66ec | bellard | putchar(c); |
1537 | e89f66ec | bellard | eol = 0;
|
1538 | e89f66ec | bellard | } else {
|
1539 | e89f66ec | bellard | if (!eol)
|
1540 | e89f66ec | bellard | putchar('\n');
|
1541 | e89f66ec | bellard | eol = 1;
|
1542 | e89f66ec | bellard | } |
1543 | e89f66ec | bellard | } |
1544 | e89f66ec | bellard | fflush(stdout); |
1545 | e89f66ec | bellard | last_cursor_pos = cursor_pos; |
1546 | e89f66ec | bellard | } |
1547 | e89f66ec | bellard | |
1548 | e89f66ec | bellard | void vga_update_display(void) |
1549 | e89f66ec | bellard | { |
1550 | e89f66ec | bellard | VGAState *s = &vga_state; |
1551 | e89f66ec | bellard | int full_update, graphic_mode;
|
1552 | e89f66ec | bellard | |
1553 | e89f66ec | bellard | if (s->ds->depth == 0) { |
1554 | e89f66ec | bellard | vga_draw_dumb(s); |
1555 | e89f66ec | bellard | } else {
|
1556 | e89f66ec | bellard | full_update = 0;
|
1557 | e89f66ec | bellard | graphic_mode = s->gr[6] & 1; |
1558 | e89f66ec | bellard | if (graphic_mode != s->graphic_mode) {
|
1559 | e89f66ec | bellard | s->graphic_mode = graphic_mode; |
1560 | e89f66ec | bellard | full_update = 1;
|
1561 | e89f66ec | bellard | } |
1562 | e89f66ec | bellard | if (graphic_mode)
|
1563 | e89f66ec | bellard | vga_draw_graphic(s, full_update); |
1564 | e89f66ec | bellard | else
|
1565 | e89f66ec | bellard | vga_draw_text(s, full_update); |
1566 | e89f66ec | bellard | } |
1567 | e89f66ec | bellard | } |
1568 | e89f66ec | bellard | |
1569 | e89f66ec | bellard | void vga_reset(VGAState *s)
|
1570 | e89f66ec | bellard | { |
1571 | e89f66ec | bellard | memset(s, 0, sizeof(VGAState)); |
1572 | a41bc9af | bellard | #ifdef CONFIG_S3VGA
|
1573 | e89f66ec | bellard | /* chip ID for 8c968 */
|
1574 | e89f66ec | bellard | s->cr[0x2d] = 0x88; |
1575 | e89f66ec | bellard | s->cr[0x2e] = 0xb0; |
1576 | e89f66ec | bellard | s->cr[0x2f] = 0x01; /* XXX: check revision code */ |
1577 | e89f66ec | bellard | s->cr[0x30] = 0xe1; |
1578 | a41bc9af | bellard | #endif
|
1579 | e89f66ec | bellard | s->graphic_mode = -1; /* force full update */ |
1580 | e89f66ec | bellard | } |
1581 | e89f66ec | bellard | |
1582 | e89f66ec | bellard | CPUReadMemoryFunc *vga_mem_read[3] = {
|
1583 | e89f66ec | bellard | vga_mem_readb, |
1584 | e89f66ec | bellard | vga_mem_readw, |
1585 | e89f66ec | bellard | vga_mem_readl, |
1586 | e89f66ec | bellard | }; |
1587 | e89f66ec | bellard | |
1588 | e89f66ec | bellard | CPUWriteMemoryFunc *vga_mem_write[3] = {
|
1589 | e89f66ec | bellard | vga_mem_writeb, |
1590 | e89f66ec | bellard | vga_mem_writew, |
1591 | e89f66ec | bellard | vga_mem_writel, |
1592 | e89f66ec | bellard | }; |
1593 | e89f66ec | bellard | |
1594 | 7138fcfb | bellard | int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base,
|
1595 | 7138fcfb | bellard | unsigned long vga_ram_offset, int vga_ram_size) |
1596 | e89f66ec | bellard | { |
1597 | e89f66ec | bellard | VGAState *s = &vga_state; |
1598 | 17b0018b | bellard | int i, j, v, b;
|
1599 | e89f66ec | bellard | |
1600 | e89f66ec | bellard | for(i = 0;i < 256; i++) { |
1601 | e89f66ec | bellard | v = 0;
|
1602 | e89f66ec | bellard | for(j = 0; j < 8; j++) { |
1603 | e89f66ec | bellard | v |= ((i >> j) & 1) << (j * 4); |
1604 | e89f66ec | bellard | } |
1605 | e89f66ec | bellard | expand4[i] = v; |
1606 | e89f66ec | bellard | |
1607 | e89f66ec | bellard | v = 0;
|
1608 | e89f66ec | bellard | for(j = 0; j < 4; j++) { |
1609 | e89f66ec | bellard | v |= ((i >> (2 * j)) & 3) << (j * 4); |
1610 | e89f66ec | bellard | } |
1611 | e89f66ec | bellard | expand2[i] = v; |
1612 | e89f66ec | bellard | } |
1613 | 17b0018b | bellard | for(i = 0; i < 16; i++) { |
1614 | 17b0018b | bellard | v = 0;
|
1615 | 17b0018b | bellard | for(j = 0; j < 4; j++) { |
1616 | 17b0018b | bellard | b = ((i >> j) & 1);
|
1617 | 17b0018b | bellard | v |= b << (2 * j);
|
1618 | 17b0018b | bellard | v |= b << (2 * j + 1); |
1619 | 17b0018b | bellard | } |
1620 | 17b0018b | bellard | expand4to8[i] = v; |
1621 | 17b0018b | bellard | } |
1622 | e89f66ec | bellard | |
1623 | e89f66ec | bellard | vga_reset(s); |
1624 | e89f66ec | bellard | |
1625 | 17b0018b | bellard | switch(ds->depth) {
|
1626 | 17b0018b | bellard | case 8: |
1627 | 17b0018b | bellard | s->rgb_to_pixel = rgb_to_pixel8_dup; |
1628 | 17b0018b | bellard | break;
|
1629 | 17b0018b | bellard | case 15: |
1630 | 17b0018b | bellard | s->rgb_to_pixel = rgb_to_pixel15_dup; |
1631 | 17b0018b | bellard | break;
|
1632 | 17b0018b | bellard | default:
|
1633 | 17b0018b | bellard | case 16: |
1634 | 17b0018b | bellard | s->rgb_to_pixel = rgb_to_pixel16_dup; |
1635 | 17b0018b | bellard | break;
|
1636 | 17b0018b | bellard | case 32: |
1637 | 17b0018b | bellard | s->rgb_to_pixel = rgb_to_pixel32_dup; |
1638 | 17b0018b | bellard | break;
|
1639 | 17b0018b | bellard | } |
1640 | 17b0018b | bellard | |
1641 | e89f66ec | bellard | s->vram_ptr = vga_ram_base; |
1642 | e89f66ec | bellard | s->vram_offset = vga_ram_offset; |
1643 | e89f66ec | bellard | s->vram_size = vga_ram_size; |
1644 | e89f66ec | bellard | s->ds = ds; |
1645 | e89f66ec | bellard | |
1646 | e89f66ec | bellard | register_ioport_write(0x3c0, 16, vga_ioport_write, 1); |
1647 | e89f66ec | bellard | |
1648 | e89f66ec | bellard | register_ioport_write(0x3b4, 2, vga_ioport_write, 1); |
1649 | e89f66ec | bellard | register_ioport_write(0x3d4, 2, vga_ioport_write, 1); |
1650 | e89f66ec | bellard | register_ioport_write(0x3ba, 1, vga_ioport_write, 1); |
1651 | e89f66ec | bellard | register_ioport_write(0x3da, 1, vga_ioport_write, 1); |
1652 | e89f66ec | bellard | |
1653 | e89f66ec | bellard | register_ioport_read(0x3c0, 16, vga_ioport_read, 1); |
1654 | e89f66ec | bellard | |
1655 | e89f66ec | bellard | register_ioport_read(0x3b4, 2, vga_ioport_read, 1); |
1656 | e89f66ec | bellard | register_ioport_read(0x3d4, 2, vga_ioport_read, 1); |
1657 | e89f66ec | bellard | register_ioport_read(0x3ba, 1, vga_ioport_read, 1); |
1658 | e89f66ec | bellard | register_ioport_read(0x3da, 1, vga_ioport_read, 1); |
1659 | cae61cef | bellard | s->bank_offset = -0xa0000;
|
1660 | e89f66ec | bellard | |
1661 | 4fa0f5d2 | bellard | #ifdef CONFIG_BOCHS_VBE
|
1662 | 4fa0f5d2 | bellard | s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0; |
1663 | cae61cef | bellard | s->vbe_bank_mask = ((s->vram_size >> 16) - 1); |
1664 | 4fa0f5d2 | bellard | register_ioport_read(0x1ce, 1, vbe_ioport_read, 2); |
1665 | 4fa0f5d2 | bellard | register_ioport_read(0x1cf, 1, vbe_ioport_read, 2); |
1666 | 4fa0f5d2 | bellard | |
1667 | 4fa0f5d2 | bellard | register_ioport_write(0x1ce, 1, vbe_ioport_write, 2); |
1668 | 4fa0f5d2 | bellard | register_ioport_write(0x1cf, 1, vbe_ioport_write, 2); |
1669 | 4fa0f5d2 | bellard | #endif
|
1670 | 4fa0f5d2 | bellard | |
1671 | e89f66ec | bellard | vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write);
|
1672 | 7138fcfb | bellard | #if defined (TARGET_I386)
|
1673 | 7138fcfb | bellard | cpu_register_physical_memory(0x000a0000, 0x20000, vga_io_memory); |
1674 | 4fa0f5d2 | bellard | #ifdef CONFIG_BOCHS_VBE
|
1675 | 4fa0f5d2 | bellard | /* XXX: use optimized standard vga accesses */
|
1676 | 4fa0f5d2 | bellard | cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS, |
1677 | 4fa0f5d2 | bellard | vga_ram_size, vga_ram_offset); |
1678 | 4fa0f5d2 | bellard | #endif
|
1679 | 7138fcfb | bellard | #elif defined (TARGET_PPC)
|
1680 | 7138fcfb | bellard | cpu_register_physical_memory(0xf00a0000, 0x20000, vga_io_memory); |
1681 | 7138fcfb | bellard | #endif
|
1682 | e89f66ec | bellard | return 0; |
1683 | e89f66ec | bellard | } |