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/*
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* QEMU 16450 UART emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <stdarg.h> |
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#include <string.h> |
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#include <getopt.h> |
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#include <inttypes.h> |
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#include <unistd.h> |
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#include <sys/mman.h> |
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#include <fcntl.h> |
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#include <signal.h> |
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#include <time.h> |
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#include <sys/time.h> |
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#include <malloc.h> |
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#include <termios.h> |
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#include <sys/poll.h> |
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#include <errno.h> |
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#include <sys/wait.h> |
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#include <netinet/in.h> |
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#include "cpu.h" |
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#include "vl.h" |
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//#define DEBUG_SERIAL
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
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#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
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#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
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#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
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#define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
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/*
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* These are the definitions for the Modem Control Register
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*/
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#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
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#define UART_MCR_OUT2 0x08 /* Out2 complement */ |
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#define UART_MCR_OUT1 0x04 /* Out1 complement */ |
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#define UART_MCR_RTS 0x02 /* RTS complement */ |
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#define UART_MCR_DTR 0x01 /* DTR complement */ |
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/*
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* These are the definitions for the Modem Status Register
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*/
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#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
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#define UART_MSR_RI 0x40 /* Ring Indicator */ |
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#define UART_MSR_DSR 0x20 /* Data Set Ready */ |
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#define UART_MSR_CTS 0x10 /* Clear to Send */ |
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#define UART_MSR_DDCD 0x08 /* Delta DCD */ |
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#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
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#define UART_MSR_DDSR 0x02 /* Delta DSR */ |
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#define UART_MSR_DCTS 0x01 /* Delta CTS */ |
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#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ |
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#define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
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#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
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#define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
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#define UART_LSR_FE 0x08 /* Frame error indicator */ |
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#define UART_LSR_PE 0x04 /* Parity error indicator */ |
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#define UART_LSR_OE 0x02 /* Overrun error indicator */ |
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#define UART_LSR_DR 0x01 /* Receiver data ready */ |
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typedef struct SerialState { |
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uint8_t divider; |
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uint8_t rbr; /* receive register */
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uint8_t ier; |
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uint8_t iir; /* read only */
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uint8_t lcr; |
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uint8_t mcr; |
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uint8_t lsr; /* read only */
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uint8_t msr; |
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uint8_t scr; |
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/* NOTE: this hidden state is necessary for tx irq generation as
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it can be reset while reading iir */
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int thr_ipending;
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int irq;
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} SerialState; |
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SerialState serial_ports[1];
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void serial_update_irq(void) |
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{
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SerialState *s = &serial_ports[0];
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if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
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s->iir = UART_IIR_RDI; |
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} else if (s->thr_ipending && (s->ier & UART_IER_THRI)) { |
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s->iir = UART_IIR_THRI; |
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} else {
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s->iir = UART_IIR_NO_INT; |
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} |
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if (s->iir != UART_IIR_NO_INT) {
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pic_set_irq(s->irq, 1);
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} else {
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pic_set_irq(s->irq, 0);
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} |
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} |
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void serial_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
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{
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SerialState *s = &serial_ports[0];
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unsigned char ch; |
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int ret;
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addr &= 7;
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#ifdef DEBUG_SERIAL
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printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
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#endif
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switch(addr) {
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default:
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case 0: |
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if (s->lcr & UART_LCR_DLAB) {
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s->divider = (s->divider & 0xff00) | val;
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} else {
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s->thr_ipending = 0;
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s->lsr &= ~UART_LSR_THRE; |
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serial_update_irq(); |
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ch = val; |
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do {
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ret = write(1, &ch, 1); |
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} while (ret != 1); |
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s->thr_ipending = 1;
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s->lsr |= UART_LSR_THRE; |
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s->lsr |= UART_LSR_TEMT; |
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serial_update_irq(); |
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} |
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break;
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case 1: |
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if (s->lcr & UART_LCR_DLAB) {
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s->divider = (s->divider & 0x00ff) | (val << 8); |
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} else {
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s->ier = val; |
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serial_update_irq(); |
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} |
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break;
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case 2: |
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break;
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case 3: |
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s->lcr = val; |
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break;
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case 4: |
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s->mcr = val; |
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break;
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case 5: |
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break;
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case 6: |
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s->msr = val; |
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break;
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case 7: |
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s->scr = val; |
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break;
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} |
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} |
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uint32_t serial_ioport_read(CPUState *env, uint32_t addr) |
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{
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SerialState *s = &serial_ports[0];
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uint32_t ret; |
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addr &= 7;
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switch(addr) {
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default:
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case 0: |
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if (s->lcr & UART_LCR_DLAB) {
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ret = s->divider & 0xff;
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} else {
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ret = s->rbr; |
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s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
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serial_update_irq(); |
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} |
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break;
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case 1: |
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if (s->lcr & UART_LCR_DLAB) {
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ret = (s->divider >> 8) & 0xff; |
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} else {
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ret = s->ier; |
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} |
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break;
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case 2: |
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ret = s->iir; |
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/* reset THR pending bit */
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if ((ret & 0x7) == UART_IIR_THRI) |
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s->thr_ipending = 0;
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serial_update_irq(); |
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break;
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case 3: |
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ret = s->lcr; |
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break;
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case 4: |
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ret = s->mcr; |
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break;
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case 5: |
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ret = s->lsr; |
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break;
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case 6: |
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if (s->mcr & UART_MCR_LOOP) {
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/* in loopback, the modem output pins are connected to the
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inputs */
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ret = (s->mcr & 0x0c) << 4; |
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ret |= (s->mcr & 0x02) << 3; |
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ret |= (s->mcr & 0x01) << 5; |
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} else {
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ret = s->msr; |
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} |
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break;
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case 7: |
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ret = s->scr; |
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break;
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} |
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#ifdef DEBUG_SERIAL
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printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
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#endif
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return ret;
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} |
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int serial_can_receive(void) |
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{
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SerialState *s = &serial_ports[0];
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return !(s->lsr & UART_LSR_DR);
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} |
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void serial_receive_byte(int ch) |
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{
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SerialState *s = &serial_ports[0];
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s->rbr = ch; |
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s->lsr |= UART_LSR_DR; |
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serial_update_irq(); |
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} |
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void serial_receive_break(void) |
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{
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SerialState *s = &serial_ports[0];
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s->rbr = 0;
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s->lsr |= UART_LSR_BI | UART_LSR_DR; |
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serial_update_irq(); |
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} |
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void serial_init(int base, int irq) |
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{
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SerialState *s = &serial_ports[0];
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s->irq = irq; |
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s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
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s->iir = UART_IIR_NO_INT; |
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register_ioport_write(base, 8, serial_ioport_write, 1); |
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register_ioport_read(base, 8, serial_ioport_read, 1); |
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} |