Revision 80d11f44
| b/target-ppc/cpu.h | ||
|---|---|---|
| 822 | 822 |
#define xer_bc env->xer[0] |
| 823 | 823 |
|
| 824 | 824 |
/* SPR definitions */ |
| 825 |
#define SPR_MQ (0x000) |
|
| 826 |
#define SPR_XER (0x001) |
|
| 827 |
#define SPR_601_VRTCU (0x004) |
|
| 828 |
#define SPR_601_VRTCL (0x005) |
|
| 829 |
#define SPR_601_UDECR (0x006) |
|
| 830 |
#define SPR_LR (0x008) |
|
| 831 |
#define SPR_CTR (0x009) |
|
| 832 |
#define SPR_DSISR (0x012) |
|
| 833 |
#define SPR_DAR (0x013) /* DAE for PowerPC 601 */ |
|
| 834 |
#define SPR_601_RTCU (0x014) |
|
| 835 |
#define SPR_601_RTCL (0x015) |
|
| 836 |
#define SPR_DECR (0x016) |
|
| 837 |
#define SPR_SDR1 (0x019) |
|
| 838 |
#define SPR_SRR0 (0x01A) |
|
| 839 |
#define SPR_SRR1 (0x01B) |
|
| 840 |
#define SPR_AMR (0x01D) |
|
| 841 |
#define SPR_BOOKE_PID (0x030) |
|
| 842 |
#define SPR_BOOKE_DECAR (0x036) |
|
| 843 |
#define SPR_BOOKE_CSRR0 (0x03A) |
|
| 844 |
#define SPR_BOOKE_CSRR1 (0x03B) |
|
| 845 |
#define SPR_BOOKE_DEAR (0x03D) |
|
| 846 |
#define SPR_BOOKE_ESR (0x03E) |
|
| 847 |
#define SPR_BOOKE_IVPR (0x03F) |
|
| 848 |
#define SPR_8xx_EIE (0x050) |
|
| 849 |
#define SPR_8xx_EID (0x051) |
|
| 850 |
#define SPR_8xx_NRE (0x052) |
|
| 851 |
#define SPR_CTRL (0x088) |
|
| 852 |
#define SPR_58x_CMPA (0x090) |
|
| 853 |
#define SPR_58x_CMPB (0x091) |
|
| 854 |
#define SPR_58x_CMPC (0x092) |
|
| 855 |
#define SPR_58x_CMPD (0x093) |
|
| 856 |
#define SPR_58x_ICR (0x094) |
|
| 857 |
#define SPR_58x_DER (0x094) |
|
| 858 |
#define SPR_58x_COUNTA (0x096) |
|
| 859 |
#define SPR_58x_COUNTB (0x097) |
|
| 860 |
#define SPR_UCTRL (0x098) |
|
| 861 |
#define SPR_58x_CMPE (0x098) |
|
| 862 |
#define SPR_58x_CMPF (0x099) |
|
| 863 |
#define SPR_58x_CMPG (0x09A) |
|
| 864 |
#define SPR_58x_CMPH (0x09B) |
|
| 865 |
#define SPR_58x_LCTRL1 (0x09C) |
|
| 866 |
#define SPR_58x_LCTRL2 (0x09D) |
|
| 867 |
#define SPR_58x_ICTRL (0x09E) |
|
| 868 |
#define SPR_58x_BAR (0x09F) |
|
| 869 |
#define SPR_VRSAVE (0x100) |
|
| 870 |
#define SPR_USPRG0 (0x100) |
|
| 871 |
#define SPR_USPRG1 (0x101) |
|
| 872 |
#define SPR_USPRG2 (0x102) |
|
| 873 |
#define SPR_USPRG3 (0x103) |
|
| 874 |
#define SPR_USPRG4 (0x104) |
|
| 875 |
#define SPR_USPRG5 (0x105) |
|
| 876 |
#define SPR_USPRG6 (0x106) |
|
| 877 |
#define SPR_USPRG7 (0x107) |
|
| 878 |
#define SPR_VTBL (0x10C) |
|
| 879 |
#define SPR_VTBU (0x10D) |
|
| 880 |
#define SPR_SPRG0 (0x110) |
|
| 881 |
#define SPR_SPRG1 (0x111) |
|
| 882 |
#define SPR_SPRG2 (0x112) |
|
| 883 |
#define SPR_SPRG3 (0x113) |
|
| 884 |
#define SPR_SPRG4 (0x114) |
|
| 885 |
#define SPR_SCOMC (0x114) |
|
| 886 |
#define SPR_SPRG5 (0x115) |
|
| 887 |
#define SPR_SCOMD (0x115) |
|
| 888 |
#define SPR_SPRG6 (0x116) |
|
| 889 |
#define SPR_SPRG7 (0x117) |
|
| 890 |
#define SPR_ASR (0x118) |
|
| 891 |
#define SPR_EAR (0x11A) |
|
| 892 |
#define SPR_TBL (0x11C) |
|
| 893 |
#define SPR_TBU (0x11D) |
|
| 894 |
#define SPR_TBU40 (0x11E) |
|
| 895 |
#define SPR_SVR (0x11E) |
|
| 896 |
#define SPR_BOOKE_PIR (0x11E) |
|
| 897 |
#define SPR_PVR (0x11F) |
|
| 898 |
#define SPR_HSPRG0 (0x130) |
|
| 899 |
#define SPR_BOOKE_DBSR (0x130) |
|
| 900 |
#define SPR_HSPRG1 (0x131) |
|
| 901 |
#define SPR_HDSISR (0x132) |
|
| 902 |
#define SPR_HDAR (0x133) |
|
| 903 |
#define SPR_BOOKE_DBCR0 (0x134) |
|
| 904 |
#define SPR_IBCR (0x135) |
|
| 905 |
#define SPR_PURR (0x135) |
|
| 906 |
#define SPR_BOOKE_DBCR1 (0x135) |
|
| 907 |
#define SPR_DBCR (0x136) |
|
| 908 |
#define SPR_HDEC (0x136) |
|
| 909 |
#define SPR_BOOKE_DBCR2 (0x136) |
|
| 910 |
#define SPR_HIOR (0x137) |
|
| 911 |
#define SPR_MBAR (0x137) |
|
| 912 |
#define SPR_RMOR (0x138) |
|
| 913 |
#define SPR_BOOKE_IAC1 (0x138) |
|
| 914 |
#define SPR_HRMOR (0x139) |
|
| 915 |
#define SPR_BOOKE_IAC2 (0x139) |
|
| 916 |
#define SPR_HSRR0 (0x13A) |
|
| 917 |
#define SPR_BOOKE_IAC3 (0x13A) |
|
| 918 |
#define SPR_HSRR1 (0x13B) |
|
| 919 |
#define SPR_BOOKE_IAC4 (0x13B) |
|
| 920 |
#define SPR_LPCR (0x13C) |
|
| 921 |
#define SPR_BOOKE_DAC1 (0x13C) |
|
| 922 |
#define SPR_LPIDR (0x13D) |
|
| 923 |
#define SPR_DABR2 (0x13D) |
|
| 924 |
#define SPR_BOOKE_DAC2 (0x13D) |
|
| 925 |
#define SPR_BOOKE_DVC1 (0x13E) |
|
| 926 |
#define SPR_BOOKE_DVC2 (0x13F) |
|
| 927 |
#define SPR_BOOKE_TSR (0x150) |
|
| 928 |
#define SPR_BOOKE_TCR (0x154) |
|
| 929 |
#define SPR_BOOKE_IVOR0 (0x190) |
|
| 930 |
#define SPR_BOOKE_IVOR1 (0x191) |
|
| 931 |
#define SPR_BOOKE_IVOR2 (0x192) |
|
| 932 |
#define SPR_BOOKE_IVOR3 (0x193) |
|
| 933 |
#define SPR_BOOKE_IVOR4 (0x194) |
|
| 934 |
#define SPR_BOOKE_IVOR5 (0x195) |
|
| 935 |
#define SPR_BOOKE_IVOR6 (0x196) |
|
| 936 |
#define SPR_BOOKE_IVOR7 (0x197) |
|
| 937 |
#define SPR_BOOKE_IVOR8 (0x198) |
|
| 938 |
#define SPR_BOOKE_IVOR9 (0x199) |
|
| 939 |
#define SPR_BOOKE_IVOR10 (0x19A) |
|
| 940 |
#define SPR_BOOKE_IVOR11 (0x19B) |
|
| 941 |
#define SPR_BOOKE_IVOR12 (0x19C) |
|
| 942 |
#define SPR_BOOKE_IVOR13 (0x19D) |
|
| 943 |
#define SPR_BOOKE_IVOR14 (0x19E) |
|
| 944 |
#define SPR_BOOKE_IVOR15 (0x19F) |
|
| 945 |
#define SPR_BOOKE_SPEFSCR (0x200) |
|
| 946 |
#define SPR_E500_BBEAR (0x201) |
|
| 947 |
#define SPR_E500_BBTAR (0x202) |
|
| 948 |
#define SPR_ATBL (0x20E) |
|
| 949 |
#define SPR_ATBU (0x20F) |
|
| 950 |
#define SPR_IBAT0U (0x210) |
|
| 951 |
#define SPR_BOOKE_IVOR32 (0x210) |
|
| 952 |
#define SPR_IBAT0L (0x211) |
|
| 953 |
#define SPR_BOOKE_IVOR33 (0x211) |
|
| 954 |
#define SPR_IBAT1U (0x212) |
|
| 955 |
#define SPR_BOOKE_IVOR34 (0x212) |
|
| 956 |
#define SPR_IBAT1L (0x213) |
|
| 957 |
#define SPR_BOOKE_IVOR35 (0x213) |
|
| 958 |
#define SPR_IBAT2U (0x214) |
|
| 959 |
#define SPR_BOOKE_IVOR36 (0x214) |
|
| 960 |
#define SPR_IBAT2L (0x215) |
|
| 961 |
#define SPR_E500_L1CFG0 (0x215) |
|
| 962 |
#define SPR_BOOKE_IVOR37 (0x215) |
|
| 963 |
#define SPR_IBAT3U (0x216) |
|
| 964 |
#define SPR_E500_L1CFG1 (0x216) |
|
| 965 |
#define SPR_IBAT3L (0x217) |
|
| 966 |
#define SPR_DBAT0U (0x218) |
|
| 967 |
#define SPR_DBAT0L (0x219) |
|
| 968 |
#define SPR_DBAT1U (0x21A) |
|
| 969 |
#define SPR_DBAT1L (0x21B) |
|
| 970 |
#define SPR_DBAT2U (0x21C) |
|
| 971 |
#define SPR_DBAT2L (0x21D) |
|
| 972 |
#define SPR_DBAT3U (0x21E) |
|
| 973 |
#define SPR_DBAT3L (0x21F) |
|
| 974 |
#define SPR_IBAT4U (0x230) |
|
| 975 |
#define SPR_IBAT4L (0x231) |
|
| 976 |
#define SPR_IBAT5U (0x232) |
|
| 977 |
#define SPR_IBAT5L (0x233) |
|
| 978 |
#define SPR_IBAT6U (0x234) |
|
| 979 |
#define SPR_IBAT6L (0x235) |
|
| 980 |
#define SPR_IBAT7U (0x236) |
|
| 981 |
#define SPR_IBAT7L (0x237) |
|
| 982 |
#define SPR_DBAT4U (0x238) |
|
| 983 |
#define SPR_DBAT4L (0x239) |
|
| 984 |
#define SPR_DBAT5U (0x23A) |
|
| 985 |
#define SPR_BOOKE_MCSRR0 (0x23A) |
|
| 986 |
#define SPR_DBAT5L (0x23B) |
|
| 987 |
#define SPR_BOOKE_MCSRR1 (0x23B) |
|
| 988 |
#define SPR_DBAT6U (0x23C) |
|
| 989 |
#define SPR_BOOKE_MCSR (0x23C) |
|
| 990 |
#define SPR_DBAT6L (0x23D) |
|
| 991 |
#define SPR_E500_MCAR (0x23D) |
|
| 992 |
#define SPR_DBAT7U (0x23E) |
|
| 993 |
#define SPR_BOOKE_DSRR0 (0x23E) |
|
| 994 |
#define SPR_DBAT7L (0x23F) |
|
| 995 |
#define SPR_BOOKE_DSRR1 (0x23F) |
|
| 996 |
#define SPR_BOOKE_SPRG8 (0x25C) |
|
| 997 |
#define SPR_BOOKE_SPRG9 (0x25D) |
|
| 998 |
#define SPR_BOOKE_MAS0 (0x270) |
|
| 999 |
#define SPR_BOOKE_MAS1 (0x271) |
|
| 1000 |
#define SPR_BOOKE_MAS2 (0x272) |
|
| 1001 |
#define SPR_BOOKE_MAS3 (0x273) |
|
| 1002 |
#define SPR_BOOKE_MAS4 (0x274) |
|
| 1003 |
#define SPR_BOOKE_MAS6 (0x276) |
|
| 1004 |
#define SPR_BOOKE_PID1 (0x279) |
|
| 1005 |
#define SPR_BOOKE_PID2 (0x27A) |
|
| 1006 |
#define SPR_BOOKE_TLB0CFG (0x2B0) |
|
| 1007 |
#define SPR_BOOKE_TLB1CFG (0x2B1) |
|
| 1008 |
#define SPR_BOOKE_TLB2CFG (0x2B2) |
|
| 1009 |
#define SPR_BOOKE_TLB3CFG (0x2B3) |
|
| 1010 |
#define SPR_BOOKE_EPR (0x2BE) |
|
| 1011 |
#define SPR_PERF0 (0x300) |
|
| 1012 |
#define SPR_PERF1 (0x301) |
|
| 1013 |
#define SPR_PERF2 (0x302) |
|
| 1014 |
#define SPR_PERF3 (0x303) |
|
| 1015 |
#define SPR_PERF4 (0x304) |
|
| 1016 |
#define SPR_PERF5 (0x305) |
|
| 1017 |
#define SPR_PERF6 (0x306) |
|
| 1018 |
#define SPR_PERF7 (0x307) |
|
| 1019 |
#define SPR_PERF8 (0x308) |
|
| 1020 |
#define SPR_PERF9 (0x309) |
|
| 1021 |
#define SPR_PERFA (0x30A) |
|
| 1022 |
#define SPR_PERFB (0x30B) |
|
| 1023 |
#define SPR_PERFC (0x30C) |
|
| 1024 |
#define SPR_PERFD (0x30D) |
|
| 1025 |
#define SPR_PERFE (0x30E) |
|
| 1026 |
#define SPR_PERFF (0x30F) |
|
| 1027 |
#define SPR_UPERF0 (0x310) |
|
| 1028 |
#define SPR_UPERF1 (0x311) |
|
| 1029 |
#define SPR_UPERF2 (0x312) |
|
| 1030 |
#define SPR_UPERF3 (0x313) |
|
| 1031 |
#define SPR_UPERF4 (0x314) |
|
| 1032 |
#define SPR_UPERF5 (0x315) |
|
| 1033 |
#define SPR_UPERF6 (0x316) |
|
| 1034 |
#define SPR_UPERF7 (0x317) |
|
| 1035 |
#define SPR_UPERF8 (0x318) |
|
| 1036 |
#define SPR_UPERF9 (0x319) |
|
| 1037 |
#define SPR_UPERFA (0x31A) |
|
| 1038 |
#define SPR_UPERFB (0x31B) |
|
| 1039 |
#define SPR_UPERFC (0x31C) |
|
| 1040 |
#define SPR_UPERFD (0x31D) |
|
| 1041 |
#define SPR_UPERFE (0x31E) |
|
| 1042 |
#define SPR_UPERFF (0x31F) |
|
| 1043 |
#define SPR_440_INV0 (0x370) |
|
| 1044 |
#define SPR_440_INV1 (0x371) |
|
| 1045 |
#define SPR_440_INV2 (0x372) |
|
| 1046 |
#define SPR_440_INV3 (0x373) |
|
| 1047 |
#define SPR_440_ITV0 (0x374) |
|
| 1048 |
#define SPR_440_ITV1 (0x375) |
|
| 1049 |
#define SPR_440_ITV2 (0x376) |
|
| 1050 |
#define SPR_440_ITV3 (0x377) |
|
| 1051 |
#define SPR_440_CCR1 (0x378) |
|
| 1052 |
#define SPR_DCRIPR (0x37B) |
|
| 1053 |
#define SPR_PPR (0x380) |
|
| 1054 |
#define SPR_440_DNV0 (0x390) |
|
| 1055 |
#define SPR_440_DNV1 (0x391) |
|
| 1056 |
#define SPR_440_DNV2 (0x392) |
|
| 1057 |
#define SPR_440_DNV3 (0x393) |
|
| 1058 |
#define SPR_440_DTV0 (0x394) |
|
| 1059 |
#define SPR_440_DTV1 (0x395) |
|
| 1060 |
#define SPR_440_DTV2 (0x396) |
|
| 1061 |
#define SPR_440_DTV3 (0x397) |
|
| 1062 |
#define SPR_440_DVLIM (0x398) |
|
| 1063 |
#define SPR_440_IVLIM (0x399) |
|
| 1064 |
#define SPR_440_RSTCFG (0x39B) |
|
| 1065 |
#define SPR_BOOKE_DCDBTRL (0x39C) |
|
| 1066 |
#define SPR_BOOKE_DCDBTRH (0x39D) |
|
| 1067 |
#define SPR_BOOKE_ICDBTRL (0x39E) |
|
| 1068 |
#define SPR_BOOKE_ICDBTRH (0x39F) |
|
| 1069 |
#define SPR_UMMCR2 (0x3A0) |
|
| 1070 |
#define SPR_UPMC5 (0x3A1) |
|
| 1071 |
#define SPR_UPMC6 (0x3A2) |
|
| 1072 |
#define SPR_UBAMR (0x3A7) |
|
| 1073 |
#define SPR_UMMCR0 (0x3A8) |
|
| 1074 |
#define SPR_UPMC1 (0x3A9) |
|
| 1075 |
#define SPR_UPMC2 (0x3AA) |
|
| 1076 |
#define SPR_USIAR (0x3AB) |
|
| 1077 |
#define SPR_UMMCR1 (0x3AC) |
|
| 1078 |
#define SPR_UPMC3 (0x3AD) |
|
| 1079 |
#define SPR_UPMC4 (0x3AE) |
|
| 1080 |
#define SPR_USDA (0x3AF) |
|
| 1081 |
#define SPR_40x_ZPR (0x3B0) |
|
| 1082 |
#define SPR_BOOKE_MAS7 (0x3B0) |
|
| 1083 |
#define SPR_620_PMR0 (0x3B0) |
|
| 1084 |
#define SPR_MMCR2 (0x3B0) |
|
| 1085 |
#define SPR_PMC5 (0x3B1) |
|
| 1086 |
#define SPR_40x_PID (0x3B1) |
|
| 1087 |
#define SPR_620_PMR1 (0x3B1) |
|
| 1088 |
#define SPR_PMC6 (0x3B2) |
|
| 1089 |
#define SPR_440_MMUCR (0x3B2) |
|
| 1090 |
#define SPR_620_PMR2 (0x3B2) |
|
| 1091 |
#define SPR_4xx_CCR0 (0x3B3) |
|
| 1092 |
#define SPR_BOOKE_EPLC (0x3B3) |
|
| 1093 |
#define SPR_620_PMR3 (0x3B3) |
|
| 1094 |
#define SPR_405_IAC3 (0x3B4) |
|
| 1095 |
#define SPR_BOOKE_EPSC (0x3B4) |
|
| 1096 |
#define SPR_620_PMR4 (0x3B4) |
|
| 1097 |
#define SPR_405_IAC4 (0x3B5) |
|
| 1098 |
#define SPR_620_PMR5 (0x3B5) |
|
| 1099 |
#define SPR_405_DVC1 (0x3B6) |
|
| 1100 |
#define SPR_620_PMR6 (0x3B6) |
|
| 1101 |
#define SPR_405_DVC2 (0x3B7) |
|
| 1102 |
#define SPR_620_PMR7 (0x3B7) |
|
| 1103 |
#define SPR_BAMR (0x3B7) |
|
| 1104 |
#define SPR_MMCR0 (0x3B8) |
|
| 1105 |
#define SPR_620_PMR8 (0x3B8) |
|
| 1106 |
#define SPR_PMC1 (0x3B9) |
|
| 1107 |
#define SPR_40x_SGR (0x3B9) |
|
| 1108 |
#define SPR_620_PMR9 (0x3B9) |
|
| 1109 |
#define SPR_PMC2 (0x3BA) |
|
| 1110 |
#define SPR_40x_DCWR (0x3BA) |
|
| 1111 |
#define SPR_620_PMRA (0x3BA) |
|
| 1112 |
#define SPR_SIAR (0x3BB) |
|
| 1113 |
#define SPR_405_SLER (0x3BB) |
|
| 1114 |
#define SPR_620_PMRB (0x3BB) |
|
| 1115 |
#define SPR_MMCR1 (0x3BC) |
|
| 1116 |
#define SPR_405_SU0R (0x3BC) |
|
| 1117 |
#define SPR_620_PMRC (0x3BC) |
|
| 1118 |
#define SPR_401_SKR (0x3BC) |
|
| 1119 |
#define SPR_PMC3 (0x3BD) |
|
| 1120 |
#define SPR_405_DBCR1 (0x3BD) |
|
| 1121 |
#define SPR_620_PMRD (0x3BD) |
|
| 1122 |
#define SPR_PMC4 (0x3BE) |
|
| 1123 |
#define SPR_620_PMRE (0x3BE) |
|
| 1124 |
#define SPR_SDA (0x3BF) |
|
| 1125 |
#define SPR_620_PMRF (0x3BF) |
|
| 1126 |
#define SPR_403_VTBL (0x3CC) |
|
| 1127 |
#define SPR_403_VTBU (0x3CD) |
|
| 1128 |
#define SPR_DMISS (0x3D0) |
|
| 1129 |
#define SPR_DCMP (0x3D1) |
|
| 1130 |
#define SPR_HASH1 (0x3D2) |
|
| 1131 |
#define SPR_HASH2 (0x3D3) |
|
| 1132 |
#define SPR_BOOKE_ICDBDR (0x3D3) |
|
| 1133 |
#define SPR_TLBMISS (0x3D4) |
|
| 1134 |
#define SPR_IMISS (0x3D4) |
|
| 1135 |
#define SPR_40x_ESR (0x3D4) |
|
| 1136 |
#define SPR_PTEHI (0x3D5) |
|
| 1137 |
#define SPR_ICMP (0x3D5) |
|
| 1138 |
#define SPR_40x_DEAR (0x3D5) |
|
| 1139 |
#define SPR_PTELO (0x3D6) |
|
| 1140 |
#define SPR_RPA (0x3D6) |
|
| 1141 |
#define SPR_40x_EVPR (0x3D6) |
|
| 1142 |
#define SPR_L3PM (0x3D7) |
|
| 1143 |
#define SPR_403_CDBCR (0x3D7) |
|
| 1144 |
#define SPR_L3OHCR (0x3D8) |
|
| 1145 |
#define SPR_TCR (0x3D8) |
|
| 1146 |
#define SPR_40x_TSR (0x3D8) |
|
| 1147 |
#define SPR_IBR (0x3DA) |
|
| 1148 |
#define SPR_40x_TCR (0x3DA) |
|
| 1149 |
#define SPR_ESASRR (0x3DB) |
|
| 1150 |
#define SPR_40x_PIT (0x3DB) |
|
| 1151 |
#define SPR_403_TBL (0x3DC) |
|
| 1152 |
#define SPR_403_TBU (0x3DD) |
|
| 1153 |
#define SPR_SEBR (0x3DE) |
|
| 1154 |
#define SPR_40x_SRR2 (0x3DE) |
|
| 1155 |
#define SPR_SER (0x3DF) |
|
| 1156 |
#define SPR_40x_SRR3 (0x3DF) |
|
| 1157 |
#define SPR_L3ITCR0 (0x3E8) |
|
| 1158 |
#define SPR_L3ITCR1 (0x3E9) |
|
| 1159 |
#define SPR_L3ITCR2 (0x3EA) |
|
| 1160 |
#define SPR_L3ITCR3 (0x3EB) |
|
| 1161 |
#define SPR_HID0 (0x3F0) |
|
| 1162 |
#define SPR_40x_DBSR (0x3F0) |
|
| 1163 |
#define SPR_HID1 (0x3F1) |
|
| 1164 |
#define SPR_IABR (0x3F2) |
|
| 1165 |
#define SPR_40x_DBCR0 (0x3F2) |
|
| 1166 |
#define SPR_601_HID2 (0x3F2) |
|
| 1167 |
#define SPR_E500_L1CSR0 (0x3F2) |
|
| 1168 |
#define SPR_ICTRL (0x3F3) |
|
| 1169 |
#define SPR_HID2 (0x3F3) |
|
| 1170 |
#define SPR_E500_L1CSR1 (0x3F3) |
|
| 1171 |
#define SPR_440_DBDR (0x3F3) |
|
| 1172 |
#define SPR_LDSTDB (0x3F4) |
|
| 1173 |
#define SPR_40x_IAC1 (0x3F4) |
|
| 1174 |
#define SPR_MMUCSR0 (0x3F4) |
|
| 1175 |
#define SPR_DABR (0x3F5) |
|
| 825 |
#define SPR_MQ (0x000) |
|
| 826 |
#define SPR_XER (0x001) |
|
| 827 |
#define SPR_601_VRTCU (0x004) |
|
| 828 |
#define SPR_601_VRTCL (0x005) |
|
| 829 |
#define SPR_601_UDECR (0x006) |
|
| 830 |
#define SPR_LR (0x008) |
|
| 831 |
#define SPR_CTR (0x009) |
|
| 832 |
#define SPR_DSISR (0x012) |
|
| 833 |
#define SPR_DAR (0x013) /* DAE for PowerPC 601 */ |
|
| 834 |
#define SPR_601_RTCU (0x014) |
|
| 835 |
#define SPR_601_RTCL (0x015) |
|
| 836 |
#define SPR_DECR (0x016) |
|
| 837 |
#define SPR_SDR1 (0x019) |
|
| 838 |
#define SPR_SRR0 (0x01A) |
|
| 839 |
#define SPR_SRR1 (0x01B) |
|
| 840 |
#define SPR_AMR (0x01D) |
|
| 841 |
#define SPR_BOOKE_PID (0x030) |
|
| 842 |
#define SPR_BOOKE_DECAR (0x036) |
|
| 843 |
#define SPR_BOOKE_CSRR0 (0x03A) |
|
| 844 |
#define SPR_BOOKE_CSRR1 (0x03B) |
|
| 845 |
#define SPR_BOOKE_DEAR (0x03D) |
|
| 846 |
#define SPR_BOOKE_ESR (0x03E) |
|
| 847 |
#define SPR_BOOKE_IVPR (0x03F) |
|
| 848 |
#define SPR_MPC_EIE (0x050) |
|
| 849 |
#define SPR_MPC_EID (0x051) |
|
| 850 |
#define SPR_MPC_NRI (0x052) |
|
| 851 |
#define SPR_CTRL (0x088) |
|
| 852 |
#define SPR_MPC_CMPA (0x090) |
|
| 853 |
#define SPR_MPC_CMPB (0x091) |
|
| 854 |
#define SPR_MPC_CMPC (0x092) |
|
| 855 |
#define SPR_MPC_CMPD (0x093) |
|
| 856 |
#define SPR_MPC_ECR (0x094) |
|
| 857 |
#define SPR_MPC_DER (0x095) |
|
| 858 |
#define SPR_MPC_COUNTA (0x096) |
|
| 859 |
#define SPR_MPC_COUNTB (0x097) |
|
| 860 |
#define SPR_UCTRL (0x098) |
|
| 861 |
#define SPR_MPC_CMPE (0x098) |
|
| 862 |
#define SPR_MPC_CMPF (0x099) |
|
| 863 |
#define SPR_MPC_CMPG (0x09A) |
|
| 864 |
#define SPR_MPC_CMPH (0x09B) |
|
| 865 |
#define SPR_MPC_LCTRL1 (0x09C) |
|
| 866 |
#define SPR_MPC_LCTRL2 (0x09D) |
|
| 867 |
#define SPR_MPC_ICTRL (0x09E) |
|
| 868 |
#define SPR_MPC_BAR (0x09F) |
|
| 869 |
#define SPR_VRSAVE (0x100) |
|
| 870 |
#define SPR_USPRG0 (0x100) |
|
| 871 |
#define SPR_USPRG1 (0x101) |
|
| 872 |
#define SPR_USPRG2 (0x102) |
|
| 873 |
#define SPR_USPRG3 (0x103) |
|
| 874 |
#define SPR_USPRG4 (0x104) |
|
| 875 |
#define SPR_USPRG5 (0x105) |
|
| 876 |
#define SPR_USPRG6 (0x106) |
|
| 877 |
#define SPR_USPRG7 (0x107) |
|
| 878 |
#define SPR_VTBL (0x10C) |
|
| 879 |
#define SPR_VTBU (0x10D) |
|
| 880 |
#define SPR_SPRG0 (0x110) |
|
| 881 |
#define SPR_SPRG1 (0x111) |
|
| 882 |
#define SPR_SPRG2 (0x112) |
|
| 883 |
#define SPR_SPRG3 (0x113) |
|
| 884 |
#define SPR_SPRG4 (0x114) |
|
| 885 |
#define SPR_SCOMC (0x114) |
|
| 886 |
#define SPR_SPRG5 (0x115) |
|
| 887 |
#define SPR_SCOMD (0x115) |
|
| 888 |
#define SPR_SPRG6 (0x116) |
|
| 889 |
#define SPR_SPRG7 (0x117) |
|
| 890 |
#define SPR_ASR (0x118) |
|
| 891 |
#define SPR_EAR (0x11A) |
|
| 892 |
#define SPR_TBL (0x11C) |
|
| 893 |
#define SPR_TBU (0x11D) |
|
| 894 |
#define SPR_TBU40 (0x11E) |
|
| 895 |
#define SPR_SVR (0x11E) |
|
| 896 |
#define SPR_BOOKE_PIR (0x11E) |
|
| 897 |
#define SPR_PVR (0x11F) |
|
| 898 |
#define SPR_HSPRG0 (0x130) |
|
| 899 |
#define SPR_BOOKE_DBSR (0x130) |
|
| 900 |
#define SPR_HSPRG1 (0x131) |
|
| 901 |
#define SPR_HDSISR (0x132) |
|
| 902 |
#define SPR_HDAR (0x133) |
|
| 903 |
#define SPR_BOOKE_DBCR0 (0x134) |
|
| 904 |
#define SPR_IBCR (0x135) |
|
| 905 |
#define SPR_PURR (0x135) |
|
| 906 |
#define SPR_BOOKE_DBCR1 (0x135) |
|
| 907 |
#define SPR_DBCR (0x136) |
|
| 908 |
#define SPR_HDEC (0x136) |
|
| 909 |
#define SPR_BOOKE_DBCR2 (0x136) |
|
| 910 |
#define SPR_HIOR (0x137) |
|
| 911 |
#define SPR_MBAR (0x137) |
|
| 912 |
#define SPR_RMOR (0x138) |
|
| 913 |
#define SPR_BOOKE_IAC1 (0x138) |
|
| 914 |
#define SPR_HRMOR (0x139) |
|
| 915 |
#define SPR_BOOKE_IAC2 (0x139) |
|
| 916 |
#define SPR_HSRR0 (0x13A) |
|
| 917 |
#define SPR_BOOKE_IAC3 (0x13A) |
|
| 918 |
#define SPR_HSRR1 (0x13B) |
|
| 919 |
#define SPR_BOOKE_IAC4 (0x13B) |
|
| 920 |
#define SPR_LPCR (0x13C) |
|
| 921 |
#define SPR_BOOKE_DAC1 (0x13C) |
|
| 922 |
#define SPR_LPIDR (0x13D) |
|
| 923 |
#define SPR_DABR2 (0x13D) |
|
| 924 |
#define SPR_BOOKE_DAC2 (0x13D) |
|
| 925 |
#define SPR_BOOKE_DVC1 (0x13E) |
|
| 926 |
#define SPR_BOOKE_DVC2 (0x13F) |
|
| 927 |
#define SPR_BOOKE_TSR (0x150) |
|
| 928 |
#define SPR_BOOKE_TCR (0x154) |
|
| 929 |
#define SPR_BOOKE_IVOR0 (0x190) |
|
| 930 |
#define SPR_BOOKE_IVOR1 (0x191) |
|
| 931 |
#define SPR_BOOKE_IVOR2 (0x192) |
|
| 932 |
#define SPR_BOOKE_IVOR3 (0x193) |
|
| 933 |
#define SPR_BOOKE_IVOR4 (0x194) |
|
| 934 |
#define SPR_BOOKE_IVOR5 (0x195) |
|
| 935 |
#define SPR_BOOKE_IVOR6 (0x196) |
|
| 936 |
#define SPR_BOOKE_IVOR7 (0x197) |
|
| 937 |
#define SPR_BOOKE_IVOR8 (0x198) |
|
| 938 |
#define SPR_BOOKE_IVOR9 (0x199) |
|
| 939 |
#define SPR_BOOKE_IVOR10 (0x19A) |
|
| 940 |
#define SPR_BOOKE_IVOR11 (0x19B) |
|
| 941 |
#define SPR_BOOKE_IVOR12 (0x19C) |
|
| 942 |
#define SPR_BOOKE_IVOR13 (0x19D) |
|
| 943 |
#define SPR_BOOKE_IVOR14 (0x19E) |
|
| 944 |
#define SPR_BOOKE_IVOR15 (0x19F) |
|
| 945 |
#define SPR_BOOKE_SPEFSCR (0x200) |
|
| 946 |
#define SPR_Exxx_BBEAR (0x201) |
|
| 947 |
#define SPR_Exxx_BBTAR (0x202) |
|
| 948 |
#define SPR_Exxx_L1CFG0 (0x203) |
|
| 949 |
#define SPR_Exxx_NPIDR (0x205) |
|
| 950 |
#define SPR_ATBL (0x20E) |
|
| 951 |
#define SPR_ATBU (0x20F) |
|
| 952 |
#define SPR_IBAT0U (0x210) |
|
| 953 |
#define SPR_BOOKE_IVOR32 (0x210) |
|
| 954 |
#define SPR_RCPU_MI_GRA (0x210) |
|
| 955 |
#define SPR_IBAT0L (0x211) |
|
| 956 |
#define SPR_BOOKE_IVOR33 (0x211) |
|
| 957 |
#define SPR_IBAT1U (0x212) |
|
| 958 |
#define SPR_BOOKE_IVOR34 (0x212) |
|
| 959 |
#define SPR_IBAT1L (0x213) |
|
| 960 |
#define SPR_BOOKE_IVOR35 (0x213) |
|
| 961 |
#define SPR_IBAT2U (0x214) |
|
| 962 |
#define SPR_BOOKE_IVOR36 (0x214) |
|
| 963 |
#define SPR_IBAT2L (0x215) |
|
| 964 |
#define SPR_BOOKE_IVOR37 (0x215) |
|
| 965 |
#define SPR_IBAT3U (0x216) |
|
| 966 |
#define SPR_IBAT3L (0x217) |
|
| 967 |
#define SPR_DBAT0U (0x218) |
|
| 968 |
#define SPR_RCPU_L2U_GRA (0x218) |
|
| 969 |
#define SPR_DBAT0L (0x219) |
|
| 970 |
#define SPR_DBAT1U (0x21A) |
|
| 971 |
#define SPR_DBAT1L (0x21B) |
|
| 972 |
#define SPR_DBAT2U (0x21C) |
|
| 973 |
#define SPR_DBAT2L (0x21D) |
|
| 974 |
#define SPR_DBAT3U (0x21E) |
|
| 975 |
#define SPR_DBAT3L (0x21F) |
|
| 976 |
#define SPR_IBAT4U (0x230) |
|
| 977 |
#define SPR_RPCU_BBCMCR (0x230) |
|
| 978 |
#define SPR_MPC_IC_CST (0x230) |
|
| 979 |
#define SPR_Exxx_CTXCR (0x230) |
|
| 980 |
#define SPR_IBAT4L (0x231) |
|
| 981 |
#define SPR_MPC_IC_ADR (0x231) |
|
| 982 |
#define SPR_Exxx_DBCR3 (0x231) |
|
| 983 |
#define SPR_IBAT5U (0x232) |
|
| 984 |
#define SPR_MPC_IC_DAT (0x232) |
|
| 985 |
#define SPR_Exxx_DBCNT (0x232) |
|
| 986 |
#define SPR_IBAT5L (0x233) |
|
| 987 |
#define SPR_IBAT6U (0x234) |
|
| 988 |
#define SPR_IBAT6L (0x235) |
|
| 989 |
#define SPR_IBAT7U (0x236) |
|
| 990 |
#define SPR_IBAT7L (0x237) |
|
| 991 |
#define SPR_DBAT4U (0x238) |
|
| 992 |
#define SPR_RCPU_L2U_MCR (0x238) |
|
| 993 |
#define SPR_MPC_DC_CST (0x238) |
|
| 994 |
#define SPR_Exxx_ALTCTXCR (0x238) |
|
| 995 |
#define SPR_DBAT4L (0x239) |
|
| 996 |
#define SPR_MPC_DC_ADR (0x239) |
|
| 997 |
#define SPR_DBAT5U (0x23A) |
|
| 998 |
#define SPR_BOOKE_MCSRR0 (0x23A) |
|
| 999 |
#define SPR_MPC_DC_DAT (0x23A) |
|
| 1000 |
#define SPR_DBAT5L (0x23B) |
|
| 1001 |
#define SPR_BOOKE_MCSRR1 (0x23B) |
|
| 1002 |
#define SPR_DBAT6U (0x23C) |
|
| 1003 |
#define SPR_BOOKE_MCSR (0x23C) |
|
| 1004 |
#define SPR_DBAT6L (0x23D) |
|
| 1005 |
#define SPR_Exxx_MCAR (0x23D) |
|
| 1006 |
#define SPR_DBAT7U (0x23E) |
|
| 1007 |
#define SPR_BOOKE_DSRR0 (0x23E) |
|
| 1008 |
#define SPR_DBAT7L (0x23F) |
|
| 1009 |
#define SPR_BOOKE_DSRR1 (0x23F) |
|
| 1010 |
#define SPR_BOOKE_SPRG8 (0x25C) |
|
| 1011 |
#define SPR_BOOKE_SPRG9 (0x25D) |
|
| 1012 |
#define SPR_BOOKE_MAS0 (0x270) |
|
| 1013 |
#define SPR_BOOKE_MAS1 (0x271) |
|
| 1014 |
#define SPR_BOOKE_MAS2 (0x272) |
|
| 1015 |
#define SPR_BOOKE_MAS3 (0x273) |
|
| 1016 |
#define SPR_BOOKE_MAS4 (0x274) |
|
| 1017 |
#define SPR_BOOKE_MAS5 (0x275) |
|
| 1018 |
#define SPR_BOOKE_MAS6 (0x276) |
|
| 1019 |
#define SPR_BOOKE_PID1 (0x279) |
|
| 1020 |
#define SPR_BOOKE_PID2 (0x27A) |
|
| 1021 |
#define SPR_MPC_DPDR (0x280) |
|
| 1022 |
#define SPR_MPC_IMMR (0x288) |
|
| 1023 |
#define SPR_BOOKE_TLB0CFG (0x2B0) |
|
| 1024 |
#define SPR_BOOKE_TLB1CFG (0x2B1) |
|
| 1025 |
#define SPR_BOOKE_TLB2CFG (0x2B2) |
|
| 1026 |
#define SPR_BOOKE_TLB3CFG (0x2B3) |
|
| 1027 |
#define SPR_BOOKE_EPR (0x2BE) |
|
| 1028 |
#define SPR_PERF0 (0x300) |
|
| 1029 |
#define SPR_RCPU_MI_RBA0 (0x300) |
|
| 1030 |
#define SPR_MPC_MI_CTR (0x300) |
|
| 1031 |
#define SPR_PERF1 (0x301) |
|
| 1032 |
#define SPR_RCPU_MI_RBA1 (0x301) |
|
| 1033 |
#define SPR_PERF2 (0x302) |
|
| 1034 |
#define SPR_RCPU_MI_RBA2 (0x302) |
|
| 1035 |
#define SPR_MPC_MI_AP (0x302) |
|
| 1036 |
#define SPR_PERF3 (0x303) |
|
| 1037 |
#define SPR_RCPU_MI_RBA3 (0x303) |
|
| 1038 |
#define SPR_MPC_MI_EPN (0x303) |
|
| 1039 |
#define SPR_PERF4 (0x304) |
|
| 1040 |
#define SPR_PERF5 (0x305) |
|
| 1041 |
#define SPR_MPC_MI_TWC (0x305) |
|
| 1042 |
#define SPR_PERF6 (0x306) |
|
| 1043 |
#define SPR_MPC_MI_RPN (0x306) |
|
| 1044 |
#define SPR_PERF7 (0x307) |
|
| 1045 |
#define SPR_PERF8 (0x308) |
|
| 1046 |
#define SPR_RCPU_L2U_RBA0 (0x308) |
|
| 1047 |
#define SPR_MPC_MD_CTR (0x308) |
|
| 1048 |
#define SPR_PERF9 (0x309) |
|
| 1049 |
#define SPR_RCPU_L2U_RBA1 (0x309) |
|
| 1050 |
#define SPR_MPC_MD_CASID (0x309) |
|
| 1051 |
#define SPR_PERFA (0x30A) |
|
| 1052 |
#define SPR_RCPU_L2U_RBA2 (0x30A) |
|
| 1053 |
#define SPR_MPC_MD_AP (0x30A) |
|
| 1054 |
#define SPR_PERFB (0x30B) |
|
| 1055 |
#define SPR_RCPU_L2U_RBA3 (0x30B) |
|
| 1056 |
#define SPR_MPC_MD_EPN (0x30B) |
|
| 1057 |
#define SPR_PERFC (0x30C) |
|
| 1058 |
#define SPR_MPC_MD_TWB (0x30C) |
|
| 1059 |
#define SPR_PERFD (0x30D) |
|
| 1060 |
#define SPR_MPC_MD_TWC (0x30D) |
|
| 1061 |
#define SPR_PERFE (0x30E) |
|
| 1062 |
#define SPR_MPC_MD_RPN (0x30E) |
|
| 1063 |
#define SPR_PERFF (0x30F) |
|
| 1064 |
#define SPR_MPC_MD_TW (0x30F) |
|
| 1065 |
#define SPR_UPERF0 (0x310) |
|
| 1066 |
#define SPR_UPERF1 (0x311) |
|
| 1067 |
#define SPR_UPERF2 (0x312) |
|
| 1068 |
#define SPR_UPERF3 (0x313) |
|
| 1069 |
#define SPR_UPERF4 (0x314) |
|
| 1070 |
#define SPR_UPERF5 (0x315) |
|
| 1071 |
#define SPR_UPERF6 (0x316) |
|
| 1072 |
#define SPR_UPERF7 (0x317) |
|
| 1073 |
#define SPR_UPERF8 (0x318) |
|
| 1074 |
#define SPR_UPERF9 (0x319) |
|
| 1075 |
#define SPR_UPERFA (0x31A) |
|
| 1076 |
#define SPR_UPERFB (0x31B) |
|
| 1077 |
#define SPR_UPERFC (0x31C) |
|
| 1078 |
#define SPR_UPERFD (0x31D) |
|
| 1079 |
#define SPR_UPERFE (0x31E) |
|
| 1080 |
#define SPR_UPERFF (0x31F) |
|
| 1081 |
#define SPR_RCPU_MI_RA0 (0x320) |
|
| 1082 |
#define SPR_MPC_MI_DBCAM (0x320) |
|
| 1083 |
#define SPR_RCPU_MI_RA1 (0x321) |
|
| 1084 |
#define SPR_MPC_MI_DBRAM0 (0x321) |
|
| 1085 |
#define SPR_RCPU_MI_RA2 (0x322) |
|
| 1086 |
#define SPR_MPC_MI_DBRAM1 (0x322) |
|
| 1087 |
#define SPR_RCPU_MI_RA3 (0x323) |
|
| 1088 |
#define SPR_RCPU_L2U_RA0 (0x328) |
|
| 1089 |
#define SPR_MPC_MD_DBCAM (0x328) |
|
| 1090 |
#define SPR_RCPU_L2U_RA1 (0x329) |
|
| 1091 |
#define SPR_MPC_MD_DBRAM0 (0x329) |
|
| 1092 |
#define SPR_RCPU_L2U_RA2 (0x32A) |
|
| 1093 |
#define SPR_MPC_MD_DBRAM1 (0x32A) |
|
| 1094 |
#define SPR_RCPU_L2U_RA3 (0x32B) |
|
| 1095 |
#define SPR_440_INV0 (0x370) |
|
| 1096 |
#define SPR_440_INV1 (0x371) |
|
| 1097 |
#define SPR_440_INV2 (0x372) |
|
| 1098 |
#define SPR_440_INV3 (0x373) |
|
| 1099 |
#define SPR_440_ITV0 (0x374) |
|
| 1100 |
#define SPR_440_ITV1 (0x375) |
|
| 1101 |
#define SPR_440_ITV2 (0x376) |
|
| 1102 |
#define SPR_440_ITV3 (0x377) |
|
| 1103 |
#define SPR_440_CCR1 (0x378) |
|
| 1104 |
#define SPR_DCRIPR (0x37B) |
|
| 1105 |
#define SPR_PPR (0x380) |
|
| 1106 |
#define SPR_440_DNV0 (0x390) |
|
| 1107 |
#define SPR_440_DNV1 (0x391) |
|
| 1108 |
#define SPR_440_DNV2 (0x392) |
|
| 1109 |
#define SPR_440_DNV3 (0x393) |
|
| 1110 |
#define SPR_440_DTV0 (0x394) |
|
| 1111 |
#define SPR_440_DTV1 (0x395) |
|
| 1112 |
#define SPR_440_DTV2 (0x396) |
|
| 1113 |
#define SPR_440_DTV3 (0x397) |
|
| 1114 |
#define SPR_440_DVLIM (0x398) |
|
| 1115 |
#define SPR_440_IVLIM (0x399) |
|
| 1116 |
#define SPR_440_RSTCFG (0x39B) |
|
| 1117 |
#define SPR_BOOKE_DCDBTRL (0x39C) |
|
| 1118 |
#define SPR_BOOKE_DCDBTRH (0x39D) |
|
| 1119 |
#define SPR_BOOKE_ICDBTRL (0x39E) |
|
| 1120 |
#define SPR_BOOKE_ICDBTRH (0x39F) |
|
| 1121 |
#define SPR_UMMCR2 (0x3A0) |
|
| 1122 |
#define SPR_UPMC5 (0x3A1) |
|
| 1123 |
#define SPR_UPMC6 (0x3A2) |
|
| 1124 |
#define SPR_UBAMR (0x3A7) |
|
| 1125 |
#define SPR_UMMCR0 (0x3A8) |
|
| 1126 |
#define SPR_UPMC1 (0x3A9) |
|
| 1127 |
#define SPR_UPMC2 (0x3AA) |
|
| 1128 |
#define SPR_USIAR (0x3AB) |
|
| 1129 |
#define SPR_UMMCR1 (0x3AC) |
|
| 1130 |
#define SPR_UPMC3 (0x3AD) |
|
| 1131 |
#define SPR_UPMC4 (0x3AE) |
|
| 1132 |
#define SPR_USDA (0x3AF) |
|
| 1133 |
#define SPR_40x_ZPR (0x3B0) |
|
| 1134 |
#define SPR_BOOKE_MAS7 (0x3B0) |
|
| 1135 |
#define SPR_620_PMR0 (0x3B0) |
|
| 1136 |
#define SPR_MMCR2 (0x3B0) |
|
| 1137 |
#define SPR_PMC5 (0x3B1) |
|
| 1138 |
#define SPR_40x_PID (0x3B1) |
|
| 1139 |
#define SPR_620_PMR1 (0x3B1) |
|
| 1140 |
#define SPR_PMC6 (0x3B2) |
|
| 1141 |
#define SPR_440_MMUCR (0x3B2) |
|
| 1142 |
#define SPR_620_PMR2 (0x3B2) |
|
| 1143 |
#define SPR_4xx_CCR0 (0x3B3) |
|
| 1144 |
#define SPR_BOOKE_EPLC (0x3B3) |
|
| 1145 |
#define SPR_620_PMR3 (0x3B3) |
|
| 1146 |
#define SPR_405_IAC3 (0x3B4) |
|
| 1147 |
#define SPR_BOOKE_EPSC (0x3B4) |
|
| 1148 |
#define SPR_620_PMR4 (0x3B4) |
|
| 1149 |
#define SPR_405_IAC4 (0x3B5) |
|
| 1150 |
#define SPR_620_PMR5 (0x3B5) |
|
| 1151 |
#define SPR_405_DVC1 (0x3B6) |
|
| 1152 |
#define SPR_620_PMR6 (0x3B6) |
|
| 1153 |
#define SPR_405_DVC2 (0x3B7) |
|
| 1154 |
#define SPR_620_PMR7 (0x3B7) |
|
| 1155 |
#define SPR_BAMR (0x3B7) |
|
| 1156 |
#define SPR_MMCR0 (0x3B8) |
|
| 1157 |
#define SPR_620_PMR8 (0x3B8) |
|
| 1158 |
#define SPR_PMC1 (0x3B9) |
|
| 1159 |
#define SPR_40x_SGR (0x3B9) |
|
| 1160 |
#define SPR_620_PMR9 (0x3B9) |
|
| 1161 |
#define SPR_PMC2 (0x3BA) |
|
| 1162 |
#define SPR_40x_DCWR (0x3BA) |
|
| 1163 |
#define SPR_620_PMRA (0x3BA) |
|
| 1164 |
#define SPR_SIAR (0x3BB) |
|
| 1165 |
#define SPR_405_SLER (0x3BB) |
|
| 1166 |
#define SPR_620_PMRB (0x3BB) |
|
| 1167 |
#define SPR_MMCR1 (0x3BC) |
|
| 1168 |
#define SPR_405_SU0R (0x3BC) |
|
| 1169 |
#define SPR_620_PMRC (0x3BC) |
|
| 1170 |
#define SPR_401_SKR (0x3BC) |
|
| 1171 |
#define SPR_PMC3 (0x3BD) |
|
| 1172 |
#define SPR_405_DBCR1 (0x3BD) |
|
| 1173 |
#define SPR_620_PMRD (0x3BD) |
|
| 1174 |
#define SPR_PMC4 (0x3BE) |
|
| 1175 |
#define SPR_620_PMRE (0x3BE) |
|
| 1176 |
#define SPR_SDA (0x3BF) |
|
| 1177 |
#define SPR_620_PMRF (0x3BF) |
|
| 1178 |
#define SPR_403_VTBL (0x3CC) |
|
| 1179 |
#define SPR_403_VTBU (0x3CD) |
|
| 1180 |
#define SPR_DMISS (0x3D0) |
|
| 1181 |
#define SPR_DCMP (0x3D1) |
|
| 1182 |
#define SPR_HASH1 (0x3D2) |
|
| 1183 |
#define SPR_HASH2 (0x3D3) |
|
| 1184 |
#define SPR_BOOKE_ICDBDR (0x3D3) |
|
| 1185 |
#define SPR_TLBMISS (0x3D4) |
|
| 1186 |
#define SPR_IMISS (0x3D4) |
|
| 1187 |
#define SPR_40x_ESR (0x3D4) |
|
| 1188 |
#define SPR_PTEHI (0x3D5) |
|
| 1189 |
#define SPR_ICMP (0x3D5) |
|
| 1190 |
#define SPR_40x_DEAR (0x3D5) |
|
| 1191 |
#define SPR_PTELO (0x3D6) |
|
| 1192 |
#define SPR_RPA (0x3D6) |
|
| 1193 |
#define SPR_40x_EVPR (0x3D6) |
|
| 1194 |
#define SPR_L3PM (0x3D7) |
|
| 1195 |
#define SPR_403_CDBCR (0x3D7) |
|
| 1196 |
#define SPR_L3OHCR (0x3D8) |
|
| 1197 |
#define SPR_TCR (0x3D8) |
|
| 1198 |
#define SPR_40x_TSR (0x3D8) |
|
| 1199 |
#define SPR_IBR (0x3DA) |
|
| 1200 |
#define SPR_40x_TCR (0x3DA) |
|
| 1201 |
#define SPR_ESASRR (0x3DB) |
|
| 1202 |
#define SPR_40x_PIT (0x3DB) |
|
| 1203 |
#define SPR_403_TBL (0x3DC) |
|
| 1204 |
#define SPR_403_TBU (0x3DD) |
|
| 1205 |
#define SPR_SEBR (0x3DE) |
|
| 1206 |
#define SPR_40x_SRR2 (0x3DE) |
|
| 1207 |
#define SPR_SER (0x3DF) |
|
| 1208 |
#define SPR_40x_SRR3 (0x3DF) |
|
| 1209 |
#define SPR_L3ITCR0 (0x3E8) |
|
| 1210 |
#define SPR_L3ITCR1 (0x3E9) |
|
| 1211 |
#define SPR_L3ITCR2 (0x3EA) |
|
| 1212 |
#define SPR_L3ITCR3 (0x3EB) |
|
| 1213 |
#define SPR_HID0 (0x3F0) |
|
| 1214 |
#define SPR_40x_DBSR (0x3F0) |
|
| 1215 |
#define SPR_HID1 (0x3F1) |
|
| 1216 |
#define SPR_IABR (0x3F2) |
|
| 1217 |
#define SPR_40x_DBCR0 (0x3F2) |
|
| 1218 |
#define SPR_601_HID2 (0x3F2) |
|
| 1219 |
#define SPR_Exxx_L1CSR0 (0x3F2) |
|
| 1220 |
#define SPR_ICTRL (0x3F3) |
|
| 1221 |
#define SPR_HID2 (0x3F3) |
|
| 1222 |
#define SPR_Exxx_L1CSR1 (0x3F3) |
|
| 1223 |
#define SPR_440_DBDR (0x3F3) |
|
| 1224 |
#define SPR_LDSTDB (0x3F4) |
|
| 1225 |
#define SPR_40x_IAC1 (0x3F4) |
|
| 1226 |
#define SPR_MMUCSR0 (0x3F4) |
|
| 1227 |
#define SPR_DABR (0x3F5) |
|
| 1176 | 1228 |
#define DABR_MASK (~(target_ulong)0x7) |
| 1177 |
#define SPR_E500_BUCSR (0x3F5) |
|
| 1178 |
#define SPR_40x_IAC2 (0x3F5) |
|
| 1179 |
#define SPR_601_HID5 (0x3F5) |
|
| 1180 |
#define SPR_40x_DAC1 (0x3F6) |
|
| 1181 |
#define SPR_MSSCR0 (0x3F6) |
|
| 1182 |
#define SPR_970_HID5 (0x3F6) |
|
| 1183 |
#define SPR_MSSSR0 (0x3F7) |
|
| 1184 |
#define SPR_DABRX (0x3F7) |
|
| 1185 |
#define SPR_40x_DAC2 (0x3F7) |
|
| 1186 |
#define SPR_MMUCFG (0x3F7) |
|
| 1187 |
#define SPR_LDSTCR (0x3F8) |
|
| 1188 |
#define SPR_L2PMCR (0x3F8) |
|
| 1189 |
#define SPR_750_HID2 (0x3F8) |
|
| 1190 |
#define SPR_620_HID8 (0x3F8) |
|
| 1191 |
#define SPR_L2CR (0x3F9) |
|
| 1192 |
#define SPR_620_HID9 (0x3F9) |
|
| 1193 |
#define SPR_L3CR (0x3FA) |
|
| 1194 |
#define SPR_IABR2 (0x3FA) |
|
| 1195 |
#define SPR_40x_DCCR (0x3FA) |
|
| 1196 |
#define SPR_ICTC (0x3FB) |
|
| 1197 |
#define SPR_40x_ICCR (0x3FB) |
|
| 1198 |
#define SPR_THRM1 (0x3FC) |
|
| 1199 |
#define SPR_403_PBL1 (0x3FC) |
|
| 1200 |
#define SPR_SP (0x3FD) |
|
| 1201 |
#define SPR_THRM2 (0x3FD) |
|
| 1202 |
#define SPR_403_PBU1 (0x3FD) |
|
| 1203 |
#define SPR_604_HID13 (0x3FD) |
|
| 1204 |
#define SPR_LT (0x3FE) |
|
| 1205 |
#define SPR_THRM3 (0x3FE) |
|
| 1206 |
#define SPR_FPECR (0x3FE) |
|
| 1207 |
#define SPR_403_PBL2 (0x3FE) |
|
| 1208 |
#define SPR_PIR (0x3FF) |
|
| 1209 |
#define SPR_403_PBU2 (0x3FF) |
|
| 1210 |
#define SPR_601_HID15 (0x3FF) |
|
| 1211 |
#define SPR_604_HID15 (0x3FF) |
|
| 1212 |
#define SPR_E500_SVR (0x3FF) |
|
| 1229 |
#define SPR_Exxx_BUCSR (0x3F5) |
|
| 1230 |
#define SPR_40x_IAC2 (0x3F5) |
|
| 1231 |
#define SPR_601_HID5 (0x3F5) |
|
| 1232 |
#define SPR_40x_DAC1 (0x3F6) |
|
| 1233 |
#define SPR_MSSCR0 (0x3F6) |
|
| 1234 |
#define SPR_970_HID5 (0x3F6) |
|
| 1235 |
#define SPR_MSSSR0 (0x3F7) |
|
| 1236 |
#define SPR_DABRX (0x3F7) |
|
| 1237 |
#define SPR_40x_DAC2 (0x3F7) |
|
| 1238 |
#define SPR_MMUCFG (0x3F7) |
|
| 1239 |
#define SPR_LDSTCR (0x3F8) |
|
| 1240 |
#define SPR_L2PMCR (0x3F8) |
|
| 1241 |
#define SPR_750_HID2 (0x3F8) |
|
| 1242 |
#define SPR_620_HID8 (0x3F8) |
|
| 1243 |
#define SPR_Exxx_L1FINV0 (0x3F8) |
|
| 1244 |
#define SPR_L2CR (0x3F9) |
|
| 1245 |
#define SPR_620_HID9 (0x3F9) |
|
| 1246 |
#define SPR_L3CR (0x3FA) |
|
| 1247 |
#define SPR_IABR2 (0x3FA) |
|
| 1248 |
#define SPR_40x_DCCR (0x3FA) |
|
| 1249 |
#define SPR_ICTC (0x3FB) |
|
| 1250 |
#define SPR_40x_ICCR (0x3FB) |
|
| 1251 |
#define SPR_THRM1 (0x3FC) |
|
| 1252 |
#define SPR_403_PBL1 (0x3FC) |
|
| 1253 |
#define SPR_SP (0x3FD) |
|
| 1254 |
#define SPR_THRM2 (0x3FD) |
|
| 1255 |
#define SPR_403_PBU1 (0x3FD) |
|
| 1256 |
#define SPR_604_HID13 (0x3FD) |
|
| 1257 |
#define SPR_LT (0x3FE) |
|
| 1258 |
#define SPR_THRM3 (0x3FE) |
|
| 1259 |
#define SPR_RCPU_FPECR (0x3FE) |
|
| 1260 |
#define SPR_403_PBL2 (0x3FE) |
|
| 1261 |
#define SPR_PIR (0x3FF) |
|
| 1262 |
#define SPR_403_PBU2 (0x3FF) |
|
| 1263 |
#define SPR_601_HID15 (0x3FF) |
|
| 1264 |
#define SPR_604_HID15 (0x3FF) |
|
| 1265 |
#define SPR_E500_SVR (0x3FF) |
|
| 1213 | 1266 |
|
| 1214 | 1267 |
/*****************************************************************************/ |
| 1215 | 1268 |
/* Memory access type : |
| b/target-ppc/translate_init.c | ||
|---|---|---|
| 28 | 28 |
|
| 29 | 29 |
//#define PPC_DUMP_CPU |
| 30 | 30 |
//#define PPC_DEBUG_SPR |
| 31 |
//#define PPC_DEBUG_IRQ |
|
| 31 |
//#define PPC_DUMP_SPR_ACCESSES |
|
| 32 |
#if defined(CONFIG_USER_ONLY) |
|
| 33 |
#define TODO_USER_ONLY 1 |
|
| 34 |
#endif |
|
| 32 | 35 |
|
| 33 | 36 |
struct ppc_def_t {
|
| 34 | 37 |
const unsigned char *name; |
| 35 | 38 |
uint32_t pvr; |
| 39 |
uint32_t svr; |
|
| 36 | 40 |
uint64_t insns_flags; |
| 37 | 41 |
uint64_t msr_mask; |
| 38 | 42 |
powerpc_mmu_t mmu_model; |
| ... | ... | |
| 983 | 987 |
SPR_NOACCESS, SPR_NOACCESS, |
| 984 | 988 |
&spr_read_generic, &spr_write_generic, |
| 985 | 989 |
0x00000000); |
| 986 |
/* System version register */ |
|
| 987 |
/* SVR */ |
|
| 988 |
/* XXX : TODO: initialize it to an appropriate value */ |
|
| 989 |
spr_register(env, SPR_SVR, "SVR", |
|
| 990 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 991 |
&spr_read_generic, SPR_NOACCESS, |
|
| 992 |
0x00000000); |
|
| 993 | 990 |
/* Exception processing */ |
| 994 | 991 |
spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", |
| 995 | 992 |
SPR_NOACCESS, SPR_NOACCESS, |
| ... | ... | |
| 1277 | 1274 |
#endif |
| 1278 | 1275 |
} |
| 1279 | 1276 |
|
| 1280 |
/* PowerPC BookE SPR */ |
|
| 1281 |
static void gen_spr_BookE (CPUPPCState *env) |
|
| 1277 |
static void gen_spr_usprgh (CPUPPCState *env) |
|
| 1282 | 1278 |
{
|
| 1283 |
/* Processor identification */ |
|
| 1284 |
spr_register(env, SPR_BOOKE_PIR, "PIR", |
|
| 1285 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1286 |
&spr_read_generic, &spr_write_pir, |
|
| 1279 |
spr_register(env, SPR_USPRG4, "USPRG4", |
|
| 1280 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1281 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1282 |
0x00000000); |
|
| 1283 |
spr_register(env, SPR_USPRG5, "USPRG5", |
|
| 1284 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1285 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1286 |
0x00000000); |
|
| 1287 |
spr_register(env, SPR_USPRG6, "USPRG6", |
|
| 1288 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1289 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1290 |
0x00000000); |
|
| 1291 |
spr_register(env, SPR_USPRG7, "USPRG7", |
|
| 1292 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1293 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1287 | 1294 |
0x00000000); |
| 1295 |
} |
|
| 1296 |
|
|
| 1297 |
/* PowerPC BookE SPR */ |
|
| 1298 |
static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask) |
|
| 1299 |
{
|
|
| 1300 |
const unsigned char *ivor_names[64] = {
|
|
| 1301 |
"IVOR0", "IVOR1", "IVOR2", "IVOR3", |
|
| 1302 |
"IVOR4", "IVOR5", "IVOR6", "IVOR7", |
|
| 1303 |
"IVOR8", "IVOR9", "IVOR10", "IVOR11", |
|
| 1304 |
"IVOR12", "IVOR13", "IVOR14", "IVOR15", |
|
| 1305 |
"IVOR16", "IVOR17", "IVOR18", "IVOR19", |
|
| 1306 |
"IVOR20", "IVOR21", "IVOR22", "IVOR23", |
|
| 1307 |
"IVOR24", "IVOR25", "IVOR26", "IVOR27", |
|
| 1308 |
"IVOR28", "IVOR29", "IVOR30", "IVOR31", |
|
| 1309 |
"IVOR32", "IVOR33", "IVOR34", "IVOR35", |
|
| 1310 |
"IVOR36", "IVOR37", "IVOR38", "IVOR39", |
|
| 1311 |
"IVOR40", "IVOR41", "IVOR42", "IVOR43", |
|
| 1312 |
"IVOR44", "IVOR45", "IVOR46", "IVOR47", |
|
| 1313 |
"IVOR48", "IVOR49", "IVOR50", "IVOR51", |
|
| 1314 |
"IVOR52", "IVOR53", "IVOR54", "IVOR55", |
|
| 1315 |
"IVOR56", "IVOR57", "IVOR58", "IVOR59", |
|
| 1316 |
"IVOR60", "IVOR61", "IVOR62", "IVOR63", |
|
| 1317 |
}; |
|
| 1318 |
#define SPR_BOOKE_IVORxx (-1) |
|
| 1319 |
int ivor_sprn[64] = {
|
|
| 1320 |
SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, |
|
| 1321 |
SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, |
|
| 1322 |
SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, |
|
| 1323 |
SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, |
|
| 1324 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1325 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1326 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1327 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1328 |
SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, |
|
| 1329 |
SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1330 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1331 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1332 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1333 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1334 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1335 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1336 |
}; |
|
| 1337 |
int i; |
|
| 1338 |
|
|
| 1288 | 1339 |
/* Interrupt processing */ |
| 1289 | 1340 |
spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", |
| 1290 | 1341 |
SPR_NOACCESS, SPR_NOACCESS, |
| ... | ... | |
| 1294 | 1345 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1295 | 1346 |
&spr_read_generic, &spr_write_generic, |
| 1296 | 1347 |
0x00000000); |
| 1297 |
#if 0 |
|
| 1298 |
spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", |
|
| 1299 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1300 |
&spr_read_generic, &spr_write_generic, |
|
| 1301 |
0x00000000); |
|
| 1302 |
spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", |
|
| 1303 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1304 |
&spr_read_generic, &spr_write_generic, |
|
| 1305 |
0x00000000); |
|
| 1306 |
#endif |
|
| 1307 | 1348 |
/* Debug */ |
| 1308 | 1349 |
/* XXX : not implemented */ |
| 1309 | 1350 |
spr_register(env, SPR_BOOKE_IAC1, "IAC1", |
| ... | ... | |
| 1316 | 1357 |
&spr_read_generic, &spr_write_generic, |
| 1317 | 1358 |
0x00000000); |
| 1318 | 1359 |
/* XXX : not implemented */ |
| 1319 |
spr_register(env, SPR_BOOKE_IAC3, "IAC3", |
|
| 1320 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1321 |
&spr_read_generic, &spr_write_generic, |
|
| 1322 |
0x00000000); |
|
| 1323 |
/* XXX : not implemented */ |
|
| 1324 |
spr_register(env, SPR_BOOKE_IAC4, "IAC4", |
|
| 1325 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1326 |
&spr_read_generic, &spr_write_generic, |
|
| 1327 |
0x00000000); |
|
| 1328 |
/* XXX : not implemented */ |
|
| 1329 | 1360 |
spr_register(env, SPR_BOOKE_DAC1, "DAC1", |
| 1330 | 1361 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1331 | 1362 |
&spr_read_generic, &spr_write_generic, |
| ... | ... | |
| 1336 | 1367 |
&spr_read_generic, &spr_write_generic, |
| 1337 | 1368 |
0x00000000); |
| 1338 | 1369 |
/* XXX : not implemented */ |
| 1339 |
spr_register(env, SPR_BOOKE_DVC1, "DVC1", |
|
| 1340 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1341 |
&spr_read_generic, &spr_write_generic, |
|
| 1342 |
0x00000000); |
|
| 1343 |
/* XXX : not implemented */ |
|
| 1344 |
spr_register(env, SPR_BOOKE_DVC2, "DVC2", |
|
| 1345 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1346 |
&spr_read_generic, &spr_write_generic, |
|
| 1347 |
0x00000000); |
|
| 1348 |
/* XXX : not implemented */ |
|
| 1349 | 1370 |
spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", |
| 1350 | 1371 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1351 | 1372 |
&spr_read_generic, &spr_write_generic, |
| ... | ... | |
| 1378 | 1399 |
&spr_read_generic, &spr_write_excp_prefix, |
| 1379 | 1400 |
0x00000000); |
| 1380 | 1401 |
/* Exception vectors */ |
| 1381 |
spr_register(env, SPR_BOOKE_IVOR0, "IVOR0", |
|
| 1382 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1383 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1384 |
0x00000000); |
|
| 1385 |
spr_register(env, SPR_BOOKE_IVOR1, "IVOR1", |
|
| 1386 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1387 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1388 |
0x00000000); |
|
| 1389 |
spr_register(env, SPR_BOOKE_IVOR2, "IVOR2", |
|
| 1390 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1391 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1392 |
0x00000000); |
|
| 1393 |
spr_register(env, SPR_BOOKE_IVOR3, "IVOR3", |
|
| 1394 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1395 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1396 |
0x00000000); |
|
| 1397 |
spr_register(env, SPR_BOOKE_IVOR4, "IVOR4", |
|
| 1398 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1399 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1400 |
0x00000000); |
|
| 1401 |
spr_register(env, SPR_BOOKE_IVOR5, "IVOR5", |
|
| 1402 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1403 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1404 |
0x00000000); |
|
| 1405 |
spr_register(env, SPR_BOOKE_IVOR6, "IVOR6", |
|
| 1406 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1407 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1408 |
0x00000000); |
|
| 1409 |
spr_register(env, SPR_BOOKE_IVOR7, "IVOR7", |
|
| 1410 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1411 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1412 |
0x00000000); |
|
| 1413 |
spr_register(env, SPR_BOOKE_IVOR8, "IVOR8", |
|
| 1414 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1415 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1416 |
0x00000000); |
|
| 1417 |
spr_register(env, SPR_BOOKE_IVOR9, "IVOR9", |
|
| 1418 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1419 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1420 |
0x00000000); |
|
| 1421 |
spr_register(env, SPR_BOOKE_IVOR10, "IVOR10", |
|
| 1422 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1423 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1424 |
0x00000000); |
|
| 1425 |
spr_register(env, SPR_BOOKE_IVOR11, "IVOR11", |
|
| 1426 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1427 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1428 |
0x00000000); |
|
| 1429 |
spr_register(env, SPR_BOOKE_IVOR12, "IVOR12", |
|
| 1430 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1431 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1432 |
0x00000000); |
|
| 1433 |
spr_register(env, SPR_BOOKE_IVOR13, "IVOR13", |
|
| 1434 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1435 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1436 |
0x00000000); |
|
| 1437 |
spr_register(env, SPR_BOOKE_IVOR14, "IVOR14", |
|
| 1438 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1439 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1440 |
0x00000000); |
|
| 1441 |
spr_register(env, SPR_BOOKE_IVOR15, "IVOR15", |
|
| 1442 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1443 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1444 |
0x00000000); |
|
| 1445 |
#if 0 |
|
| 1446 |
spr_register(env, SPR_BOOKE_IVOR32, "IVOR32", |
|
| 1447 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1448 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1449 |
0x00000000); |
|
| 1450 |
spr_register(env, SPR_BOOKE_IVOR33, "IVOR33", |
|
| 1451 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1452 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1453 |
0x00000000); |
|
| 1454 |
spr_register(env, SPR_BOOKE_IVOR34, "IVOR34", |
|
| 1455 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1456 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1457 |
0x00000000); |
|
| 1458 |
spr_register(env, SPR_BOOKE_IVOR35, "IVOR35", |
|
| 1459 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1460 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1461 |
0x00000000); |
|
| 1462 |
spr_register(env, SPR_BOOKE_IVOR36, "IVOR36", |
|
| 1463 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1464 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1465 |
0x00000000); |
|
| 1466 |
spr_register(env, SPR_BOOKE_IVOR37, "IVOR37", |
|
| 1467 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1468 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1469 |
0x00000000); |
|
| 1470 |
#endif |
|
| 1402 |
for (i = 0; i < 64; i++) {
|
|
| 1403 |
if (ivor_mask & (1ULL << i)) {
|
|
| 1404 |
if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
|
|
| 1405 |
fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); |
|
| 1406 |
exit(1); |
|
| 1407 |
} |
|
| 1408 |
spr_register(env, ivor_sprn[i], ivor_names[i], |
|
| 1409 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1410 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1411 |
0x00000000); |
|
| 1412 |
} |
|
| 1413 |
} |
|
| 1471 | 1414 |
spr_register(env, SPR_BOOKE_PID, "PID", |
| 1472 | 1415 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1473 | 1416 |
&spr_read_generic, &spr_write_generic, |
| ... | ... | |
| 1498 | 1441 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1499 | 1442 |
&spr_read_generic, &spr_write_generic, |
| 1500 | 1443 |
0x00000000); |
| 1501 |
spr_register(env, SPR_USPRG4, "USPRG4", |
|
| 1502 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1503 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1504 |
0x00000000); |
|
| 1505 | 1444 |
spr_register(env, SPR_SPRG5, "SPRG5", |
| 1506 | 1445 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1507 | 1446 |
&spr_read_generic, &spr_write_generic, |
| 1508 | 1447 |
0x00000000); |
| 1509 |
spr_register(env, SPR_USPRG5, "USPRG5", |
|
| 1510 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1511 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1512 |
0x00000000); |
|
| 1513 | 1448 |
spr_register(env, SPR_SPRG6, "SPRG6", |
| 1514 | 1449 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1515 | 1450 |
&spr_read_generic, &spr_write_generic, |
| 1516 | 1451 |
0x00000000); |
| 1517 |
spr_register(env, SPR_USPRG6, "USPRG6", |
|
| 1518 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1519 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1520 |
0x00000000); |
|
| 1521 | 1452 |
spr_register(env, SPR_SPRG7, "SPRG7", |
| 1522 | 1453 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1523 | 1454 |
&spr_read_generic, &spr_write_generic, |
| 1524 | 1455 |
0x00000000); |
| 1525 |
spr_register(env, SPR_USPRG7, "USPRG7", |
|
| 1526 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1527 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1528 |
0x00000000); |
|
| 1529 | 1456 |
} |
| 1530 | 1457 |
|
| 1531 | 1458 |
/* FSL storage control registers */ |
| 1532 |
static void gen_spr_BookE_FSL (CPUPPCState *env) |
|
| 1459 |
static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
|
|
| 1533 | 1460 |
{
|
| 1534 | 1461 |
#if !defined(CONFIG_USER_ONLY) |
| 1462 |
const unsigned char *mas_names[8] = {
|
|
| 1463 |
"MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", |
|
| 1464 |
}; |
|
| 1465 |
int mas_sprn[8] = {
|
|
| 1466 |
SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, |
|
| 1467 |
SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, |
|
| 1468 |
}; |
|
| 1469 |
int i; |
|
| 1470 |
|
|
| 1535 | 1471 |
/* TLB assist registers */ |
| 1536 | 1472 |
/* XXX : not implemented */ |
| 1537 |
spr_register(env, SPR_BOOKE_MAS0, "MAS0", |
|
| 1538 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1539 |
&spr_read_generic, &spr_write_generic, |
|
| 1540 |
0x00000000); |
|
| 1541 |
/* XXX : not implemented */ |
|
| 1542 |
spr_register(env, SPR_BOOKE_MAS1, "MAS2", |
|
| 1543 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1544 |
&spr_read_generic, &spr_write_generic, |
|
| 1545 |
0x00000000); |
|
| 1546 |
/* XXX : not implemented */ |
|
| 1547 |
spr_register(env, SPR_BOOKE_MAS2, "MAS3", |
|
| 1548 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1549 |
&spr_read_generic, &spr_write_generic, |
|
| 1550 |
0x00000000); |
|
| 1551 |
/* XXX : not implemented */ |
|
| 1552 |
spr_register(env, SPR_BOOKE_MAS3, "MAS4", |
|
| 1553 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1554 |
&spr_read_generic, &spr_write_generic, |
|
| 1555 |
0x00000000); |
|
| 1556 |
/* XXX : not implemented */ |
|
| 1557 |
spr_register(env, SPR_BOOKE_MAS4, "MAS5", |
|
| 1558 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1559 |
&spr_read_generic, &spr_write_generic, |
|
| 1560 |
0x00000000); |
|
| 1561 |
/* XXX : not implemented */ |
|
| 1562 |
spr_register(env, SPR_BOOKE_MAS6, "MAS6", |
|
| 1563 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1564 |
&spr_read_generic, &spr_write_generic, |
|
| 1565 |
0x00000000); |
|
| 1566 |
/* XXX : not implemented */ |
|
| 1567 |
spr_register(env, SPR_BOOKE_MAS7, "MAS7", |
|
| 1568 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1569 |
&spr_read_generic, &spr_write_generic, |
|
| 1570 |
0x00000000); |
|
| 1473 |
for (i = 0; i < 8; i++) {
|
|
| 1474 |
if (mas_mask & (1 << i)) {
|
|
| 1475 |
spr_register(env, mas_sprn[i], mas_names[i], |
|
| 1476 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1477 |
&spr_read_generic, &spr_write_generic, |
|
| 1478 |
0x00000000); |
|
| 1479 |
} |
|
| 1480 |
} |
|
| 1571 | 1481 |
if (env->nb_pids > 1) {
|
| 1572 | 1482 |
/* XXX : not implemented */ |
| 1573 | 1483 |
spr_register(env, SPR_BOOKE_PID1, "PID1", |
| ... | ... | |
| 1915 | 1825 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1916 | 1826 |
&spr_read_generic, &spr_write_generic, |
| 1917 | 1827 |
0x00000000); |
| 1918 |
spr_register(env, SPR_USPRG4, "USPRG4", |
|
| 1919 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1920 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1921 |
0x00000000); |
|
| 1922 | 1828 |
spr_register(env, SPR_SPRG5, "SPRG5", |
| 1923 | 1829 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1924 | 1830 |
spr_read_generic, &spr_write_generic, |
| 1925 | 1831 |
0x00000000); |
| 1926 |
spr_register(env, SPR_USPRG5, "USPRG5", |
|
| 1927 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1928 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1929 |
0x00000000); |
|
| 1930 | 1832 |
spr_register(env, SPR_SPRG6, "SPRG6", |
| 1931 | 1833 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1932 | 1834 |
spr_read_generic, &spr_write_generic, |
| 1933 | 1835 |
0x00000000); |
| 1934 |
spr_register(env, SPR_USPRG6, "USPRG6", |
|
| 1935 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1936 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1937 |
0x00000000); |
|
| 1938 | 1836 |
spr_register(env, SPR_SPRG7, "SPRG7", |
| 1939 | 1837 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1940 | 1838 |
spr_read_generic, &spr_write_generic, |
| 1941 | 1839 |
0x00000000); |
| 1942 |
spr_register(env, SPR_USPRG7, "USPRG7", |
|
| 1943 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1944 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1945 |
0x00000000); |
|
| 1840 |
gen_spr_usprgh(env); |
|
| 1946 | 1841 |
} |
| 1947 | 1842 |
|
| 1948 | 1843 |
/* SPR shared between PowerPC 401 & 403 implementations */ |
| ... | ... | |
| 2206 | 2101 |
} |
| 2207 | 2102 |
#endif /* defined (TARGET_PPC64) */ |
| 2208 | 2103 |
|
| 2209 |
// XXX: TODO |
|
| 2210 |
/* |
|
| 2211 |
* AMR => SPR 29 (Power 2.04) |
|
| 2212 |
* CTRL => SPR 136 (Power 2.04) |
|
| 2213 |
* CTRL => SPR 152 (Power 2.04) |
|
| 2214 |
* SCOMC => SPR 276 (64 bits ?) |
|
| 2215 |
* SCOMD => SPR 277 (64 bits ?) |
|
| 2216 |
* TBU40 => SPR 286 (Power 2.04 hypv) |
|
| 2217 |
* HSPRG0 => SPR 304 (Power 2.04 hypv) |
|
| 2218 |
* HSPRG1 => SPR 305 (Power 2.04 hypv) |
|
| 2219 |
* HDSISR => SPR 306 (Power 2.04 hypv) |
|
| 2220 |
* HDAR => SPR 307 (Power 2.04 hypv) |
|
| 2221 |
* PURR => SPR 309 (Power 2.04 hypv) |
|
| 2222 |
* HDEC => SPR 310 (Power 2.04 hypv) |
|
| 2223 |
* HIOR => SPR 311 (hypv) |
|
| 2224 |
* RMOR => SPR 312 (970) |
|
| 2225 |
* HRMOR => SPR 313 (Power 2.04 hypv) |
|
| 2226 |
* HSRR0 => SPR 314 (Power 2.04 hypv) |
|
| 2227 |
* HSRR1 => SPR 315 (Power 2.04 hypv) |
|
| 2228 |
* LPCR => SPR 316 (970) |
|
| 2229 |
* LPIDR => SPR 317 (970) |
|
| 2230 |
* SPEFSCR => SPR 512 (Power 2.04 emb) |
|
| 2231 |
* EPR => SPR 702 (Power 2.04 emb) |
|
| 2232 |
* perf => 768-783 (Power 2.04) |
|
| 2233 |
* perf => 784-799 (Power 2.04) |
|
| 2234 |
* PPR => SPR 896 (Power 2.04) |
|
| 2235 |
* EPLC => SPR 947 (Power 2.04 emb) |
|
| 2236 |
* EPSC => SPR 948 (Power 2.04 emb) |
|
| 2237 |
* DABRX => 1015 (Power 2.04 hypv) |
|
| 2238 |
* FPECR => SPR 1022 (?) |
|
| 2239 |
* ... and more (thermal management, performance counters, ...) |
|
| 2240 |
*/ |
|
| 2241 |
|
|
| 2242 |
/*****************************************************************************/ |
|
| 2243 |
/* Exception vectors models */ |
|
| 2244 |
static void init_excp_4xx_real (CPUPPCState *env) |
|
| 2245 |
{
|
|
| 2246 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2247 |
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; |
|
| 2248 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
|
| 2249 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
|
| 2250 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
|
| 2251 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
|
| 2252 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
|
| 2253 |
env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; |
|
| 2254 |
env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; |
|
| 2255 |
env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; |
|
| 2256 |
env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; |
|
| 2257 |
env->excp_prefix = 0x00000000UL; |
|
| 2258 |
env->ivor_mask = 0x0000FFF0UL; |
|
| 2259 |
env->ivpr_mask = 0xFFFF0000UL; |
|
| 2260 |
/* Hardware reset vector */ |
|
| 2261 |
env->hreset_vector = 0xFFFFFFFCUL; |
|
| 2262 |
#endif |
|
| 2263 |
} |
|
| 2264 |
|
|
| 2265 |
static void init_excp_4xx_softmmu (CPUPPCState *env) |
|
| 2266 |
{
|
|
| 2267 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2268 |
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; |
|
| 2269 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
|
| 2270 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
|
| 2271 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
|
| 2272 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
|
| 2273 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
|
| 2274 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
|
| 2275 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
|
| 2276 |
env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; |
|
| 2277 |
env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; |
|
| 2278 |
env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; |
|
| 2279 |
env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; |
|
| 2280 |
env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; |
|
| 2281 |
env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; |
|
| 2282 |
env->excp_prefix = 0x00000000UL; |
|
| 2283 |
env->ivor_mask = 0x0000FFF0UL; |
|
| 2284 |
env->ivpr_mask = 0xFFFF0000UL; |
|
| 2285 |
/* Hardware reset vector */ |
|
| 2286 |
env->hreset_vector = 0xFFFFFFFCUL; |
|
| 2287 |
#endif |
|
| 2288 |
} |
|
| 2289 |
|
|
| 2290 |
static void init_excp_BookE (CPUPPCState *env) |
|
| 2104 |
static void gen_spr_5xx_8xx (CPUPPCState *env) |
|
| 2291 | 2105 |
{
|
| 2292 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2293 |
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; |
|
| 2106 |
/* Exception processing */ |
|
| 2107 |
spr_register(env, SPR_DSISR, "DSISR", |
|
| 2108 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2109 |
&spr_read_generic, &spr_write_generic, |
|
| 2110 |
0x00000000); |
|
| 2111 |
spr_register(env, SPR_DAR, "DAR", |
|
| 2112 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2113 |
&spr_read_generic, &spr_write_generic, |
|
| 2114 |
0x00000000); |
|
| 2115 |
/* Timer */ |
|
| 2116 |
spr_register(env, SPR_DECR, "DECR", |
|
| 2117 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2118 |
&spr_read_decr, &spr_write_decr, |
|
| 2119 |
0x00000000); |
|
| 2120 |
/* XXX : not implemented */ |
|
| 2121 |
spr_register(env, SPR_MPC_EIE, "EIE", |
|
| 2122 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2123 |
&spr_read_generic, &spr_write_generic, |
|
| 2124 |
0x00000000); |
|
| 2125 |
/* XXX : not implemented */ |
|
| 2126 |
spr_register(env, SPR_MPC_EID, "EID", |
|
| 2127 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2128 |
&spr_read_generic, &spr_write_generic, |
|
| 2129 |
0x00000000); |
|
| 2130 |
/* XXX : not implemented */ |
|
| 2131 |
spr_register(env, SPR_MPC_NRI, "NRI", |
|
| 2132 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2133 |
&spr_read_generic, &spr_write_generic, |
|
| 2134 |
0x00000000); |
|
| 2135 |
/* XXX : not implemented */ |
|
| 2136 |
spr_register(env, SPR_MPC_CMPA, "CMPA", |
|
| 2137 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2138 |
&spr_read_generic, &spr_write_generic, |
|
| 2139 |
0x00000000); |
|
| 2140 |
/* XXX : not implemented */ |
|
| 2141 |
spr_register(env, SPR_MPC_CMPB, "CMPB", |
|
| 2142 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2143 |
&spr_read_generic, &spr_write_generic, |
|
| 2144 |
0x00000000); |
|
| 2145 |
/* XXX : not implemented */ |
|
| 2146 |
spr_register(env, SPR_MPC_CMPC, "CMPC", |
|
| 2147 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2148 |
&spr_read_generic, &spr_write_generic, |
|
| 2149 |
0x00000000); |
|
| 2150 |
/* XXX : not implemented */ |
|
| 2151 |
spr_register(env, SPR_MPC_CMPD, "CMPD", |
|
| 2152 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2153 |
&spr_read_generic, &spr_write_generic, |
|
| 2154 |
0x00000000); |
|
| 2155 |
/* XXX : not implemented */ |
|
| 2156 |
spr_register(env, SPR_MPC_ECR, "ECR", |
|
| 2157 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2158 |
&spr_read_generic, &spr_write_generic, |
|
| 2159 |
0x00000000); |
|
| 2160 |
/* XXX : not implemented */ |
|
| 2161 |
spr_register(env, SPR_MPC_DER, "DER", |
|
| 2162 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2163 |
&spr_read_generic, &spr_write_generic, |
|
| 2164 |
0x00000000); |
|
| 2165 |
/* XXX : not implemented */ |
|
| 2166 |
spr_register(env, SPR_MPC_COUNTA, "COUNTA", |
|
| 2167 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2168 |
&spr_read_generic, &spr_write_generic, |
|
| 2169 |
0x00000000); |
|
| 2170 |
/* XXX : not implemented */ |
|
| 2171 |
spr_register(env, SPR_MPC_COUNTB, "COUNTB", |
|
| 2172 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2173 |
&spr_read_generic, &spr_write_generic, |
|
| 2174 |
0x00000000); |
|
| 2175 |
/* XXX : not implemented */ |
|
| 2176 |
spr_register(env, SPR_MPC_CMPE, "CMPE", |
|
| 2177 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2178 |
&spr_read_generic, &spr_write_generic, |
|
| 2179 |
0x00000000); |
|
| 2180 |
/* XXX : not implemented */ |
|
| 2181 |
spr_register(env, SPR_MPC_CMPF, "CMPF", |
|
| 2182 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2183 |
&spr_read_generic, &spr_write_generic, |
|
| 2184 |
0x00000000); |
|
| 2185 |
/* XXX : not implemented */ |
|
| 2186 |
spr_register(env, SPR_MPC_CMPG, "CMPG", |
|
| 2187 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2188 |
&spr_read_generic, &spr_write_generic, |
|
| 2189 |
0x00000000); |
|
| 2190 |
/* XXX : not implemented */ |
|
| 2191 |
spr_register(env, SPR_MPC_CMPH, "CMPH", |
|
| 2192 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2193 |
&spr_read_generic, &spr_write_generic, |
|
| 2194 |
0x00000000); |
|
| 2195 |
/* XXX : not implemented */ |
|
| 2196 |
spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", |
|
| 2197 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2198 |
&spr_read_generic, &spr_write_generic, |
|
| 2199 |
0x00000000); |
|
| 2200 |
/* XXX : not implemented */ |
|
| 2201 |
spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", |
|
| 2202 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2203 |
&spr_read_generic, &spr_write_generic, |
|
| 2204 |
0x00000000); |
|
| 2205 |
/* XXX : not implemented */ |
|
| 2206 |
spr_register(env, SPR_MPC_BAR, "BAR", |
|
| 2207 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2208 |
&spr_read_generic, &spr_write_generic, |
|
| 2209 |
0x00000000); |
|
| 2210 |
/* XXX : not implemented */ |
|
| 2211 |
spr_register(env, SPR_MPC_DPDR, "DPDR", |
|
| 2212 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2213 |
&spr_read_generic, &spr_write_generic, |
|
| 2214 |
0x00000000); |
|
| 2215 |
/* XXX : not implemented */ |
|
| 2216 |
spr_register(env, SPR_MPC_IMMR, "IMMR", |
|
| 2217 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2218 |
&spr_read_generic, &spr_write_generic, |
|
| 2219 |
0x00000000); |
|
| 2220 |
} |
|
| 2221 |
|
|
| 2222 |
static void gen_spr_5xx (CPUPPCState *env) |
|
| 2223 |
{
|
|
| 2224 |
/* XXX : not implemented */ |
|
| 2225 |
spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", |
|
| 2226 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2227 |
&spr_read_generic, &spr_write_generic, |
|
| 2228 |
0x00000000); |
|
| 2229 |
/* XXX : not implemented */ |
|
| 2230 |
spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", |
|
| 2231 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2232 |
&spr_read_generic, &spr_write_generic, |
|
| 2233 |
0x00000000); |
|
| 2234 |
/* XXX : not implemented */ |
|
| 2235 |
spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", |
|
| 2236 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2237 |
&spr_read_generic, &spr_write_generic, |
|
| 2238 |
0x00000000); |
|
| 2239 |
/* XXX : not implemented */ |
|
| 2240 |
spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", |
|
| 2241 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2242 |
&spr_read_generic, &spr_write_generic, |
|
| 2243 |
0x00000000); |
|
| 2244 |
/* XXX : not implemented */ |
|
| 2245 |
spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", |
|
| 2246 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2247 |
&spr_read_generic, &spr_write_generic, |
|
| 2248 |
0x00000000); |
|
| 2249 |
/* XXX : not implemented */ |
|
| 2250 |
spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", |
|
| 2251 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2252 |
&spr_read_generic, &spr_write_generic, |
|
| 2253 |
0x00000000); |
|
| 2254 |
/* XXX : not implemented */ |
|
| 2255 |
spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", |
|
| 2256 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2257 |
&spr_read_generic, &spr_write_generic, |
|
| 2258 |
0x00000000); |
|
| 2259 |
/* XXX : not implemented */ |
|
| 2260 |
spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", |
|
| 2261 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2262 |
&spr_read_generic, &spr_write_generic, |
|
| 2263 |
0x00000000); |
|
| 2264 |
/* XXX : not implemented */ |
|
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