Revision 80d11f44 target-ppc/translate_init.c
| b/target-ppc/translate_init.c | ||
|---|---|---|
| 28 | 28 |
|
| 29 | 29 |
//#define PPC_DUMP_CPU |
| 30 | 30 |
//#define PPC_DEBUG_SPR |
| 31 |
//#define PPC_DEBUG_IRQ |
|
| 31 |
//#define PPC_DUMP_SPR_ACCESSES |
|
| 32 |
#if defined(CONFIG_USER_ONLY) |
|
| 33 |
#define TODO_USER_ONLY 1 |
|
| 34 |
#endif |
|
| 32 | 35 |
|
| 33 | 36 |
struct ppc_def_t {
|
| 34 | 37 |
const unsigned char *name; |
| 35 | 38 |
uint32_t pvr; |
| 39 |
uint32_t svr; |
|
| 36 | 40 |
uint64_t insns_flags; |
| 37 | 41 |
uint64_t msr_mask; |
| 38 | 42 |
powerpc_mmu_t mmu_model; |
| ... | ... | |
| 983 | 987 |
SPR_NOACCESS, SPR_NOACCESS, |
| 984 | 988 |
&spr_read_generic, &spr_write_generic, |
| 985 | 989 |
0x00000000); |
| 986 |
/* System version register */ |
|
| 987 |
/* SVR */ |
|
| 988 |
/* XXX : TODO: initialize it to an appropriate value */ |
|
| 989 |
spr_register(env, SPR_SVR, "SVR", |
|
| 990 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 991 |
&spr_read_generic, SPR_NOACCESS, |
|
| 992 |
0x00000000); |
|
| 993 | 990 |
/* Exception processing */ |
| 994 | 991 |
spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", |
| 995 | 992 |
SPR_NOACCESS, SPR_NOACCESS, |
| ... | ... | |
| 1277 | 1274 |
#endif |
| 1278 | 1275 |
} |
| 1279 | 1276 |
|
| 1280 |
/* PowerPC BookE SPR */ |
|
| 1281 |
static void gen_spr_BookE (CPUPPCState *env) |
|
| 1277 |
static void gen_spr_usprgh (CPUPPCState *env) |
|
| 1282 | 1278 |
{
|
| 1283 |
/* Processor identification */ |
|
| 1284 |
spr_register(env, SPR_BOOKE_PIR, "PIR", |
|
| 1285 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1286 |
&spr_read_generic, &spr_write_pir, |
|
| 1279 |
spr_register(env, SPR_USPRG4, "USPRG4", |
|
| 1280 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1281 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1282 |
0x00000000); |
|
| 1283 |
spr_register(env, SPR_USPRG5, "USPRG5", |
|
| 1284 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1285 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1286 |
0x00000000); |
|
| 1287 |
spr_register(env, SPR_USPRG6, "USPRG6", |
|
| 1288 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1289 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1290 |
0x00000000); |
|
| 1291 |
spr_register(env, SPR_USPRG7, "USPRG7", |
|
| 1292 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1293 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1287 | 1294 |
0x00000000); |
| 1295 |
} |
|
| 1296 |
|
|
| 1297 |
/* PowerPC BookE SPR */ |
|
| 1298 |
static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask) |
|
| 1299 |
{
|
|
| 1300 |
const unsigned char *ivor_names[64] = {
|
|
| 1301 |
"IVOR0", "IVOR1", "IVOR2", "IVOR3", |
|
| 1302 |
"IVOR4", "IVOR5", "IVOR6", "IVOR7", |
|
| 1303 |
"IVOR8", "IVOR9", "IVOR10", "IVOR11", |
|
| 1304 |
"IVOR12", "IVOR13", "IVOR14", "IVOR15", |
|
| 1305 |
"IVOR16", "IVOR17", "IVOR18", "IVOR19", |
|
| 1306 |
"IVOR20", "IVOR21", "IVOR22", "IVOR23", |
|
| 1307 |
"IVOR24", "IVOR25", "IVOR26", "IVOR27", |
|
| 1308 |
"IVOR28", "IVOR29", "IVOR30", "IVOR31", |
|
| 1309 |
"IVOR32", "IVOR33", "IVOR34", "IVOR35", |
|
| 1310 |
"IVOR36", "IVOR37", "IVOR38", "IVOR39", |
|
| 1311 |
"IVOR40", "IVOR41", "IVOR42", "IVOR43", |
|
| 1312 |
"IVOR44", "IVOR45", "IVOR46", "IVOR47", |
|
| 1313 |
"IVOR48", "IVOR49", "IVOR50", "IVOR51", |
|
| 1314 |
"IVOR52", "IVOR53", "IVOR54", "IVOR55", |
|
| 1315 |
"IVOR56", "IVOR57", "IVOR58", "IVOR59", |
|
| 1316 |
"IVOR60", "IVOR61", "IVOR62", "IVOR63", |
|
| 1317 |
}; |
|
| 1318 |
#define SPR_BOOKE_IVORxx (-1) |
|
| 1319 |
int ivor_sprn[64] = {
|
|
| 1320 |
SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, |
|
| 1321 |
SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, |
|
| 1322 |
SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, |
|
| 1323 |
SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, |
|
| 1324 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1325 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1326 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1327 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1328 |
SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, |
|
| 1329 |
SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1330 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1331 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1332 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1333 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1334 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1335 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
|
| 1336 |
}; |
|
| 1337 |
int i; |
|
| 1338 |
|
|
| 1288 | 1339 |
/* Interrupt processing */ |
| 1289 | 1340 |
spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", |
| 1290 | 1341 |
SPR_NOACCESS, SPR_NOACCESS, |
| ... | ... | |
| 1294 | 1345 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1295 | 1346 |
&spr_read_generic, &spr_write_generic, |
| 1296 | 1347 |
0x00000000); |
| 1297 |
#if 0 |
|
| 1298 |
spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", |
|
| 1299 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1300 |
&spr_read_generic, &spr_write_generic, |
|
| 1301 |
0x00000000); |
|
| 1302 |
spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", |
|
| 1303 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1304 |
&spr_read_generic, &spr_write_generic, |
|
| 1305 |
0x00000000); |
|
| 1306 |
#endif |
|
| 1307 | 1348 |
/* Debug */ |
| 1308 | 1349 |
/* XXX : not implemented */ |
| 1309 | 1350 |
spr_register(env, SPR_BOOKE_IAC1, "IAC1", |
| ... | ... | |
| 1316 | 1357 |
&spr_read_generic, &spr_write_generic, |
| 1317 | 1358 |
0x00000000); |
| 1318 | 1359 |
/* XXX : not implemented */ |
| 1319 |
spr_register(env, SPR_BOOKE_IAC3, "IAC3", |
|
| 1320 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1321 |
&spr_read_generic, &spr_write_generic, |
|
| 1322 |
0x00000000); |
|
| 1323 |
/* XXX : not implemented */ |
|
| 1324 |
spr_register(env, SPR_BOOKE_IAC4, "IAC4", |
|
| 1325 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1326 |
&spr_read_generic, &spr_write_generic, |
|
| 1327 |
0x00000000); |
|
| 1328 |
/* XXX : not implemented */ |
|
| 1329 | 1360 |
spr_register(env, SPR_BOOKE_DAC1, "DAC1", |
| 1330 | 1361 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1331 | 1362 |
&spr_read_generic, &spr_write_generic, |
| ... | ... | |
| 1336 | 1367 |
&spr_read_generic, &spr_write_generic, |
| 1337 | 1368 |
0x00000000); |
| 1338 | 1369 |
/* XXX : not implemented */ |
| 1339 |
spr_register(env, SPR_BOOKE_DVC1, "DVC1", |
|
| 1340 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1341 |
&spr_read_generic, &spr_write_generic, |
|
| 1342 |
0x00000000); |
|
| 1343 |
/* XXX : not implemented */ |
|
| 1344 |
spr_register(env, SPR_BOOKE_DVC2, "DVC2", |
|
| 1345 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1346 |
&spr_read_generic, &spr_write_generic, |
|
| 1347 |
0x00000000); |
|
| 1348 |
/* XXX : not implemented */ |
|
| 1349 | 1370 |
spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", |
| 1350 | 1371 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1351 | 1372 |
&spr_read_generic, &spr_write_generic, |
| ... | ... | |
| 1378 | 1399 |
&spr_read_generic, &spr_write_excp_prefix, |
| 1379 | 1400 |
0x00000000); |
| 1380 | 1401 |
/* Exception vectors */ |
| 1381 |
spr_register(env, SPR_BOOKE_IVOR0, "IVOR0", |
|
| 1382 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1383 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1384 |
0x00000000); |
|
| 1385 |
spr_register(env, SPR_BOOKE_IVOR1, "IVOR1", |
|
| 1386 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1387 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1388 |
0x00000000); |
|
| 1389 |
spr_register(env, SPR_BOOKE_IVOR2, "IVOR2", |
|
| 1390 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1391 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1392 |
0x00000000); |
|
| 1393 |
spr_register(env, SPR_BOOKE_IVOR3, "IVOR3", |
|
| 1394 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1395 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1396 |
0x00000000); |
|
| 1397 |
spr_register(env, SPR_BOOKE_IVOR4, "IVOR4", |
|
| 1398 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1399 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1400 |
0x00000000); |
|
| 1401 |
spr_register(env, SPR_BOOKE_IVOR5, "IVOR5", |
|
| 1402 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1403 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1404 |
0x00000000); |
|
| 1405 |
spr_register(env, SPR_BOOKE_IVOR6, "IVOR6", |
|
| 1406 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1407 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1408 |
0x00000000); |
|
| 1409 |
spr_register(env, SPR_BOOKE_IVOR7, "IVOR7", |
|
| 1410 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1411 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1412 |
0x00000000); |
|
| 1413 |
spr_register(env, SPR_BOOKE_IVOR8, "IVOR8", |
|
| 1414 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1415 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1416 |
0x00000000); |
|
| 1417 |
spr_register(env, SPR_BOOKE_IVOR9, "IVOR9", |
|
| 1418 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1419 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1420 |
0x00000000); |
|
| 1421 |
spr_register(env, SPR_BOOKE_IVOR10, "IVOR10", |
|
| 1422 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1423 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1424 |
0x00000000); |
|
| 1425 |
spr_register(env, SPR_BOOKE_IVOR11, "IVOR11", |
|
| 1426 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1427 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1428 |
0x00000000); |
|
| 1429 |
spr_register(env, SPR_BOOKE_IVOR12, "IVOR12", |
|
| 1430 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1431 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1432 |
0x00000000); |
|
| 1433 |
spr_register(env, SPR_BOOKE_IVOR13, "IVOR13", |
|
| 1434 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1435 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1436 |
0x00000000); |
|
| 1437 |
spr_register(env, SPR_BOOKE_IVOR14, "IVOR14", |
|
| 1438 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1439 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1440 |
0x00000000); |
|
| 1441 |
spr_register(env, SPR_BOOKE_IVOR15, "IVOR15", |
|
| 1442 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1443 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1444 |
0x00000000); |
|
| 1445 |
#if 0 |
|
| 1446 |
spr_register(env, SPR_BOOKE_IVOR32, "IVOR32", |
|
| 1447 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1448 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1449 |
0x00000000); |
|
| 1450 |
spr_register(env, SPR_BOOKE_IVOR33, "IVOR33", |
|
| 1451 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1452 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1453 |
0x00000000); |
|
| 1454 |
spr_register(env, SPR_BOOKE_IVOR34, "IVOR34", |
|
| 1455 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1456 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1457 |
0x00000000); |
|
| 1458 |
spr_register(env, SPR_BOOKE_IVOR35, "IVOR35", |
|
| 1459 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1460 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1461 |
0x00000000); |
|
| 1462 |
spr_register(env, SPR_BOOKE_IVOR36, "IVOR36", |
|
| 1463 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1464 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1465 |
0x00000000); |
|
| 1466 |
spr_register(env, SPR_BOOKE_IVOR37, "IVOR37", |
|
| 1467 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1468 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1469 |
0x00000000); |
|
| 1470 |
#endif |
|
| 1402 |
for (i = 0; i < 64; i++) {
|
|
| 1403 |
if (ivor_mask & (1ULL << i)) {
|
|
| 1404 |
if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
|
|
| 1405 |
fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); |
|
| 1406 |
exit(1); |
|
| 1407 |
} |
|
| 1408 |
spr_register(env, ivor_sprn[i], ivor_names[i], |
|
| 1409 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1410 |
&spr_read_generic, &spr_write_excp_vector, |
|
| 1411 |
0x00000000); |
|
| 1412 |
} |
|
| 1413 |
} |
|
| 1471 | 1414 |
spr_register(env, SPR_BOOKE_PID, "PID", |
| 1472 | 1415 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1473 | 1416 |
&spr_read_generic, &spr_write_generic, |
| ... | ... | |
| 1498 | 1441 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1499 | 1442 |
&spr_read_generic, &spr_write_generic, |
| 1500 | 1443 |
0x00000000); |
| 1501 |
spr_register(env, SPR_USPRG4, "USPRG4", |
|
| 1502 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1503 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1504 |
0x00000000); |
|
| 1505 | 1444 |
spr_register(env, SPR_SPRG5, "SPRG5", |
| 1506 | 1445 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1507 | 1446 |
&spr_read_generic, &spr_write_generic, |
| 1508 | 1447 |
0x00000000); |
| 1509 |
spr_register(env, SPR_USPRG5, "USPRG5", |
|
| 1510 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1511 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1512 |
0x00000000); |
|
| 1513 | 1448 |
spr_register(env, SPR_SPRG6, "SPRG6", |
| 1514 | 1449 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1515 | 1450 |
&spr_read_generic, &spr_write_generic, |
| 1516 | 1451 |
0x00000000); |
| 1517 |
spr_register(env, SPR_USPRG6, "USPRG6", |
|
| 1518 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1519 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1520 |
0x00000000); |
|
| 1521 | 1452 |
spr_register(env, SPR_SPRG7, "SPRG7", |
| 1522 | 1453 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1523 | 1454 |
&spr_read_generic, &spr_write_generic, |
| 1524 | 1455 |
0x00000000); |
| 1525 |
spr_register(env, SPR_USPRG7, "USPRG7", |
|
| 1526 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1527 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1528 |
0x00000000); |
|
| 1529 | 1456 |
} |
| 1530 | 1457 |
|
| 1531 | 1458 |
/* FSL storage control registers */ |
| 1532 |
static void gen_spr_BookE_FSL (CPUPPCState *env) |
|
| 1459 |
static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
|
|
| 1533 | 1460 |
{
|
| 1534 | 1461 |
#if !defined(CONFIG_USER_ONLY) |
| 1462 |
const unsigned char *mas_names[8] = {
|
|
| 1463 |
"MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", |
|
| 1464 |
}; |
|
| 1465 |
int mas_sprn[8] = {
|
|
| 1466 |
SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, |
|
| 1467 |
SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, |
|
| 1468 |
}; |
|
| 1469 |
int i; |
|
| 1470 |
|
|
| 1535 | 1471 |
/* TLB assist registers */ |
| 1536 | 1472 |
/* XXX : not implemented */ |
| 1537 |
spr_register(env, SPR_BOOKE_MAS0, "MAS0", |
|
| 1538 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1539 |
&spr_read_generic, &spr_write_generic, |
|
| 1540 |
0x00000000); |
|
| 1541 |
/* XXX : not implemented */ |
|
| 1542 |
spr_register(env, SPR_BOOKE_MAS1, "MAS2", |
|
| 1543 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1544 |
&spr_read_generic, &spr_write_generic, |
|
| 1545 |
0x00000000); |
|
| 1546 |
/* XXX : not implemented */ |
|
| 1547 |
spr_register(env, SPR_BOOKE_MAS2, "MAS3", |
|
| 1548 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1549 |
&spr_read_generic, &spr_write_generic, |
|
| 1550 |
0x00000000); |
|
| 1551 |
/* XXX : not implemented */ |
|
| 1552 |
spr_register(env, SPR_BOOKE_MAS3, "MAS4", |
|
| 1553 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1554 |
&spr_read_generic, &spr_write_generic, |
|
| 1555 |
0x00000000); |
|
| 1556 |
/* XXX : not implemented */ |
|
| 1557 |
spr_register(env, SPR_BOOKE_MAS4, "MAS5", |
|
| 1558 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1559 |
&spr_read_generic, &spr_write_generic, |
|
| 1560 |
0x00000000); |
|
| 1561 |
/* XXX : not implemented */ |
|
| 1562 |
spr_register(env, SPR_BOOKE_MAS6, "MAS6", |
|
| 1563 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1564 |
&spr_read_generic, &spr_write_generic, |
|
| 1565 |
0x00000000); |
|
| 1566 |
/* XXX : not implemented */ |
|
| 1567 |
spr_register(env, SPR_BOOKE_MAS7, "MAS7", |
|
| 1568 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1569 |
&spr_read_generic, &spr_write_generic, |
|
| 1570 |
0x00000000); |
|
| 1473 |
for (i = 0; i < 8; i++) {
|
|
| 1474 |
if (mas_mask & (1 << i)) {
|
|
| 1475 |
spr_register(env, mas_sprn[i], mas_names[i], |
|
| 1476 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1477 |
&spr_read_generic, &spr_write_generic, |
|
| 1478 |
0x00000000); |
|
| 1479 |
} |
|
| 1480 |
} |
|
| 1571 | 1481 |
if (env->nb_pids > 1) {
|
| 1572 | 1482 |
/* XXX : not implemented */ |
| 1573 | 1483 |
spr_register(env, SPR_BOOKE_PID1, "PID1", |
| ... | ... | |
| 1915 | 1825 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1916 | 1826 |
&spr_read_generic, &spr_write_generic, |
| 1917 | 1827 |
0x00000000); |
| 1918 |
spr_register(env, SPR_USPRG4, "USPRG4", |
|
| 1919 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1920 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1921 |
0x00000000); |
|
| 1922 | 1828 |
spr_register(env, SPR_SPRG5, "SPRG5", |
| 1923 | 1829 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1924 | 1830 |
spr_read_generic, &spr_write_generic, |
| 1925 | 1831 |
0x00000000); |
| 1926 |
spr_register(env, SPR_USPRG5, "USPRG5", |
|
| 1927 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1928 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1929 |
0x00000000); |
|
| 1930 | 1832 |
spr_register(env, SPR_SPRG6, "SPRG6", |
| 1931 | 1833 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1932 | 1834 |
spr_read_generic, &spr_write_generic, |
| 1933 | 1835 |
0x00000000); |
| 1934 |
spr_register(env, SPR_USPRG6, "USPRG6", |
|
| 1935 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1936 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1937 |
0x00000000); |
|
| 1938 | 1836 |
spr_register(env, SPR_SPRG7, "SPRG7", |
| 1939 | 1837 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1940 | 1838 |
spr_read_generic, &spr_write_generic, |
| 1941 | 1839 |
0x00000000); |
| 1942 |
spr_register(env, SPR_USPRG7, "USPRG7", |
|
| 1943 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1944 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1945 |
0x00000000); |
|
| 1840 |
gen_spr_usprgh(env); |
|
| 1946 | 1841 |
} |
| 1947 | 1842 |
|
| 1948 | 1843 |
/* SPR shared between PowerPC 401 & 403 implementations */ |
| ... | ... | |
| 2206 | 2101 |
} |
| 2207 | 2102 |
#endif /* defined (TARGET_PPC64) */ |
| 2208 | 2103 |
|
| 2209 |
// XXX: TODO |
|
| 2210 |
/* |
|
| 2211 |
* AMR => SPR 29 (Power 2.04) |
|
| 2212 |
* CTRL => SPR 136 (Power 2.04) |
|
| 2213 |
* CTRL => SPR 152 (Power 2.04) |
|
| 2214 |
* SCOMC => SPR 276 (64 bits ?) |
|
| 2215 |
* SCOMD => SPR 277 (64 bits ?) |
|
| 2216 |
* TBU40 => SPR 286 (Power 2.04 hypv) |
|
| 2217 |
* HSPRG0 => SPR 304 (Power 2.04 hypv) |
|
| 2218 |
* HSPRG1 => SPR 305 (Power 2.04 hypv) |
|
| 2219 |
* HDSISR => SPR 306 (Power 2.04 hypv) |
|
| 2220 |
* HDAR => SPR 307 (Power 2.04 hypv) |
|
| 2221 |
* PURR => SPR 309 (Power 2.04 hypv) |
|
| 2222 |
* HDEC => SPR 310 (Power 2.04 hypv) |
|
| 2223 |
* HIOR => SPR 311 (hypv) |
|
| 2224 |
* RMOR => SPR 312 (970) |
|
| 2225 |
* HRMOR => SPR 313 (Power 2.04 hypv) |
|
| 2226 |
* HSRR0 => SPR 314 (Power 2.04 hypv) |
|
| 2227 |
* HSRR1 => SPR 315 (Power 2.04 hypv) |
|
| 2228 |
* LPCR => SPR 316 (970) |
|
| 2229 |
* LPIDR => SPR 317 (970) |
|
| 2230 |
* SPEFSCR => SPR 512 (Power 2.04 emb) |
|
| 2231 |
* EPR => SPR 702 (Power 2.04 emb) |
|
| 2232 |
* perf => 768-783 (Power 2.04) |
|
| 2233 |
* perf => 784-799 (Power 2.04) |
|
| 2234 |
* PPR => SPR 896 (Power 2.04) |
|
| 2235 |
* EPLC => SPR 947 (Power 2.04 emb) |
|
| 2236 |
* EPSC => SPR 948 (Power 2.04 emb) |
|
| 2237 |
* DABRX => 1015 (Power 2.04 hypv) |
|
| 2238 |
* FPECR => SPR 1022 (?) |
|
| 2239 |
* ... and more (thermal management, performance counters, ...) |
|
| 2240 |
*/ |
|
| 2241 |
|
|
| 2242 |
/*****************************************************************************/ |
|
| 2243 |
/* Exception vectors models */ |
|
| 2244 |
static void init_excp_4xx_real (CPUPPCState *env) |
|
| 2245 |
{
|
|
| 2246 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2247 |
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; |
|
| 2248 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
|
| 2249 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
|
| 2250 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
|
| 2251 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
|
| 2252 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
|
| 2253 |
env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; |
|
| 2254 |
env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; |
|
| 2255 |
env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; |
|
| 2256 |
env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; |
|
| 2257 |
env->excp_prefix = 0x00000000UL; |
|
| 2258 |
env->ivor_mask = 0x0000FFF0UL; |
|
| 2259 |
env->ivpr_mask = 0xFFFF0000UL; |
|
| 2260 |
/* Hardware reset vector */ |
|
| 2261 |
env->hreset_vector = 0xFFFFFFFCUL; |
|
| 2262 |
#endif |
|
| 2263 |
} |
|
| 2264 |
|
|
| 2265 |
static void init_excp_4xx_softmmu (CPUPPCState *env) |
|
| 2266 |
{
|
|
| 2267 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2268 |
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; |
|
| 2269 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
|
| 2270 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
|
| 2271 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
|
| 2272 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
|
| 2273 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
|
| 2274 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
|
| 2275 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
|
| 2276 |
env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; |
|
| 2277 |
env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; |
|
| 2278 |
env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; |
|
| 2279 |
env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; |
|
| 2280 |
env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; |
|
| 2281 |
env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; |
|
| 2282 |
env->excp_prefix = 0x00000000UL; |
|
| 2283 |
env->ivor_mask = 0x0000FFF0UL; |
|
| 2284 |
env->ivpr_mask = 0xFFFF0000UL; |
|
| 2285 |
/* Hardware reset vector */ |
|
| 2286 |
env->hreset_vector = 0xFFFFFFFCUL; |
|
| 2287 |
#endif |
|
| 2288 |
} |
|
| 2289 |
|
|
| 2290 |
static void init_excp_BookE (CPUPPCState *env) |
|
| 2104 |
static void gen_spr_5xx_8xx (CPUPPCState *env) |
|
| 2291 | 2105 |
{
|
| 2292 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2293 |
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; |
|
| 2106 |
/* Exception processing */ |
|
| 2107 |
spr_register(env, SPR_DSISR, "DSISR", |
|
| 2108 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2109 |
&spr_read_generic, &spr_write_generic, |
|
| 2110 |
0x00000000); |
|
| 2111 |
spr_register(env, SPR_DAR, "DAR", |
|
| 2112 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2113 |
&spr_read_generic, &spr_write_generic, |
|
| 2114 |
0x00000000); |
|
| 2115 |
/* Timer */ |
|
| 2116 |
spr_register(env, SPR_DECR, "DECR", |
|
| 2117 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2118 |
&spr_read_decr, &spr_write_decr, |
|
| 2119 |
0x00000000); |
|
| 2120 |
/* XXX : not implemented */ |
|
| 2121 |
spr_register(env, SPR_MPC_EIE, "EIE", |
|
| 2122 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2123 |
&spr_read_generic, &spr_write_generic, |
|
| 2124 |
0x00000000); |
|
| 2125 |
/* XXX : not implemented */ |
|
| 2126 |
spr_register(env, SPR_MPC_EID, "EID", |
|
| 2127 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2128 |
&spr_read_generic, &spr_write_generic, |
|
| 2129 |
0x00000000); |
|
| 2130 |
/* XXX : not implemented */ |
|
| 2131 |
spr_register(env, SPR_MPC_NRI, "NRI", |
|
| 2132 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2133 |
&spr_read_generic, &spr_write_generic, |
|
| 2134 |
0x00000000); |
|
| 2135 |
/* XXX : not implemented */ |
|
| 2136 |
spr_register(env, SPR_MPC_CMPA, "CMPA", |
|
| 2137 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2138 |
&spr_read_generic, &spr_write_generic, |
|
| 2139 |
0x00000000); |
|
| 2140 |
/* XXX : not implemented */ |
|
| 2141 |
spr_register(env, SPR_MPC_CMPB, "CMPB", |
|
| 2142 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2143 |
&spr_read_generic, &spr_write_generic, |
|
| 2144 |
0x00000000); |
|
| 2145 |
/* XXX : not implemented */ |
|
| 2146 |
spr_register(env, SPR_MPC_CMPC, "CMPC", |
|
| 2147 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2148 |
&spr_read_generic, &spr_write_generic, |
|
| 2149 |
0x00000000); |
|
| 2150 |
/* XXX : not implemented */ |
|
| 2151 |
spr_register(env, SPR_MPC_CMPD, "CMPD", |
|
| 2152 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2153 |
&spr_read_generic, &spr_write_generic, |
|
| 2154 |
0x00000000); |
|
| 2155 |
/* XXX : not implemented */ |
|
| 2156 |
spr_register(env, SPR_MPC_ECR, "ECR", |
|
| 2157 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2158 |
&spr_read_generic, &spr_write_generic, |
|
| 2159 |
0x00000000); |
|
| 2160 |
/* XXX : not implemented */ |
|
| 2161 |
spr_register(env, SPR_MPC_DER, "DER", |
|
| 2162 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2163 |
&spr_read_generic, &spr_write_generic, |
|
| 2164 |
0x00000000); |
|
| 2165 |
/* XXX : not implemented */ |
|
| 2166 |
spr_register(env, SPR_MPC_COUNTA, "COUNTA", |
|
| 2167 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2168 |
&spr_read_generic, &spr_write_generic, |
|
| 2169 |
0x00000000); |
|
| 2170 |
/* XXX : not implemented */ |
|
| 2171 |
spr_register(env, SPR_MPC_COUNTB, "COUNTB", |
|
| 2172 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2173 |
&spr_read_generic, &spr_write_generic, |
|
| 2174 |
0x00000000); |
|
| 2175 |
/* XXX : not implemented */ |
|
| 2176 |
spr_register(env, SPR_MPC_CMPE, "CMPE", |
|
| 2177 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2178 |
&spr_read_generic, &spr_write_generic, |
|
| 2179 |
0x00000000); |
|
| 2180 |
/* XXX : not implemented */ |
|
| 2181 |
spr_register(env, SPR_MPC_CMPF, "CMPF", |
|
| 2182 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2183 |
&spr_read_generic, &spr_write_generic, |
|
| 2184 |
0x00000000); |
|
| 2185 |
/* XXX : not implemented */ |
|
| 2186 |
spr_register(env, SPR_MPC_CMPG, "CMPG", |
|
| 2187 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2188 |
&spr_read_generic, &spr_write_generic, |
|
| 2189 |
0x00000000); |
|
| 2190 |
/* XXX : not implemented */ |
|
| 2191 |
spr_register(env, SPR_MPC_CMPH, "CMPH", |
|
| 2192 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2193 |
&spr_read_generic, &spr_write_generic, |
|
| 2194 |
0x00000000); |
|
| 2195 |
/* XXX : not implemented */ |
|
| 2196 |
spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", |
|
| 2197 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2198 |
&spr_read_generic, &spr_write_generic, |
|
| 2199 |
0x00000000); |
|
| 2200 |
/* XXX : not implemented */ |
|
| 2201 |
spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", |
|
| 2202 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2203 |
&spr_read_generic, &spr_write_generic, |
|
| 2204 |
0x00000000); |
|
| 2205 |
/* XXX : not implemented */ |
|
| 2206 |
spr_register(env, SPR_MPC_BAR, "BAR", |
|
| 2207 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2208 |
&spr_read_generic, &spr_write_generic, |
|
| 2209 |
0x00000000); |
|
| 2210 |
/* XXX : not implemented */ |
|
| 2211 |
spr_register(env, SPR_MPC_DPDR, "DPDR", |
|
| 2212 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2213 |
&spr_read_generic, &spr_write_generic, |
|
| 2214 |
0x00000000); |
|
| 2215 |
/* XXX : not implemented */ |
|
| 2216 |
spr_register(env, SPR_MPC_IMMR, "IMMR", |
|
| 2217 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2218 |
&spr_read_generic, &spr_write_generic, |
|
| 2219 |
0x00000000); |
|
| 2220 |
} |
|
| 2221 |
|
|
| 2222 |
static void gen_spr_5xx (CPUPPCState *env) |
|
| 2223 |
{
|
|
| 2224 |
/* XXX : not implemented */ |
|
| 2225 |
spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", |
|
| 2226 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2227 |
&spr_read_generic, &spr_write_generic, |
|
| 2228 |
0x00000000); |
|
| 2229 |
/* XXX : not implemented */ |
|
| 2230 |
spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", |
|
| 2231 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2232 |
&spr_read_generic, &spr_write_generic, |
|
| 2233 |
0x00000000); |
|
| 2234 |
/* XXX : not implemented */ |
|
| 2235 |
spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", |
|
| 2236 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2237 |
&spr_read_generic, &spr_write_generic, |
|
| 2238 |
0x00000000); |
|
| 2239 |
/* XXX : not implemented */ |
|
| 2240 |
spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", |
|
| 2241 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2242 |
&spr_read_generic, &spr_write_generic, |
|
| 2243 |
0x00000000); |
|
| 2244 |
/* XXX : not implemented */ |
|
| 2245 |
spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", |
|
| 2246 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2247 |
&spr_read_generic, &spr_write_generic, |
|
| 2248 |
0x00000000); |
|
| 2249 |
/* XXX : not implemented */ |
|
| 2250 |
spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", |
|
| 2251 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2252 |
&spr_read_generic, &spr_write_generic, |
|
| 2253 |
0x00000000); |
|
| 2254 |
/* XXX : not implemented */ |
|
| 2255 |
spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", |
|
| 2256 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2257 |
&spr_read_generic, &spr_write_generic, |
|
| 2258 |
0x00000000); |
|
| 2259 |
/* XXX : not implemented */ |
|
| 2260 |
spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", |
|
| 2261 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2262 |
&spr_read_generic, &spr_write_generic, |
|
| 2263 |
0x00000000); |
|
| 2264 |
/* XXX : not implemented */ |
|
| 2265 |
spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", |
|
| 2266 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2267 |
&spr_read_generic, &spr_write_generic, |
|
| 2268 |
0x00000000); |
|
| 2269 |
/* XXX : not implemented */ |
|
| 2270 |
spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", |
|
| 2271 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2272 |
&spr_read_generic, &spr_write_generic, |
|
| 2273 |
0x00000000); |
|
| 2274 |
/* XXX : not implemented */ |
|
| 2275 |
spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", |
|
| 2276 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2277 |
&spr_read_generic, &spr_write_generic, |
|
| 2278 |
0x00000000); |
|
| 2279 |
/* XXX : not implemented */ |
|
| 2280 |
spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", |
|
| 2281 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2282 |
&spr_read_generic, &spr_write_generic, |
|
| 2283 |
0x00000000); |
|
| 2284 |
/* XXX : not implemented */ |
|
| 2285 |
spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", |
|
| 2286 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2287 |
&spr_read_generic, &spr_write_generic, |
|
| 2288 |
0x00000000); |
|
| 2289 |
/* XXX : not implemented */ |
|
| 2290 |
spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", |
|
| 2291 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2292 |
&spr_read_generic, &spr_write_generic, |
|
| 2293 |
0x00000000); |
|
| 2294 |
/* XXX : not implemented */ |
|
| 2295 |
spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", |
|
| 2296 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2297 |
&spr_read_generic, &spr_write_generic, |
|
| 2298 |
0x00000000); |
|
| 2299 |
/* XXX : not implemented */ |
|
| 2300 |
spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", |
|
| 2301 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2302 |
&spr_read_generic, &spr_write_generic, |
|
| 2303 |
0x00000000); |
|
| 2304 |
/* XXX : not implemented */ |
|
| 2305 |
spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", |
|
| 2306 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2307 |
&spr_read_generic, &spr_write_generic, |
|
| 2308 |
0x00000000); |
|
| 2309 |
/* XXX : not implemented */ |
|
| 2310 |
spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", |
|
| 2311 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2312 |
&spr_read_generic, &spr_write_generic, |
|
| 2313 |
0x00000000); |
|
| 2314 |
/* XXX : not implemented */ |
|
| 2315 |
spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", |
|
| 2316 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2317 |
&spr_read_generic, &spr_write_generic, |
|
| 2318 |
0x00000000); |
|
| 2319 |
/* XXX : not implemented */ |
|
| 2320 |
spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", |
|
| 2321 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2322 |
&spr_read_generic, &spr_write_generic, |
|
| 2323 |
0x00000000); |
|
| 2324 |
/* XXX : not implemented */ |
|
| 2325 |
spr_register(env, SPR_RCPU_FPECR, "FPECR", |
|
| 2326 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2327 |
&spr_read_generic, &spr_write_generic, |
|
| 2328 |
0x00000000); |
|
| 2329 |
} |
|
| 2330 |
|
|
| 2331 |
static void gen_spr_8xx (CPUPPCState *env) |
|
| 2332 |
{
|
|
| 2333 |
/* XXX : not implemented */ |
|
| 2334 |
spr_register(env, SPR_MPC_IC_CST, "IC_CST", |
|
| 2335 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2336 |
&spr_read_generic, &spr_write_generic, |
|
| 2337 |
0x00000000); |
|
| 2338 |
/* XXX : not implemented */ |
|
| 2339 |
spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", |
|
| 2340 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2341 |
&spr_read_generic, &spr_write_generic, |
|
| 2342 |
0x00000000); |
|
| 2343 |
/* XXX : not implemented */ |
|
| 2344 |
spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", |
|
| 2345 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2346 |
&spr_read_generic, &spr_write_generic, |
|
| 2347 |
0x00000000); |
|
| 2348 |
/* XXX : not implemented */ |
|
| 2349 |
spr_register(env, SPR_MPC_DC_CST, "DC_CST", |
|
| 2350 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2351 |
&spr_read_generic, &spr_write_generic, |
|
| 2352 |
0x00000000); |
|
| 2353 |
/* XXX : not implemented */ |
|
| 2354 |
spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", |
|
| 2355 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2356 |
&spr_read_generic, &spr_write_generic, |
|
| 2357 |
0x00000000); |
|
| 2358 |
/* XXX : not implemented */ |
|
| 2359 |
spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", |
|
| 2360 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2361 |
&spr_read_generic, &spr_write_generic, |
|
| 2362 |
0x00000000); |
|
| 2363 |
/* XXX : not implemented */ |
|
| 2364 |
spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", |
|
| 2365 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2366 |
&spr_read_generic, &spr_write_generic, |
|
| 2367 |
0x00000000); |
|
| 2368 |
/* XXX : not implemented */ |
|
| 2369 |
spr_register(env, SPR_MPC_MI_AP, "MI_AP", |
|
| 2370 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2371 |
&spr_read_generic, &spr_write_generic, |
|
| 2372 |
0x00000000); |
|
| 2373 |
/* XXX : not implemented */ |
|
| 2374 |
spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", |
|
| 2375 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2376 |
&spr_read_generic, &spr_write_generic, |
|
| 2377 |
0x00000000); |
|
| 2378 |
/* XXX : not implemented */ |
|
| 2379 |
spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", |
|
| 2380 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2381 |
&spr_read_generic, &spr_write_generic, |
|
| 2382 |
0x00000000); |
|
| 2383 |
/* XXX : not implemented */ |
|
| 2384 |
spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", |
|
| 2385 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2386 |
&spr_read_generic, &spr_write_generic, |
|
| 2387 |
0x00000000); |
|
| 2388 |
/* XXX : not implemented */ |
|
| 2389 |
spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", |
|
| 2390 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2391 |
&spr_read_generic, &spr_write_generic, |
|
| 2392 |
0x00000000); |
|
| 2393 |
/* XXX : not implemented */ |
|
| 2394 |
spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", |
|
| 2395 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2396 |
&spr_read_generic, &spr_write_generic, |
|
| 2397 |
0x00000000); |
|
| 2398 |
/* XXX : not implemented */ |
|
| 2399 |
spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", |
|
| 2400 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2401 |
&spr_read_generic, &spr_write_generic, |
|
| 2402 |
0x00000000); |
|
| 2403 |
/* XXX : not implemented */ |
|
| 2404 |
spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", |
|
| 2405 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2406 |
&spr_read_generic, &spr_write_generic, |
|
| 2407 |
0x00000000); |
|
| 2408 |
/* XXX : not implemented */ |
|
| 2409 |
spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", |
|
| 2410 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2411 |
&spr_read_generic, &spr_write_generic, |
|
| 2412 |
0x00000000); |
|
| 2413 |
/* XXX : not implemented */ |
|
| 2414 |
spr_register(env, SPR_MPC_MD_AP, "MD_AP", |
|
| 2415 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2416 |
&spr_read_generic, &spr_write_generic, |
|
| 2417 |
0x00000000); |
|
| 2418 |
/* XXX : not implemented */ |
|
| 2419 |
spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", |
|
| 2420 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2421 |
&spr_read_generic, &spr_write_generic, |
|
| 2422 |
0x00000000); |
|
| 2423 |
/* XXX : not implemented */ |
|
| 2424 |
spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", |
|
| 2425 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2426 |
&spr_read_generic, &spr_write_generic, |
|
| 2427 |
0x00000000); |
|
| 2428 |
/* XXX : not implemented */ |
|
| 2429 |
spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", |
|
| 2430 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2431 |
&spr_read_generic, &spr_write_generic, |
|
| 2432 |
0x00000000); |
|
| 2433 |
/* XXX : not implemented */ |
|
| 2434 |
spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", |
|
| 2435 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2436 |
&spr_read_generic, &spr_write_generic, |
|
| 2437 |
0x00000000); |
|
| 2438 |
/* XXX : not implemented */ |
|
| 2439 |
spr_register(env, SPR_MPC_MD_TW, "MD_TW", |
|
| 2440 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2441 |
&spr_read_generic, &spr_write_generic, |
|
| 2442 |
0x00000000); |
|
| 2443 |
/* XXX : not implemented */ |
|
| 2444 |
spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", |
|
| 2445 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2446 |
&spr_read_generic, &spr_write_generic, |
|
| 2447 |
0x00000000); |
|
| 2448 |
/* XXX : not implemented */ |
|
| 2449 |
spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", |
|
| 2450 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2451 |
&spr_read_generic, &spr_write_generic, |
|
| 2452 |
0x00000000); |
|
| 2453 |
/* XXX : not implemented */ |
|
| 2454 |
spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", |
|
| 2455 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2456 |
&spr_read_generic, &spr_write_generic, |
|
| 2457 |
0x00000000); |
|
| 2458 |
} |
|
| 2459 |
|
|
| 2460 |
// XXX: TODO |
|
| 2461 |
/* |
|
| 2462 |
* AMR => SPR 29 (Power 2.04) |
|
| 2463 |
* CTRL => SPR 136 (Power 2.04) |
|
| 2464 |
* CTRL => SPR 152 (Power 2.04) |
|
| 2465 |
* SCOMC => SPR 276 (64 bits ?) |
|
| 2466 |
* SCOMD => SPR 277 (64 bits ?) |
|
| 2467 |
* TBU40 => SPR 286 (Power 2.04 hypv) |
|
| 2468 |
* HSPRG0 => SPR 304 (Power 2.04 hypv) |
|
| 2469 |
* HSPRG1 => SPR 305 (Power 2.04 hypv) |
|
| 2470 |
* HDSISR => SPR 306 (Power 2.04 hypv) |
|
| 2471 |
* HDAR => SPR 307 (Power 2.04 hypv) |
|
| 2472 |
* PURR => SPR 309 (Power 2.04 hypv) |
|
| 2473 |
* HDEC => SPR 310 (Power 2.04 hypv) |
|
| 2474 |
* HIOR => SPR 311 (hypv) |
|
| 2475 |
* RMOR => SPR 312 (970) |
|
| 2476 |
* HRMOR => SPR 313 (Power 2.04 hypv) |
|
| 2477 |
* HSRR0 => SPR 314 (Power 2.04 hypv) |
|
| 2478 |
* HSRR1 => SPR 315 (Power 2.04 hypv) |
|
| 2479 |
* LPCR => SPR 316 (970) |
|
| 2480 |
* LPIDR => SPR 317 (970) |
|
| 2481 |
* SPEFSCR => SPR 512 (Power 2.04 emb) |
|
| 2482 |
* EPR => SPR 702 (Power 2.04 emb) |
|
| 2483 |
* perf => 768-783 (Power 2.04) |
|
| 2484 |
* perf => 784-799 (Power 2.04) |
|
| 2485 |
* PPR => SPR 896 (Power 2.04) |
|
| 2486 |
* EPLC => SPR 947 (Power 2.04 emb) |
|
| 2487 |
* EPSC => SPR 948 (Power 2.04 emb) |
|
| 2488 |
* DABRX => 1015 (Power 2.04 hypv) |
|
| 2489 |
* FPECR => SPR 1022 (?) |
|
| 2490 |
* ... and more (thermal management, performance counters, ...) |
|
| 2491 |
*/ |
|
| 2492 |
|
|
| 2493 |
/*****************************************************************************/ |
|
| 2494 |
/* Exception vectors models */ |
|
| 2495 |
static void init_excp_4xx_real (CPUPPCState *env) |
|
| 2496 |
{
|
|
| 2497 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2498 |
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; |
|
| 2499 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
|
| 2500 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
|
| 2501 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
|
| 2502 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
|
| 2503 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
|
| 2504 |
env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; |
|
| 2505 |
env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; |
|
| 2506 |
env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; |
|
| 2507 |
env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; |
|
| 2508 |
env->excp_prefix = 0x00000000UL; |
|
| 2509 |
env->ivor_mask = 0x0000FFF0UL; |
|
| 2510 |
env->ivpr_mask = 0xFFFF0000UL; |
|
| 2511 |
/* Hardware reset vector */ |
|
| 2512 |
env->hreset_vector = 0xFFFFFFFCUL; |
|
| 2513 |
#endif |
|
| 2514 |
} |
|
| 2515 |
|
|
| 2516 |
static void init_excp_4xx_softmmu (CPUPPCState *env) |
|
| 2517 |
{
|
|
| 2518 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2519 |
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; |
|
| 2520 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
|
| 2521 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
|
| 2522 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
|
| 2523 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
|
| 2524 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
|
| 2525 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
|
| 2526 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
|
| 2527 |
env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; |
|
| 2528 |
env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; |
|
| 2529 |
env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; |
|
| 2530 |
env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; |
|
| 2531 |
env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; |
|
| 2532 |
env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; |
|
| 2533 |
env->excp_prefix = 0x00000000UL; |
|
| 2534 |
env->ivor_mask = 0x0000FFF0UL; |
|
| 2535 |
env->ivpr_mask = 0xFFFF0000UL; |
|
| 2536 |
/* Hardware reset vector */ |
|
| 2537 |
env->hreset_vector = 0xFFFFFFFCUL; |
|
| 2538 |
#endif |
|
| 2539 |
} |
|
| 2540 |
|
|
| 2541 |
static void init_excp_MPC5xx (CPUPPCState *env) |
|
| 2542 |
{
|
|
| 2543 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2544 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
|
| 2545 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
|
| 2546 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
|
| 2547 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
|
| 2548 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
|
| 2549 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; |
|
| 2550 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
|
| 2551 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
|
| 2552 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
|
| 2553 |
env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; |
|
| 2554 |
env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; |
|
| 2555 |
env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; |
|
| 2556 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; |
|
| 2557 |
env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; |
|
| 2558 |
env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; |
|
| 2559 |
env->excp_prefix = 0x00000000UL; |
|
| 2560 |
env->ivor_mask = 0x0000FFF0UL; |
|
| 2561 |
env->ivpr_mask = 0xFFFF0000UL; |
|
| 2562 |
/* Hardware reset vector */ |
|
| 2563 |
env->hreset_vector = 0xFFFFFFFCUL; |
|
| 2564 |
#endif |
|
| 2565 |
} |
|
| 2566 |
|
|
| 2567 |
static void init_excp_MPC8xx (CPUPPCState *env) |
|
| 2568 |
{
|
|
| 2569 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2570 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
|
| 2571 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
|
| 2572 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
|
| 2573 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
|
| 2574 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
|
| 2575 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
|
| 2576 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
|
| 2577 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; |
|
| 2578 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
|
| 2579 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
|
| 2580 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
|
| 2581 |
env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; |
|
| 2582 |
env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; |
|
| 2583 |
env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; |
|
| 2584 |
env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; |
|
| 2585 |
env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; |
|
| 2586 |
env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; |
|
| 2587 |
env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; |
|
| 2588 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; |
|
| 2589 |
env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; |
|
| 2590 |
env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; |
|
| 2591 |
env->excp_prefix = 0x00000000UL; |
|
| 2592 |
env->ivor_mask = 0x0000FFF0UL; |
|
| 2593 |
env->ivpr_mask = 0xFFFF0000UL; |
|
| 2594 |
/* Hardware reset vector */ |
|
| 2595 |
env->hreset_vector = 0xFFFFFFFCUL; |
|
| 2596 |
#endif |
|
| 2597 |
} |
|
| 2598 |
|
|
| 2599 |
static void init_excp_G2 (CPUPPCState *env) |
|
| 2600 |
{
|
|
| 2601 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2602 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
|
| 2603 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
|
| 2604 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
|
| 2605 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
|
| 2606 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
|
| 2607 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
|
| 2608 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
|
| 2609 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; |
|
| 2610 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
|
| 2611 |
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; |
|
| 2612 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
|
| 2613 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
|
| 2614 |
env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; |
|
| 2615 |
env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; |
|
| 2616 |
env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; |
|
| 2617 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; |
|
| 2618 |
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; |
|
| 2619 |
env->excp_prefix = 0x00000000UL; |
|
| 2620 |
/* Hardware reset vector */ |
|
| 2621 |
env->hreset_vector = 0xFFFFFFFCUL; |
|
| 2622 |
#endif |
|
| 2623 |
} |
|
| 2624 |
|
|
| 2625 |
static void init_excp_e200 (CPUPPCState *env) |
|
| 2626 |
{
|
|
| 2627 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2628 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; |
|
| 2629 |
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; |
|
| 2630 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; |
|
| 2631 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; |
|
| 2632 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; |
|
| 2633 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; |
|
| 2634 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; |
|
| 2635 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; |
|
| 2636 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; |
|
| 2637 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; |
|
| 2638 |
env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; |
|
| 2639 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; |
|
| 2640 |
env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; |
|
| 2641 |
env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; |
|
| 2642 |
env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; |
|
| 2643 |
env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; |
|
| 2644 |
env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; |
|
| 2645 |
env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; |
|
| 2646 |
env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; |
|
| 2647 |
env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; |
|
| 2648 |
env->excp_prefix = 0x00000000UL; |
|
| 2649 |
env->ivor_mask = 0x0000FFF7UL; |
|
| 2650 |
env->ivpr_mask = 0xFFFF0000UL; |
|
| 2651 |
/* Hardware reset vector */ |
|
| 2652 |
env->hreset_vector = 0xFFFFFFFCUL; |
|
| 2653 |
#endif |
|
| 2654 |
} |
|
| 2655 |
|
|
| 2656 |
static void init_excp_BookE (CPUPPCState *env) |
|
| 2657 |
{
|
|
| 2658 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2659 |
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; |
|
| 2294 | 2660 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; |
| 2295 | 2661 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; |
| 2296 | 2662 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; |
| ... | ... | |
| 2388 | 2754 |
#endif |
| 2389 | 2755 |
} |
| 2390 | 2756 |
|
| 2391 |
static void init_excp_G2 (CPUPPCState *env) |
|
| 2757 |
static void init_excp_604 (CPUPPCState *env) |
|
| 2758 |
{
|
|
| 2759 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2760 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
|
| 2761 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
|
| 2762 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
|
| 2763 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
|
| 2764 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
|
| 2765 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
|
| 2766 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
|
| 2767 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; |
|
| 2768 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
|
| 2769 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
|
| 2770 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
|
| 2771 |
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; |
|
| 2772 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; |
|
| 2773 |
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; |
|
| 2774 |
env->excp_prefix = 0x00000000UL; |
|
| 2775 |
/* Hardware reset vector */ |
|
| 2776 |
env->hreset_vector = 0xFFFFFFFCUL; |
|
| 2777 |
#endif |
|
| 2778 |
} |
|
| 2779 |
|
|
| 2780 |
#if defined(TARGET_PPC64) |
|
| 2781 |
static void init_excp_620 (CPUPPCState *env) |
|
| 2782 |
{
|
|
| 2783 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2784 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
|
| 2785 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
|
| 2786 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
|
| 2787 |
env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; |
|
| 2788 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
|
| 2789 |
env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; |
|
| 2790 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
|
| 2791 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
|
| 2792 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
|
| 2793 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; |
|
| 2794 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
|
| 2795 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
|
| 2796 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
|
| 2797 |
env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; |
|
| 2798 |
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; |
|
| 2799 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; |
|
| 2800 |
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; |
|
| 2801 |
env->excp_prefix = 0xFFF00000UL; |
|
| 2802 |
/* Hardware reset vector */ |
|
| 2803 |
env->hreset_vector = 0x0000000000000100ULL; |
|
| 2804 |
#endif |
|
| 2805 |
} |
|
| 2806 |
#endif /* defined(TARGET_PPC64) */ |
|
| 2807 |
|
|
| 2808 |
static void init_excp_7x0 (CPUPPCState *env) |
|
| 2809 |
{
|
|
| 2810 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2811 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
|
| 2812 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
|
| 2813 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
|
| 2814 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
|
| 2815 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
|
| 2816 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
|
| 2817 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
|
| 2818 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; |
|
| 2819 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
|
| 2820 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
|
| 2821 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
|
| 2822 |
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; |
|
| 2823 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; |
|
| 2824 |
env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; |
|
| 2825 |
env->excp_prefix = 0x00000000UL; |
|
| 2826 |
/* Hardware reset vector */ |
|
| 2827 |
env->hreset_vector = 0xFFFFFFFCUL; |
|
| 2828 |
#endif |
|
| 2829 |
} |
|
| 2830 |
|
|
| 2831 |
static void init_excp_750FX (CPUPPCState *env) |
|
| 2832 |
{
|
|
| 2833 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2834 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
|
| 2835 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
|
| 2836 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
|
| 2837 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
|
| 2838 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
|
| 2839 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
|
| 2840 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
|
| 2841 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; |
|
| 2842 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
|
| 2843 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
|
| 2844 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
|
| 2845 |
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; |
|
| 2846 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; |
|
| 2847 |
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; |
|
| 2848 |
env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; |
|
| 2849 |
env->excp_prefix = 0x00000000UL; |
|
| 2850 |
/* Hardware reset vector */ |
|
| 2851 |
env->hreset_vector = 0xFFFFFFFCUL; |
|
| 2852 |
#endif |
|
| 2853 |
} |
|
| 2854 |
|
|
| 2855 |
/* XXX: Check if this is correct */ |
|
| 2856 |
static void init_excp_7x5 (CPUPPCState *env) |
|
| 2857 |
{
|
|
| 2858 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2859 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
|
| 2860 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
|
| 2861 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
|
| 2862 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
|
| 2863 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
|
| 2864 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
|
| 2865 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
|
| 2866 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; |
|
| 2867 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
|
| 2868 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
|
| 2869 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
|
| 2870 |
env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; |
|
| 2871 |
env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; |
|
| 2872 |
env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; |
|
| 2873 |
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; |
|
| 2874 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; |
|
| 2875 |
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; |
|
| 2876 |
env->excp_prefix = 0x00000000UL; |
|
| 2877 |
/* Hardware reset vector */ |
|
| 2878 |
env->hreset_vector = 0xFFFFFFFCUL; |
|
| 2879 |
#endif |
|
| 2880 |
} |
|
| 2881 |
|
|
| 2882 |
static void init_excp_7400 (CPUPPCState *env) |
|
| 2883 |
{
|
|
| 2884 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2885 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
|
| 2886 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
|
| 2887 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
|
| 2888 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
|
| 2889 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
|
| 2890 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
|
| 2891 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
|
| 2892 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; |
|
| 2893 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
|
| 2894 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
|
| 2895 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
|
| 2896 |
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; |
|
| 2897 |
env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; |
|
| 2898 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; |
|
| 2899 |
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; |
|
| 2900 |
env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; |
|
| 2901 |
env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; |
|
| 2902 |
env->excp_prefix = 0x00000000UL; |
|
| 2903 |
/* Hardware reset vector */ |
|
| 2904 |
env->hreset_vector = 0xFFFFFFFCUL; |
|
| 2905 |
#endif |
|
| 2906 |
} |
|
| 2907 |
|
|
| 2908 |
static void init_excp_7450 (CPUPPCState *env) |
|
| 2392 | 2909 |
{
|
| 2393 | 2910 |
#if !defined(CONFIG_USER_ONLY) |
| 2394 | 2911 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
| ... | ... | |
| 2400 | 2917 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
| 2401 | 2918 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; |
| 2402 | 2919 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
| 2403 |
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; |
|
| 2404 | 2920 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
| 2405 | 2921 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
| 2922 |
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; |
|
| 2923 |
env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; |
|
| 2406 | 2924 |
env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; |
| 2407 | 2925 |
env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; |
| 2408 | 2926 |
env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; |
| 2409 | 2927 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; |
| 2410 | 2928 |
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; |
| 2929 |
env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; |
|
| 2411 | 2930 |
env->excp_prefix = 0x00000000UL; |
| 2412 | 2931 |
/* Hardware reset vector */ |
| 2413 | 2932 |
env->hreset_vector = 0xFFFFFFFCUL; |
| 2414 | 2933 |
#endif |
| 2415 | 2934 |
} |
| 2416 | 2935 |
|
| 2417 |
static void init_excp_604 (CPUPPCState *env) |
|
| 2936 |
#if defined (TARGET_PPC64) |
|
| 2937 |
static void init_excp_970 (CPUPPCState *env) |
|
| 2938 |
{
|
|
| 2939 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2940 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
|
| 2941 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
|
| 2942 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
|
| 2943 |
env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; |
|
| 2944 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
|
| 2945 |
env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; |
|
| 2946 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
|
| 2947 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
|
| 2948 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
|
| 2949 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; |
|
| 2950 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
|
| 2951 |
env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; |
|
| 2952 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
|
| 2953 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
|
| 2954 |
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; |
|
| 2955 |
env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; |
|
| 2956 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; |
|
| 2957 |
env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; |
|
| 2958 |
env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; |
|
| 2959 |
env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; |
|
| 2960 |
env->excp_prefix = 0x00000000FFF00000ULL; |
|
| 2961 |
/* Hardware reset vector */ |
|
| 2962 |
env->hreset_vector = 0x0000000000000100ULL; |
|
| 2963 |
#endif |
|
| 2964 |
} |
|
| 2965 |
#endif |
|
| 2966 |
|
|
| 2967 |
/*****************************************************************************/ |
|
| 2968 |
/* Power management enable checks */ |
|
| 2969 |
static int check_pow_none (CPUPPCState *env) |
|
| 2970 |
{
|
|
| 2971 |
return 0; |
|
| 2972 |
} |
|
| 2973 |
|
|
| 2974 |
static int check_pow_nocheck (CPUPPCState *env) |
|
| 2975 |
{
|
|
| 2976 |
return 1; |
|
| 2977 |
} |
|
| 2978 |
|
|
| 2979 |
static int check_pow_hid0 (CPUPPCState *env) |
|
| 2980 |
{
|
|
| 2981 |
if (env->spr[SPR_HID0] & 0x00E00000) |
|
| 2982 |
return 1; |
|
| 2983 |
|
|
| 2984 |
return 0; |
|
| 2985 |
} |
|
| 2986 |
|
|
| 2987 |
/*****************************************************************************/ |
|
| 2988 |
/* PowerPC implementations definitions */ |
|
| 2989 |
|
|
| 2990 |
/* PowerPC 40x instruction set */ |
|
| 2991 |
#define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_WRTEE | \ |
|
| 2992 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ) |
|
| 2993 |
|
|
| 2994 |
/* PowerPC 401 */ |
|
| 2995 |
#define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \ |
|
| 2996 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
|
| 2997 |
PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) |
|
| 2998 |
#define POWERPC_MSRM_401 (0x00000000000FD201ULL) |
|
| 2999 |
#define POWERPC_MMU_401 (POWERPC_MMU_REAL) |
|
| 3000 |
#define POWERPC_EXCP_401 (POWERPC_EXCP_40x) |
|
| 3001 |
#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401) |
|
| 3002 |
#define POWERPC_BFDM_401 (bfd_mach_ppc_403) |
|
| 3003 |
#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE) |
|
| 3004 |
#define check_pow_401 check_pow_nocheck |
|
| 3005 |
|
|
| 3006 |
static void init_proc_401 (CPUPPCState *env) |
|
| 3007 |
{
|
|
| 3008 |
gen_spr_40x(env); |
|
| 3009 |
gen_spr_401_403(env); |
|
| 3010 |
gen_spr_401(env); |
|
| 3011 |
init_excp_4xx_real(env); |
|
| 3012 |
env->dcache_line_size = 32; |
|
| 3013 |
env->icache_line_size = 32; |
|
| 3014 |
/* Allocate hardware IRQ controller */ |
|
| 3015 |
ppc40x_irq_init(env); |
|
| 3016 |
} |
|
| 3017 |
|
|
| 3018 |
/* PowerPC 401x2 */ |
|
| 3019 |
#define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \ |
|
| 3020 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
|
| 3021 |
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ |
|
| 3022 |
PPC_CACHE_DCBA | PPC_MFTB | \ |
|
| 3023 |
PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) |
|
| 3024 |
#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL) |
|
| 3025 |
#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z) |
|
| 3026 |
#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x) |
|
| 3027 |
#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401) |
|
| 3028 |
#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403) |
|
| 3029 |
#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE) |
|
| 3030 |
#define check_pow_401x2 check_pow_nocheck |
|
| 3031 |
|
|
| 3032 |
static void init_proc_401x2 (CPUPPCState *env) |
|
| 2418 | 3033 |
{
|
| 3034 |
gen_spr_40x(env); |
|
| 3035 |
gen_spr_401_403(env); |
|
| 3036 |
gen_spr_401x2(env); |
|
| 3037 |
gen_spr_compress(env); |
|
| 3038 |
/* Memory management */ |
|
| 2419 | 3039 |
#if !defined(CONFIG_USER_ONLY) |
| 2420 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
|
| 2421 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
|
| 2422 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
|
| 2423 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
|
| 2424 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
|
| 2425 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
|
| 2426 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
|
| 2427 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; |
|
| 2428 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
|
| 2429 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
|
| 2430 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
|
| 2431 |
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; |
|
| 2432 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; |
|
| 2433 |
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; |
|
| 2434 |
env->excp_prefix = 0x00000000UL; |
|
| 2435 |
/* Hardware reset vector */ |
|
| 2436 |
env->hreset_vector = 0xFFFFFFFCUL; |
|
| 3040 |
env->nb_tlb = 64; |
|
| 3041 |
env->nb_ways = 1; |
|
| 3042 |
env->id_tlbs = 0; |
|
| 2437 | 3043 |
#endif |
| 3044 |
init_excp_4xx_softmmu(env); |
|
| 3045 |
env->dcache_line_size = 32; |
|
| 3046 |
env->icache_line_size = 32; |
|
| 3047 |
/* Allocate hardware IRQ controller */ |
|
| 3048 |
ppc40x_irq_init(env); |
|
| 2438 | 3049 |
} |
| 2439 | 3050 |
|
| 2440 |
#if defined(TARGET_PPC64) |
|
| 2441 |
static void init_excp_620 (CPUPPCState *env) |
|
| 3051 |
/* PowerPC 401x3 */ |
|
| 3052 |
#define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \ |
|
| 3053 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
|
| 3054 |
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ |
|
| 3055 |
PPC_CACHE_DCBA | PPC_MFTB | \ |
|
| 3056 |
PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) |
|
| 3057 |
#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL) |
|
| 3058 |
#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z) |
|
| 3059 |
#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x) |
|
| 3060 |
#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401) |
|
| 3061 |
#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403) |
|
| 3062 |
#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE) |
|
| 3063 |
#define check_pow_401x3 check_pow_nocheck |
|
| 3064 |
|
|
| 3065 |
__attribute__ (( unused )) |
|
| 3066 |
static void init_proc_401x3 (CPUPPCState *env) |
|
| 3067 |
{
|
|
| 3068 |
gen_spr_40x(env); |
|
| 3069 |
gen_spr_401_403(env); |
|
| 3070 |
gen_spr_401(env); |
|
| 3071 |
gen_spr_401x2(env); |
|
| 3072 |
gen_spr_compress(env); |
|
| 3073 |
init_excp_4xx_softmmu(env); |
|
| 3074 |
env->dcache_line_size = 32; |
|
| 3075 |
env->icache_line_size = 32; |
|
| 3076 |
/* Allocate hardware IRQ controller */ |
|
| 3077 |
ppc40x_irq_init(env); |
|
| 3078 |
} |
|
| 3079 |
|
|
| 3080 |
/* IOP480 */ |
|
| 3081 |
#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \ |
|
| 3082 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
|
| 3083 |
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ |
|
| 3084 |
PPC_CACHE_DCBA | \ |
|
| 3085 |
PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) |
|
| 3086 |
#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL) |
|
| 3087 |
#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z) |
|
| 3088 |
#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x) |
|
| 3089 |
#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401) |
|
| 3090 |
#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403) |
|
| 3091 |
#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE) |
|
| 3092 |
#define check_pow_IOP480 check_pow_nocheck |
|
| 3093 |
|
|
| 3094 |
static void init_proc_IOP480 (CPUPPCState *env) |
|
| 2442 | 3095 |
{
|
| 3096 |
gen_spr_40x(env); |
|
| 3097 |
gen_spr_401_403(env); |
|
| 3098 |
gen_spr_401x2(env); |
|
| 3099 |
gen_spr_compress(env); |
|
| 3100 |
/* Memory management */ |
|
| 2443 | 3101 |
#if !defined(CONFIG_USER_ONLY) |
| 2444 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
|
| 2445 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
|
| 2446 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
|
| 2447 |
env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; |
|
| 2448 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
|
| 2449 |
env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; |
|
| 2450 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
|
| 2451 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
|
| 2452 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
|
| 2453 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; |
|
| 2454 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
|
| 2455 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
|
| 2456 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
|
| 2457 |
env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; |
|
| 2458 |
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; |
|
| 2459 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; |
|
| 2460 |
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; |
|
| 2461 |
env->excp_prefix = 0xFFF00000UL; |
|
| 2462 |
/* Hardware reset vector */ |
|
| 2463 |
env->hreset_vector = 0x0000000000000100ULL; |
|
| 3102 |
env->nb_tlb = 64; |
|
| 3103 |
env->nb_ways = 1; |
|
| 3104 |
env->id_tlbs = 0; |
|
| 2464 | 3105 |
#endif |
| 3106 |
init_excp_4xx_softmmu(env); |
|
| 3107 |
env->dcache_line_size = 32; |
|
| 3108 |
env->icache_line_size = 32; |
|
| 3109 |
/* Allocate hardware IRQ controller */ |
|
| 3110 |
ppc40x_irq_init(env); |
|
| 2465 | 3111 |
} |
| 2466 |
#endif /* defined(TARGET_PPC64) */ |
|
| 2467 | 3112 |
|
| 2468 |
static void init_excp_7x0 (CPUPPCState *env) |
|
| 3113 |
/* PowerPC 403 */ |
|
| 3114 |
#define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \ |
|
| 3115 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
|
| 3116 |
PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) |
|
| 3117 |
#define POWERPC_MSRM_403 (0x000000000007D00DULL) |
|
| 3118 |
#define POWERPC_MMU_403 (POWERPC_MMU_REAL) |
|
| 3119 |
#define POWERPC_EXCP_403 (POWERPC_EXCP_40x) |
|
| 3120 |
#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401) |
|
| 3121 |
#define POWERPC_BFDM_403 (bfd_mach_ppc_403) |
|
| 3122 |
#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX) |
|
| 3123 |
#define check_pow_403 check_pow_nocheck |
|
| 3124 |
|
|
| 3125 |
static void init_proc_403 (CPUPPCState *env) |
|
| 2469 | 3126 |
{
|
| 3127 |
gen_spr_40x(env); |
|
| 3128 |
gen_spr_401_403(env); |
|
| 3129 |
gen_spr_403(env); |
|
| 3130 |
gen_spr_403_real(env); |
|
| 3131 |
init_excp_4xx_real(env); |
|
| 3132 |
env->dcache_line_size = 32; |
|
| 3133 |
env->icache_line_size = 32; |
|
| 3134 |
/* Allocate hardware IRQ controller */ |
|
| 3135 |
ppc40x_irq_init(env); |
|
| 2470 | 3136 |
#if !defined(CONFIG_USER_ONLY) |
| 2471 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
|
| 2472 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
|
| 2473 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
|
| 2474 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
|
| 2475 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
|
| 2476 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
|
| 2477 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
|
| 2478 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; |
|
| 2479 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
|
| 2480 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
|
| 2481 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
|
| 2482 |
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; |
|
| 2483 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; |
|
| 2484 |
env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; |
|
| 2485 |
env->excp_prefix = 0x00000000UL; |
|
| 2486 | 3137 |
/* Hardware reset vector */ |
| 2487 | 3138 |
env->hreset_vector = 0xFFFFFFFCUL; |
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