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/*
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 * SH-7750 memory-mapped registers
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 * This file based on information provided in the following document:
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 * "Hitachi SuperH (tm) RISC engine. SH7750 Series (SH7750, SH7750S)
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 *  Hardware Manual"
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 *  Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd.
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 *
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 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
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 * Author: Alexandra Kossovsky <sasha@oktet.ru>
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 *         Victor V. Vengerov <vvv@oktet.ru>
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 *
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 * The license and distribution terms for this file may be
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 * found in the file LICENSE in this distribution or at
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 *  http://www.rtems.com/license/LICENSE.
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 *
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 * @(#) sh7750_regs.h,v 1.2.4.1 2003/09/04 18:46:00 joel Exp
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 */
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#ifndef __SH7750_REGS_H__
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#define __SH7750_REGS_H__
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/*
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 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address)  and
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 * in 0x1f000000 - 0x1fffffff (area 7 address)
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 */
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#define SH7750_P4_BASE       0xff000000        /* Accessable only in
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                                           priveleged mode */
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#define SH7750_A7_BASE       0x1f000000        /* Accessable only using TLB */
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#define SH7750_P4_REG32(ofs) (SH7750_P4_BASE + (ofs))
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#define SH7750_A7_REG32(ofs) (SH7750_A7_BASE + (ofs))
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/*
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 * MMU Registers
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 */
36

    
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/* Page Table Entry High register - PTEH */
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#define SH7750_PTEH_REGOFS    0x000000        /* offset */
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#define SH7750_PTEH           SH7750_P4_REG32(SH7750_PTEH_REGOFS)
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#define SH7750_PTEH_A7        SH7750_A7_REG32(SH7750_PTEH_REGOFS)
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#define SH7750_PTEH_VPN       0xfffffd00        /* Virtual page number */
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#define SH7750_PTEH_VPN_S     10
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#define SH7750_PTEH_ASID      0x000000ff        /* Address space identifier */
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#define SH7750_PTEH_ASID_S    0
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/* Page Table Entry Low register - PTEL */
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#define SH7750_PTEL_REGOFS    0x000004        /* offset */
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#define SH7750_PTEL           SH7750_P4_REG32(SH7750_PTEL_REGOFS)
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#define SH7750_PTEL_A7        SH7750_A7_REG32(SH7750_PTEL_REGOFS)
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#define SH7750_PTEL_PPN       0x1ffffc00        /* Physical page number */
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#define SH7750_PTEL_PPN_S     10
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#define SH7750_PTEL_V         0x00000100        /* Validity (0-entry is invalid) */
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#define SH7750_PTEL_SZ1       0x00000080        /* Page size bit 1 */
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#define SH7750_PTEL_SZ0       0x00000010        /* Page size bit 0 */
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#define SH7750_PTEL_SZ_1KB    0x00000000        /*   1-kbyte page */
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#define SH7750_PTEL_SZ_4KB    0x00000010        /*   4-kbyte page */
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#define SH7750_PTEL_SZ_64KB   0x00000080        /*   64-kbyte page */
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#define SH7750_PTEL_SZ_1MB    0x00000090        /*   1-Mbyte page */
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#define SH7750_PTEL_PR        0x00000060        /* Protection Key Data */
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#define SH7750_PTEL_PR_ROPO   0x00000000        /*   read-only in priv mode */
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#define SH7750_PTEL_PR_RWPO   0x00000020        /*   read-write in priv mode */
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#define SH7750_PTEL_PR_ROPU   0x00000040        /*   read-only in priv or user mode */
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#define SH7750_PTEL_PR_RWPU   0x00000060        /*   read-write in priv or user mode */
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#define SH7750_PTEL_C         0x00000008        /* Cacheability
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                                                   (0 - page not cacheable) */
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#define SH7750_PTEL_D         0x00000004        /* Dirty bit (1 - write has been
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                                                   performed to a page) */
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#define SH7750_PTEL_SH        0x00000002        /* Share Status bit (1 - page are
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                                                   shared by processes) */
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#define SH7750_PTEL_WT        0x00000001        /* Write-through bit, specifies the
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                                                   cache write mode:
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                                                   0 - Copy-back mode
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                                                   1 - Write-through mode */
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/* Page Table Entry Assistance register - PTEA */
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#define SH7750_PTEA_REGOFS    0x000034        /* offset */
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#define SH7750_PTEA           SH7750_P4_REG32(SH7750_PTEA_REGOFS)
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#define SH7750_PTEA_A7        SH7750_A7_REG32(SH7750_PTEA_REGOFS)
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#define SH7750_PTEA_TC        0x00000008        /* Timing Control bit
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                                                   0 - use area 5 wait states
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                                                   1 - use area 6 wait states */
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#define SH7750_PTEA_SA        0x00000007        /* Space Attribute bits: */
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#define SH7750_PTEA_SA_UNDEF  0x00000000        /*    0 - undefined */
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#define SH7750_PTEA_SA_IOVAR  0x00000001        /*    1 - variable-size I/O space */
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#define SH7750_PTEA_SA_IO8    0x00000002        /*    2 - 8-bit I/O space */
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#define SH7750_PTEA_SA_IO16   0x00000003        /*    3 - 16-bit I/O space */
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#define SH7750_PTEA_SA_CMEM8  0x00000004        /*    4 - 8-bit common memory space */
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#define SH7750_PTEA_SA_CMEM16 0x00000005        /*    5 - 16-bit common memory space */
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#define SH7750_PTEA_SA_AMEM8  0x00000006        /*    6 - 8-bit attr memory space */
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#define SH7750_PTEA_SA_AMEM16 0x00000007        /*    7 - 16-bit attr memory space */
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/* Translation table base register */
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#define SH7750_TTB_REGOFS     0x000008        /* offset */
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#define SH7750_TTB            SH7750_P4_REG32(SH7750_TTB_REGOFS)
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#define SH7750_TTB_A7         SH7750_A7_REG32(SH7750_TTB_REGOFS)
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/* TLB exeption address register - TEA */
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#define SH7750_TEA_REGOFS     0x00000c        /* offset */
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#define SH7750_TEA            SH7750_P4_REG32(SH7750_TEA_REGOFS)
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#define SH7750_TEA_A7         SH7750_A7_REG32(SH7750_TEA_REGOFS)
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/* MMU control register - MMUCR */
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#define SH7750_MMUCR_REGOFS   0x000010        /* offset */
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#define SH7750_MMUCR          SH7750_P4_REG32(SH7750_MMUCR_REGOFS)
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#define SH7750_MMUCR_A7       SH7750_A7_REG32(SH7750_MMUCR_REGOFS)
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#define SH7750_MMUCR_AT       0x00000001        /* Address translation bit */
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#define SH7750_MMUCR_TI       0x00000004        /* TLB invalidate */
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#define SH7750_MMUCR_SV       0x00000100        /* Single Virtual Mode bit */
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#define SH7750_MMUCR_SQMD     0x00000200        /* Store Queue Mode bit */
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#define SH7750_MMUCR_URC      0x0000FC00        /* UTLB Replace Counter */
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#define SH7750_MMUCR_URC_S    10
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#define SH7750_MMUCR_URB      0x00FC0000        /* UTLB Replace Boundary */
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#define SH7750_MMUCR_URB_S    18
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#define SH7750_MMUCR_LRUI     0xFC000000        /* Least Recently Used ITLB */
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#define SH7750_MMUCR_LRUI_S   26
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120

    
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/*
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 * Cache registers
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 *   IC -- instructions cache
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 *   OC -- operand cache
125
 */
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/* Cache Control Register - CCR */
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#define SH7750_CCR_REGOFS     0x00001c        /* offset */
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#define SH7750_CCR            SH7750_P4_REG32(SH7750_CCR_REGOFS)
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#define SH7750_CCR_A7         SH7750_A7_REG32(SH7750_CCR_REGOFS)
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#define SH7750_CCR_IIX      0x00008000        /* IC index enable bit */
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#define SH7750_CCR_ICI      0x00000800        /* IC invalidation bit:
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                                           set it to clear IC */
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#define SH7750_CCR_ICE      0x00000100        /* IC enable bit */
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#define SH7750_CCR_OIX      0x00000080        /* OC index enable bit */
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#define SH7750_CCR_ORA      0x00000020        /* OC RAM enable bit
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                                           if you set OCE = 0,
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                                           you should set ORA = 0 */
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#define SH7750_CCR_OCI      0x00000008        /* OC invalidation bit */
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#define SH7750_CCR_CB       0x00000004        /* Copy-back bit for P1 area */
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#define SH7750_CCR_WT       0x00000002        /* Write-through bit for P0,U0,P3 area */
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#define SH7750_CCR_OCE      0x00000001        /* OC enable bit */
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/* Queue address control register 0 - QACR0 */
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#define SH7750_QACR0_REGOFS   0x000038        /* offset */
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#define SH7750_QACR0          SH7750_P4_REG32(SH7750_QACR0_REGOFS)
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#define SH7750_QACR0_A7       SH7750_A7_REG32(SH7750_QACR0_REGOFS)
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/* Queue address control register 1 - QACR1 */
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#define SH7750_QACR1_REGOFS   0x00003c        /* offset */
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#define SH7750_QACR1          SH7750_P4_REG32(SH7750_QACR1_REGOFS)
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#define SH7750_QACR1_A7       SH7750_A7_REG32(SH7750_QACR1_REGOFS)
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/*
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 * Exeption-related registers
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 */
159

    
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/* Immediate data for TRAPA instuction - TRA */
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#define SH7750_TRA_REGOFS     0x000020        /* offset */
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#define SH7750_TRA            SH7750_P4_REG32(SH7750_TRA_REGOFS)
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#define SH7750_TRA_A7         SH7750_A7_REG32(SH7750_TRA_REGOFS)
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#define SH7750_TRA_IMM      0x000003fd        /* Immediate data operand */
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#define SH7750_TRA_IMM_S    2
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/* Exeption event register - EXPEVT */
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#define SH7750_EXPEVT_REGOFS  0x000024
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#define SH7750_EXPEVT         SH7750_P4_REG32(SH7750_EXPEVT_REGOFS)
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#define SH7750_EXPEVT_A7      SH7750_A7_REG32(SH7750_EXPEVT_REGOFS)
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#define SH7750_EXPEVT_EX      0x00000fff        /* Exeption code */
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#define SH7750_EXPEVT_EX_S    0
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/* Interrupt event register */
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#define SH7750_INTEVT_REGOFS  0x000028
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#define SH7750_INTEVT         SH7750_P4_REG32(SH7750_INTEVT_REGOFS)
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#define SH7750_INTEVT_A7      SH7750_A7_REG32(SH7750_INTEVT_REGOFS)
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#define SH7750_INTEVT_EX    0x00000fff        /* Exeption code */
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#define SH7750_INTEVT_EX_S  0
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/*
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 * Exception/interrupt codes
185
 */
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#define SH7750_EVT_TO_NUM(evt)  ((evt) >> 5)
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/* Reset exception category */
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#define SH7750_EVT_POWER_ON_RST        0x000        /* Power-on reset */
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#define SH7750_EVT_MANUAL_RST          0x020        /* Manual reset */
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#define SH7750_EVT_TLB_MULT_HIT        0x140        /* TLB multiple-hit exception */
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/* General exception category */
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#define SH7750_EVT_USER_BREAK          0x1E0        /* User break */
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#define SH7750_EVT_IADDR_ERR           0x0E0        /* Instruction address error */
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#define SH7750_EVT_TLB_READ_MISS       0x040        /* ITLB miss exception /
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                                                   DTLB miss exception (read) */
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#define SH7750_EVT_TLB_READ_PROTV      0x0A0        /* ITLB protection violation /
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                                                   DTLB protection violation (read) */
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#define SH7750_EVT_ILLEGAL_INSTR       0x180        /* General Illegal Instruction
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                                                   exception */
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#define SH7750_EVT_SLOT_ILLEGAL_INSTR  0x1A0        /* Slot Illegal Instruction
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                                                   exception */
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#define SH7750_EVT_FPU_DISABLE         0x800        /* General FPU disable exception */
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#define SH7750_EVT_SLOT_FPU_DISABLE    0x820        /* Slot FPU disable exception */
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#define SH7750_EVT_DATA_READ_ERR       0x0E0        /* Data address error (read) */
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#define SH7750_EVT_DATA_WRITE_ERR      0x100        /* Data address error (write) */
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#define SH7750_EVT_DTLB_WRITE_MISS     0x060        /* DTLB miss exception (write) */
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#define SH7750_EVT_DTLB_WRITE_PROTV    0x0C0        /* DTLB protection violation
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                                                   exception (write) */
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#define SH7750_EVT_FPU_EXCEPTION       0x120        /* FPU exception */
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#define SH7750_EVT_INITIAL_PGWRITE     0x080        /* Initial Page Write exception */
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#define SH7750_EVT_TRAPA               0x160        /* Unconditional trap (TRAPA) */
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/* Interrupt exception category */
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#define SH7750_EVT_NMI                 0x1C0        /* Non-maskable interrupt */
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#define SH7750_EVT_IRQ0                0x200        /* External Interrupt 0 */
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#define SH7750_EVT_IRQ1                0x220        /* External Interrupt 1 */
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#define SH7750_EVT_IRQ2                0x240        /* External Interrupt 2 */
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#define SH7750_EVT_IRQ3                0x260        /* External Interrupt 3 */
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#define SH7750_EVT_IRQ4                0x280        /* External Interrupt 4 */
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#define SH7750_EVT_IRQ5                0x2A0        /* External Interrupt 5 */
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#define SH7750_EVT_IRQ6                0x2C0        /* External Interrupt 6 */
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#define SH7750_EVT_IRQ7                0x2E0        /* External Interrupt 7 */
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#define SH7750_EVT_IRQ8                0x300        /* External Interrupt 8 */
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#define SH7750_EVT_IRQ9                0x320        /* External Interrupt 9 */
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#define SH7750_EVT_IRQA                0x340        /* External Interrupt A */
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#define SH7750_EVT_IRQB                0x360        /* External Interrupt B */
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#define SH7750_EVT_IRQC                0x380        /* External Interrupt C */
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#define SH7750_EVT_IRQD                0x3A0        /* External Interrupt D */
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#define SH7750_EVT_IRQE                0x3C0        /* External Interrupt E */
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/* Peripheral Module Interrupts - Timer Unit (TMU) */
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#define SH7750_EVT_TUNI0               0x400        /* TMU Underflow Interrupt 0 */
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#define SH7750_EVT_TUNI1               0x420        /* TMU Underflow Interrupt 1 */
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#define SH7750_EVT_TUNI2               0x440        /* TMU Underflow Interrupt 2 */
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#define SH7750_EVT_TICPI2              0x460        /* TMU Input Capture Interrupt 2 */
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/* Peripheral Module Interrupts - Real-Time Clock (RTC) */
240
#define SH7750_EVT_RTC_ATI             0x480        /* Alarm Interrupt Request */
241
#define SH7750_EVT_RTC_PRI             0x4A0        /* Periodic Interrupt Request */
242
#define SH7750_EVT_RTC_CUI             0x4C0        /* Carry Interrupt Request */
243

    
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/* Peripheral Module Interrupts - Serial Communication Interface (SCI) */
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#define SH7750_EVT_SCI_ERI             0x4E0        /* Receive Error */
246
#define SH7750_EVT_SCI_RXI             0x500        /* Receive Data Register Full */
247
#define SH7750_EVT_SCI_TXI             0x520        /* Transmit Data Register Empty */
248
#define SH7750_EVT_SCI_TEI             0x540        /* Transmit End */
249

    
250
/* Peripheral Module Interrupts - Watchdog Timer (WDT) */
251
#define SH7750_EVT_WDT_ITI             0x560        /* Interval Timer Interrupt
252
                                                   (used when WDT operates in
253
                                                   interval timer mode) */
254

    
255
/* Peripheral Module Interrupts - Memory Refresh Unit (REF) */
256
#define SH7750_EVT_REF_RCMI            0x580        /* Compare-match Interrupt */
257
#define SH7750_EVT_REF_ROVI            0x5A0        /* Refresh Counter Overflow
258
                                                   interrupt */
259

    
260
/* Peripheral Module Interrupts - Hitachi User Debug Interface (H-UDI) */
261
#define SH7750_EVT_HUDI                0x600        /* UDI interrupt */
262

    
263
/* Peripheral Module Interrupts - General-Purpose I/O (GPIO) */
264
#define SH7750_EVT_GPIO                0x620        /* GPIO Interrupt */
265

    
266
/* Peripheral Module Interrupts - DMA Controller (DMAC) */
267
#define SH7750_EVT_DMAC_DMTE0          0x640        /* DMAC 0 Transfer End Interrupt */
268
#define SH7750_EVT_DMAC_DMTE1          0x660        /* DMAC 1 Transfer End Interrupt */
269
#define SH7750_EVT_DMAC_DMTE2          0x680        /* DMAC 2 Transfer End Interrupt */
270
#define SH7750_EVT_DMAC_DMTE3          0x6A0        /* DMAC 3 Transfer End Interrupt */
271
#define SH7750_EVT_DMAC_DMAE           0x6C0        /* DMAC Address Error Interrupt */
272

    
273
/* Peripheral Module Interrupts - Serial Communication Interface with FIFO */
274
/*                                                                  (SCIF) */
275
#define SH7750_EVT_SCIF_ERI            0x700        /* Receive Error */
276
#define SH7750_EVT_SCIF_RXI            0x720        /* Receive FIFO Data Full or
277
                                                   Receive Data ready interrupt */
278
#define SH7750_EVT_SCIF_BRI            0x740        /* Break or overrun error */
279
#define SH7750_EVT_SCIF_TXI            0x760        /* Transmit FIFO Data Empty */
280

    
281
/*
282
 * Power Management
283
 */
284
#define SH7750_STBCR_REGOFS   0xC00004        /* offset */
285
#define SH7750_STBCR          SH7750_P4_REG32(SH7750_STBCR_REGOFS)
286
#define SH7750_STBCR_A7       SH7750_A7_REG32(SH7750_STBCR_REGOFS)
287

    
288
#define SH7750_STBCR_STBY     0x80        /* Specifies a transition to standby mode:
289
                                           0 - Transition to SLEEP mode on SLEEP
290
                                           1 - Transition to STANDBY mode on SLEEP */
291
#define SH7750_STBCR_PHZ      0x40        /* State of peripheral module pins in
292
                                           standby mode:
293
                                           0 - normal state
294
                                           1 - high-impendance state */
295

    
296
#define SH7750_STBCR_PPU      0x20        /* Peripheral module pins pull-up controls */
297
#define SH7750_STBCR_MSTP4    0x10        /* Stopping the clock supply to DMAC */
298
#define SH7750_STBCR_DMAC_STP SH7750_STBCR_MSTP4
299
#define SH7750_STBCR_MSTP3    0x08        /* Stopping the clock supply to SCIF */
300
#define SH7750_STBCR_SCIF_STP SH7750_STBCR_MSTP3
301
#define SH7750_STBCR_MSTP2    0x04        /* Stopping the clock supply to TMU */
302
#define SH7750_STBCR_TMU_STP  SH7750_STBCR_MSTP2
303
#define SH7750_STBCR_MSTP1    0x02        /* Stopping the clock supply to RTC */
304
#define SH7750_STBCR_RTC_STP  SH7750_STBCR_MSTP1
305
#define SH7750_STBCR_MSPT0    0x01        /* Stopping the clock supply to SCI */
306
#define SH7750_STBCR_SCI_STP  SH7750_STBCR_MSTP0
307

    
308
#define SH7750_STBCR_STBY     0x80
309

    
310

    
311
#define SH7750_STBCR2_REGOFS  0xC00010        /* offset */
312
#define SH7750_STBCR2         SH7750_P4_REG32(SH7750_STBCR2_REGOFS)
313
#define SH7750_STBCR2_A7      SH7750_A7_REG32(SH7750_STBCR2_REGOFS)
314

    
315
#define SH7750_STBCR2_DSLP    0x80        /* Specifies transition to deep sleep mode:
316
                                           0 - transition to sleep or standby mode
317
                                           as it is specified in STBY bit
318
                                           1 - transition to deep sleep mode on
319
                                           execution of SLEEP instruction */
320
#define SH7750_STBCR2_MSTP6   0x02        /* Stopping the clock supply to Store Queue
321
                                           in the cache controller */
322
#define SH7750_STBCR2_SQ_STP  SH7750_STBCR2_MSTP6
323
#define SH7750_STBCR2_MSTP5   0x01        /* Stopping the clock supply to the User
324
                                           Break Controller (UBC) */
325
#define SH7750_STBCR2_UBC_STP SH7750_STBCR2_MSTP5
326

    
327
/*
328
 * Clock Pulse Generator (CPG)
329
 */
330
#define SH7750_FRQCR_REGOFS   0xC00000        /* offset */
331
#define SH7750_FRQCR          SH7750_P4_REG32(SH7750_FRQCR_REGOFS)
332
#define SH7750_FRQCR_A7       SH7750_A7_REG32(SH7750_FRQCR_REGOFS)
333

    
334
#define SH7750_FRQCR_CKOEN    0x0800        /* Clock Output Enable
335
                                           0 - CKIO pin goes to HiZ/pullup
336
                                           1 - Clock is output from CKIO */
337
#define SH7750_FRQCR_PLL1EN   0x0400        /* PLL circuit 1 enable */
338
#define SH7750_FRQCR_PLL2EN   0x0200        /* PLL circuit 2 enable */
339

    
340
#define SH7750_FRQCR_IFC      0x01C0        /* CPU clock frequency division ratio: */
341
#define SH7750_FRQCR_IFCDIV1  0x0000        /*    0 - * 1 */
342
#define SH7750_FRQCR_IFCDIV2  0x0040        /*    1 - * 1/2 */
343
#define SH7750_FRQCR_IFCDIV3  0x0080        /*    2 - * 1/3 */
344
#define SH7750_FRQCR_IFCDIV4  0x00C0        /*    3 - * 1/4 */
345
#define SH7750_FRQCR_IFCDIV6  0x0100        /*    4 - * 1/6 */
346
#define SH7750_FRQCR_IFCDIV8  0x0140        /*    5 - * 1/8 */
347

    
348
#define SH7750_FRQCR_BFC      0x0038        /* Bus clock frequency division ratio: */
349
#define SH7750_FRQCR_BFCDIV1  0x0000        /*    0 - * 1 */
350
#define SH7750_FRQCR_BFCDIV2  0x0008        /*    1 - * 1/2 */
351
#define SH7750_FRQCR_BFCDIV3  0x0010        /*    2 - * 1/3 */
352
#define SH7750_FRQCR_BFCDIV4  0x0018        /*    3 - * 1/4 */
353
#define SH7750_FRQCR_BFCDIV6  0x0020        /*    4 - * 1/6 */
354
#define SH7750_FRQCR_BFCDIV8  0x0028        /*    5 - * 1/8 */
355

    
356
#define SH7750_FRQCR_PFC      0x0007        /* Peripheral module clock frequency
357
                                           division ratio: */
358
#define SH7750_FRQCR_PFCDIV2  0x0000        /*    0 - * 1/2 */
359
#define SH7750_FRQCR_PFCDIV3  0x0001        /*    1 - * 1/3 */
360
#define SH7750_FRQCR_PFCDIV4  0x0002        /*    2 - * 1/4 */
361
#define SH7750_FRQCR_PFCDIV6  0x0003        /*    3 - * 1/6 */
362
#define SH7750_FRQCR_PFCDIV8  0x0004        /*    4 - * 1/8 */
363

    
364
/*
365
 * Watchdog Timer (WDT)
366
 */
367

    
368
/* Watchdog Timer Counter register - WTCNT */
369
#define SH7750_WTCNT_REGOFS   0xC00008        /* offset */
370
#define SH7750_WTCNT          SH7750_P4_REG32(SH7750_WTCNT_REGOFS)
371
#define SH7750_WTCNT_A7       SH7750_A7_REG32(SH7750_WTCNT_REGOFS)
372
#define SH7750_WTCNT_KEY      0x5A00        /* When WTCNT byte register written,
373
                                           you have to set the upper byte to
374
                                           0x5A */
375

    
376
/* Watchdog Timer Control/Status register - WTCSR */
377
#define SH7750_WTCSR_REGOFS   0xC0000C        /* offset */
378
#define SH7750_WTCSR          SH7750_P4_REG32(SH7750_WTCSR_REGOFS)
379
#define SH7750_WTCSR_A7       SH7750_A7_REG32(SH7750_WTCSR_REGOFS)
380
#define SH7750_WTCSR_KEY      0xA500        /* When WTCSR byte register written,
381
                                           you have to set the upper byte to
382
                                           0xA5 */
383
#define SH7750_WTCSR_TME      0x80        /* Timer enable (1-upcount start) */
384
#define SH7750_WTCSR_MODE     0x40        /* Timer Mode Select: */
385
#define SH7750_WTCSR_MODE_WT  0x40        /*    Watchdog Timer Mode */
386
#define SH7750_WTCSR_MODE_IT  0x00        /*    Interval Timer Mode */
387
#define SH7750_WTCSR_RSTS     0x20        /* Reset Select: */
388
#define SH7750_WTCSR_RST_MAN  0x20        /*    Manual Reset */
389
#define SH7750_WTCSR_RST_PWR  0x00        /*    Power-on Reset */
390
#define SH7750_WTCSR_WOVF     0x10        /* Watchdog Timer Overflow Flag */
391
#define SH7750_WTCSR_IOVF     0x08        /* Interval Timer Overflow Flag */
392
#define SH7750_WTCSR_CKS      0x07        /* Clock Select: */
393
#define SH7750_WTCSR_CKS_DIV32   0x00        /*   1/32 of frequency divider 2 input */
394
#define SH7750_WTCSR_CKS_DIV64   0x01        /*   1/64 */
395
#define SH7750_WTCSR_CKS_DIV128  0x02        /*   1/128 */
396
#define SH7750_WTCSR_CKS_DIV256  0x03        /*   1/256 */
397
#define SH7750_WTCSR_CKS_DIV512  0x04        /*   1/512 */
398
#define SH7750_WTCSR_CKS_DIV1024 0x05        /*   1/1024 */
399
#define SH7750_WTCSR_CKS_DIV2048 0x06        /*   1/2048 */
400
#define SH7750_WTCSR_CKS_DIV4096 0x07        /*   1/4096 */
401

    
402
/*
403
 * Real-Time Clock (RTC)
404
 */
405
/* 64-Hz Counter Register (byte, read-only) - R64CNT */
406
#define SH7750_R64CNT_REGOFS  0xC80000        /* offset */
407
#define SH7750_R64CNT         SH7750_P4_REG32(SH7750_R64CNT_REGOFS)
408
#define SH7750_R64CNT_A7      SH7750_A7_REG32(SH7750_R64CNT_REGOFS)
409

    
410
/* Second Counter Register (byte, BCD-coded) - RSECCNT */
411
#define SH7750_RSECCNT_REGOFS 0xC80004        /* offset */
412
#define SH7750_RSECCNT        SH7750_P4_REG32(SH7750_RSECCNT_REGOFS)
413
#define SH7750_RSECCNT_A7     SH7750_A7_REG32(SH7750_RSECCNT_REGOFS)
414

    
415
/* Minute Counter Register (byte, BCD-coded) - RMINCNT */
416
#define SH7750_RMINCNT_REGOFS 0xC80008        /* offset */
417
#define SH7750_RMINCNT        SH7750_P4_REG32(SH7750_RMINCNT_REGOFS)
418
#define SH7750_RMINCNT_A7     SH7750_A7_REG32(SH7750_RMINCNT_REGOFS)
419

    
420
/* Hour Counter Register (byte, BCD-coded) - RHRCNT */
421
#define SH7750_RHRCNT_REGOFS  0xC8000C        /* offset */
422
#define SH7750_RHRCNT         SH7750_P4_REG32(SH7750_RHRCNT_REGOFS)
423
#define SH7750_RHRCNT_A7      SH7750_A7_REG32(SH7750_RHRCNT_REGOFS)
424

    
425
/* Day-of-Week Counter Register (byte) - RWKCNT */
426
#define SH7750_RWKCNT_REGOFS  0xC80010        /* offset */
427
#define SH7750_RWKCNT         SH7750_P4_REG32(SH7750_RWKCNT_REGOFS)
428
#define SH7750_RWKCNT_A7      SH7750_A7_REG32(SH7750_RWKCNT_REGOFS)
429

    
430
#define SH7750_RWKCNT_SUN     0        /* Sunday */
431
#define SH7750_RWKCNT_MON     1        /* Monday */
432
#define SH7750_RWKCNT_TUE     2        /* Tuesday */
433
#define SH7750_RWKCNT_WED     3        /* Wednesday */
434
#define SH7750_RWKCNT_THU     4        /* Thursday */
435
#define SH7750_RWKCNT_FRI     5        /* Friday */
436
#define SH7750_RWKCNT_SAT     6        /* Saturday */
437

    
438
/* Day Counter Register (byte, BCD-coded) - RDAYCNT */
439
#define SH7750_RDAYCNT_REGOFS 0xC80014        /* offset */
440
#define SH7750_RDAYCNT        SH7750_P4_REG32(SH7750_RDAYCNT_REGOFS)
441
#define SH7750_RDAYCNT_A7     SH7750_A7_REG32(SH7750_RDAYCNT_REGOFS)
442

    
443
/* Month Counter Register (byte, BCD-coded) - RMONCNT */
444
#define SH7750_RMONCNT_REGOFS 0xC80018        /* offset */
445
#define SH7750_RMONCNT        SH7750_P4_REG32(SH7750_RMONCNT_REGOFS)
446
#define SH7750_RMONCNT_A7     SH7750_A7_REG32(SH7750_RMONCNT_REGOFS)
447

    
448
/* Year Counter Register (half, BCD-coded) - RYRCNT */
449
#define SH7750_RYRCNT_REGOFS  0xC8001C        /* offset */
450
#define SH7750_RYRCNT         SH7750_P4_REG32(SH7750_RYRCNT_REGOFS)
451
#define SH7750_RYRCNT_A7      SH7750_A7_REG32(SH7750_RYRCNT_REGOFS)
452

    
453
/* Second Alarm Register (byte, BCD-coded) - RSECAR */
454
#define SH7750_RSECAR_REGOFS  0xC80020        /* offset */
455
#define SH7750_RSECAR         SH7750_P4_REG32(SH7750_RSECAR_REGOFS)
456
#define SH7750_RSECAR_A7      SH7750_A7_REG32(SH7750_RSECAR_REGOFS)
457
#define SH7750_RSECAR_ENB     0x80        /* Second Alarm Enable */
458

    
459
/* Minute Alarm Register (byte, BCD-coded) - RMINAR */
460
#define SH7750_RMINAR_REGOFS  0xC80024        /* offset */
461
#define SH7750_RMINAR         SH7750_P4_REG32(SH7750_RMINAR_REGOFS)
462
#define SH7750_RMINAR_A7      SH7750_A7_REG32(SH7750_RMINAR_REGOFS)
463
#define SH7750_RMINAR_ENB     0x80        /* Minute Alarm Enable */
464

    
465
/* Hour Alarm Register (byte, BCD-coded) - RHRAR */
466
#define SH7750_RHRAR_REGOFS   0xC80028        /* offset */
467
#define SH7750_RHRAR          SH7750_P4_REG32(SH7750_RHRAR_REGOFS)
468
#define SH7750_RHRAR_A7       SH7750_A7_REG32(SH7750_RHRAR_REGOFS)
469
#define SH7750_RHRAR_ENB      0x80        /* Hour Alarm Enable */
470

    
471
/* Day-of-Week Alarm Register (byte) - RWKAR */
472
#define SH7750_RWKAR_REGOFS   0xC8002C        /* offset */
473
#define SH7750_RWKAR          SH7750_P4_REG32(SH7750_RWKAR_REGOFS)
474
#define SH7750_RWKAR_A7       SH7750_A7_REG32(SH7750_RWKAR_REGOFS)
475
#define SH7750_RWKAR_ENB      0x80        /* Day-of-week Alarm Enable */
476

    
477
#define SH7750_RWKAR_SUN      0        /* Sunday */
478
#define SH7750_RWKAR_MON      1        /* Monday */
479
#define SH7750_RWKAR_TUE      2        /* Tuesday */
480
#define SH7750_RWKAR_WED      3        /* Wednesday */
481
#define SH7750_RWKAR_THU      4        /* Thursday */
482
#define SH7750_RWKAR_FRI      5        /* Friday */
483
#define SH7750_RWKAR_SAT      6        /* Saturday */
484

    
485
/* Day Alarm Register (byte, BCD-coded) - RDAYAR */
486
#define SH7750_RDAYAR_REGOFS  0xC80030        /* offset */
487
#define SH7750_RDAYAR         SH7750_P4_REG32(SH7750_RDAYAR_REGOFS)
488
#define SH7750_RDAYAR_A7      SH7750_A7_REG32(SH7750_RDAYAR_REGOFS)
489
#define SH7750_RDAYAR_ENB     0x80        /* Day Alarm Enable */
490

    
491
/* Month Counter Register (byte, BCD-coded) - RMONAR */
492
#define SH7750_RMONAR_REGOFS  0xC80034        /* offset */
493
#define SH7750_RMONAR         SH7750_P4_REG32(SH7750_RMONAR_REGOFS)
494
#define SH7750_RMONAR_A7      SH7750_A7_REG32(SH7750_RMONAR_REGOFS)
495
#define SH7750_RMONAR_ENB     0x80        /* Month Alarm Enable */
496

    
497
/* RTC Control Register 1 (byte) - RCR1 */
498
#define SH7750_RCR1_REGOFS    0xC80038        /* offset */
499
#define SH7750_RCR1           SH7750_P4_REG32(SH7750_RCR1_REGOFS)
500
#define SH7750_RCR1_A7        SH7750_A7_REG32(SH7750_RCR1_REGOFS)
501
#define SH7750_RCR1_CF        0x80        /* Carry Flag */
502
#define SH7750_RCR1_CIE       0x10        /* Carry Interrupt Enable */
503
#define SH7750_RCR1_AIE       0x08        /* Alarm Interrupt Enable */
504
#define SH7750_RCR1_AF        0x01        /* Alarm Flag */
505

    
506
/* RTC Control Register 2 (byte) - RCR2 */
507
#define SH7750_RCR2_REGOFS    0xC8003C        /* offset */
508
#define SH7750_RCR2           SH7750_P4_REG32(SH7750_RCR2_REGOFS)
509
#define SH7750_RCR2_A7        SH7750_A7_REG32(SH7750_RCR2_REGOFS)
510
#define SH7750_RCR2_PEF        0x80        /* Periodic Interrupt Flag */
511
#define SH7750_RCR2_PES        0x70        /* Periodic Interrupt Enable: */
512
#define SH7750_RCR2_PES_DIS    0x00        /*   Periodic Interrupt Disabled */
513
#define SH7750_RCR2_PES_DIV256 0x10        /*   Generated at 1/256 sec interval */
514
#define SH7750_RCR2_PES_DIV64  0x20        /*   Generated at 1/64 sec interval */
515
#define SH7750_RCR2_PES_DIV16  0x30        /*   Generated at 1/16 sec interval */
516
#define SH7750_RCR2_PES_DIV4   0x40        /*   Generated at 1/4 sec interval */
517
#define SH7750_RCR2_PES_DIV2   0x50        /*   Generated at 1/2 sec interval */
518
#define SH7750_RCR2_PES_x1     0x60        /*   Generated at 1 sec interval */
519
#define SH7750_RCR2_PES_x2     0x70        /*   Generated at 2 sec interval */
520
#define SH7750_RCR2_RTCEN      0x08        /* RTC Crystal Oscillator is Operated */
521
#define SH7750_RCR2_ADJ        0x04        /* 30-Second Adjastment */
522
#define SH7750_RCR2_RESET      0x02        /* Frequency divider circuits are reset */
523
#define SH7750_RCR2_START      0x01        /* 0 - sec, min, hr, day-of-week, month,
524
                                           year counters are stopped
525
                                           1 - sec, min, hr, day-of-week, month,
526
                                           year counters operate normally */
527
/*
528
 * Bus State Controller - BSC
529
 */
530
/* Bus Control Register 1 - BCR1 */
531
#define SH7750_BCR1_REGOFS    0x800000        /* offset */
532
#define SH7750_BCR1           SH7750_P4_REG32(SH7750_BCR1_REGOFS)
533
#define SH7750_BCR1_A7        SH7750_A7_REG32(SH7750_BCR1_REGOFS)
534
#define SH7750_BCR1_ENDIAN    0x80000000        /* Endianness (1 - little endian) */
535
#define SH7750_BCR1_MASTER    0x40000000        /* Master/Slave mode (1-master) */
536
#define SH7750_BCR1_A0MPX     0x20000000        /* Area 0 Memory Type (0-SRAM,1-MPX) */
537
#define SH7750_BCR1_IPUP      0x02000000        /* Input Pin Pull-up Control:
538
                                                   0 - pull-up resistor is on for
539
                                                   control input pins
540
                                                   1 - pull-up resistor is off */
541
#define SH7750_BCR1_OPUP      0x01000000        /* Output Pin Pull-up Control:
542
                                                   0 - pull-up resistor is on for
543
                                                   control output pins
544
                                                   1 - pull-up resistor is off */
545
#define SH7750_BCR1_A1MBC     0x00200000        /* Area 1 SRAM Byte Control Mode:
546
                                                   0 - Area 1 SRAM is set to
547
                                                   normal mode
548
                                                   1 - Area 1 SRAM is set to byte
549
                                                   control mode */
550
#define SH7750_BCR1_A4MBC     0x00100000        /* Area 4 SRAM Byte Control Mode:
551
                                                   0 - Area 4 SRAM is set to
552
                                                   normal mode
553
                                                   1 - Area 4 SRAM is set to byte
554
                                                   control mode */
555
#define SH7750_BCR1_BREQEN    0x00080000        /* BREQ Enable:
556
                                                   0 - External requests are  not
557
                                                   accepted
558
                                                   1 - External requests are
559
                                                   accepted */
560
#define SH7750_BCR1_PSHR      0x00040000        /* Partial Sharing Bit:
561
                                                   0 - Master Mode
562
                                                   1 - Partial-sharing Mode */
563
#define SH7750_BCR1_MEMMPX    0x00020000        /* Area 1 to 6 MPX Interface:
564
                                                   0 - SRAM/burst ROM interface
565
                                                   1 - MPX interface */
566
#define SH7750_BCR1_HIZMEM    0x00008000        /* High Impendance Control. Specifies
567
                                                   the state of A[25:0], BS\, CSn\,
568
                                                   RD/WR\, CE2A\, CE2B\ in standby
569
                                                   mode and when bus is released:
570
                                                   0 - signals go to High-Z mode
571
                                                   1 - signals driven */
572
#define SH7750_BCR1_HIZCNT    0x00004000        /* High Impendance Control. Specifies
573
                                                   the state of the RAS\, RAS2\, WEn\,
574
                                                   CASn\, DQMn, RD\, CASS\, FRAME\,
575
                                                   RD2\ signals in standby mode and
576
                                                   when bus is released:
577
                                                   0 - signals go to High-Z mode
578
                                                   1 - signals driven */
579
#define SH7750_BCR1_A0BST     0x00003800        /* Area 0 Burst ROM Control */
580
#define SH7750_BCR1_A0BST_SRAM    0x0000        /*   Area 0 accessed as SRAM i/f */
581
#define SH7750_BCR1_A0BST_ROM4    0x0800        /*   Area 0 accessed as burst ROM
582
                                                   interface, 4 cosequtive access */
583
#define SH7750_BCR1_A0BST_ROM8    0x1000        /*   Area 0 accessed as burst ROM
584
                                                   interface, 8 cosequtive access */
585
#define SH7750_BCR1_A0BST_ROM16   0x1800        /*   Area 0 accessed as burst ROM
586
                                                   interface, 16 cosequtive access */
587
#define SH7750_BCR1_A0BST_ROM32   0x2000        /*   Area 0 accessed as burst ROM
588
                                                   interface, 32 cosequtive access */
589

    
590
#define SH7750_BCR1_A5BST     0x00000700        /* Area 5 Burst ROM Control */
591
#define SH7750_BCR1_A5BST_SRAM    0x0000        /*   Area 5 accessed as SRAM i/f */
592
#define SH7750_BCR1_A5BST_ROM4    0x0100        /*   Area 5 accessed as burst ROM
593
                                                   interface, 4 cosequtive access */
594
#define SH7750_BCR1_A5BST_ROM8    0x0200        /*   Area 5 accessed as burst ROM
595
                                                   interface, 8 cosequtive access */
596
#define SH7750_BCR1_A5BST_ROM16   0x0300        /*   Area 5 accessed as burst ROM
597
                                                   interface, 16 cosequtive access */
598
#define SH7750_BCR1_A5BST_ROM32   0x0400        /*   Area 5 accessed as burst ROM
599
                                                   interface, 32 cosequtive access */
600

    
601
#define SH7750_BCR1_A6BST     0x000000E0        /* Area 6 Burst ROM Control */
602
#define SH7750_BCR1_A6BST_SRAM    0x0000        /*   Area 6 accessed as SRAM i/f */
603
#define SH7750_BCR1_A6BST_ROM4    0x0020        /*   Area 6 accessed as burst ROM
604
                                                   interface, 4 cosequtive access */
605
#define SH7750_BCR1_A6BST_ROM8    0x0040        /*   Area 6 accessed as burst ROM
606
                                                   interface, 8 cosequtive access */
607
#define SH7750_BCR1_A6BST_ROM16   0x0060        /*   Area 6 accessed as burst ROM
608
                                                   interface, 16 cosequtive access */
609
#define SH7750_BCR1_A6BST_ROM32   0x0080        /*   Area 6 accessed as burst ROM
610
                                                   interface, 32 cosequtive access */
611

    
612
#define SH7750_BCR1_DRAMTP        0x001C        /* Area 2 and 3 Memory Type */
613
#define SH7750_BCR1_DRAMTP_2SRAM_3SRAM   0x0000        /* Area 2 and 3 are SRAM or MPX
614
                                                   interface. */
615
#define SH7750_BCR1_DRAMTP_2SRAM_3SDRAM  0x0008        /* Area 2 - SRAM/MPX, Area 3 -
616
                                                   synchronous DRAM */
617
#define SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM 0x000C        /* Area 2 and 3 are synchronous
618
                                                   DRAM interface */
619
#define SH7750_BCR1_DRAMTP_2SRAM_3DRAM   0x0010        /* Area 2 - SRAM/MPX, Area 3 -
620
                                                   DRAM interface */
621
#define SH7750_BCR1_DRAMTP_2DRAM_3DRAM   0x0014        /* Area 2 and 3 are DRAM
622
                                                   interface */
623

    
624
#define SH7750_BCR1_A56PCM    0x00000001        /* Area 5 and 6 Bus Type:
625
                                                   0 - SRAM interface
626
                                                   1 - PCMCIA interface */
627

    
628
/* Bus Control Register 2 (half) - BCR2 */
629
#define SH7750_BCR2_REGOFS    0x800004        /* offset */
630
#define SH7750_BCR2           SH7750_P4_REG32(SH7750_BCR2_REGOFS)
631
#define SH7750_BCR2_A7        SH7750_A7_REG32(SH7750_BCR2_REGOFS)
632

    
633
#define SH7750_BCR2_A0SZ      0xC000        /* Area 0 Bus Width */
634
#define SH7750_BCR2_A0SZ_S    14
635
#define SH7750_BCR2_A6SZ      0x3000        /* Area 6 Bus Width */
636
#define SH7750_BCR2_A6SZ_S    12
637
#define SH7750_BCR2_A5SZ      0x0C00        /* Area 5 Bus Width */
638
#define SH7750_BCR2_A5SZ_S    10
639
#define SH7750_BCR2_A4SZ      0x0300        /* Area 4 Bus Width */
640
#define SH7750_BCR2_A4SZ_S    8
641
#define SH7750_BCR2_A3SZ      0x00C0        /* Area 3 Bus Width */
642
#define SH7750_BCR2_A3SZ_S    6
643
#define SH7750_BCR2_A2SZ      0x0030        /* Area 2 Bus Width */
644
#define SH7750_BCR2_A2SZ_S    4
645
#define SH7750_BCR2_A1SZ      0x000C        /* Area 1 Bus Width */
646
#define SH7750_BCR2_A1SZ_S    2
647
#define SH7750_BCR2_SZ_64     0        /* 64 bits */
648
#define SH7750_BCR2_SZ_8      1        /* 8 bits */
649
#define SH7750_BCR2_SZ_16     2        /* 16 bits */
650
#define SH7750_BCR2_SZ_32     3        /* 32 bits */
651
#define SH7750_BCR2_PORTEN    0x0001        /* Port Function Enable :
652
                                           0 - D51-D32 are not used as a port
653
                                           1 - D51-D32 are used as a port */
654

    
655
/* Wait Control Register 1 - WCR1 */
656
#define SH7750_WCR1_REGOFS    0x800008        /* offset */
657
#define SH7750_WCR1           SH7750_P4_REG32(SH7750_WCR1_REGOFS)
658
#define SH7750_WCR1_A7        SH7750_A7_REG32(SH7750_WCR1_REGOFS)
659
#define SH7750_WCR1_DMAIW     0x70000000        /* DACK Device Inter-Cycle Idle
660
                                                   specification */
661
#define SH7750_WCR1_DMAIW_S   28
662
#define SH7750_WCR1_A6IW      0x07000000        /* Area 6 Inter-Cycle Idle spec. */
663
#define SH7750_WCR1_A6IW_S    24
664
#define SH7750_WCR1_A5IW      0x00700000        /* Area 5 Inter-Cycle Idle spec. */
665
#define SH7750_WCR1_A5IW_S    20
666
#define SH7750_WCR1_A4IW      0x00070000        /* Area 4 Inter-Cycle Idle spec. */
667
#define SH7750_WCR1_A4IW_S    16
668
#define SH7750_WCR1_A3IW      0x00007000        /* Area 3 Inter-Cycle Idle spec. */
669
#define SH7750_WCR1_A3IW_S    12
670
#define SH7750_WCR1_A2IW      0x00000700        /* Area 2 Inter-Cycle Idle spec. */
671
#define SH7750_WCR1_A2IW_S    8
672
#define SH7750_WCR1_A1IW      0x00000070        /* Area 1 Inter-Cycle Idle spec. */
673
#define SH7750_WCR1_A1IW_S    4
674
#define SH7750_WCR1_A0IW      0x00000007        /* Area 0 Inter-Cycle Idle spec. */
675
#define SH7750_WCR1_A0IW_S    0
676

    
677
/* Wait Control Register 2 - WCR2 */
678
#define SH7750_WCR2_REGOFS    0x80000C        /* offset */
679
#define SH7750_WCR2           SH7750_P4_REG32(SH7750_WCR2_REGOFS)
680
#define SH7750_WCR2_A7        SH7750_A7_REG32(SH7750_WCR2_REGOFS)
681

    
682
#define SH7750_WCR2_A6W       0xE0000000        /* Area 6 Wait Control */
683
#define SH7750_WCR2_A6W_S     29
684
#define SH7750_WCR2_A6B       0x1C000000        /* Area 6 Burst Pitch */
685
#define SH7750_WCR2_A6B_S     26
686
#define SH7750_WCR2_A5W       0x03800000        /* Area 5 Wait Control */
687
#define SH7750_WCR2_A5W_S     23
688
#define SH7750_WCR2_A5B       0x00700000        /* Area 5 Burst Pitch */
689
#define SH7750_WCR2_A5B_S     20
690
#define SH7750_WCR2_A4W       0x000E0000        /* Area 4 Wait Control */
691
#define SH7750_WCR2_A4W_S     17
692
#define SH7750_WCR2_A3W       0x0000E000        /* Area 3 Wait Control */
693
#define SH7750_WCR2_A3W_S     13
694
#define SH7750_WCR2_A2W       0x00000E00        /* Area 2 Wait Control */
695
#define SH7750_WCR2_A2W_S     9
696
#define SH7750_WCR2_A1W       0x000001C0        /* Area 1 Wait Control */
697
#define SH7750_WCR2_A1W_S     6
698
#define SH7750_WCR2_A0W       0x00000038        /* Area 0 Wait Control */
699
#define SH7750_WCR2_A0W_S     3
700
#define SH7750_WCR2_A0B       0x00000007        /* Area 0 Burst Pitch */
701
#define SH7750_WCR2_A0B_S     0
702

    
703
#define SH7750_WCR2_WS0       0        /* 0 wait states inserted */
704
#define SH7750_WCR2_WS1       1        /* 1 wait states inserted */
705
#define SH7750_WCR2_WS2       2        /* 2 wait states inserted */
706
#define SH7750_WCR2_WS3       3        /* 3 wait states inserted */
707
#define SH7750_WCR2_WS6       4        /* 6 wait states inserted */
708
#define SH7750_WCR2_WS9       5        /* 9 wait states inserted */
709
#define SH7750_WCR2_WS12      6        /* 12 wait states inserted */
710
#define SH7750_WCR2_WS15      7        /* 15 wait states inserted */
711

    
712
#define SH7750_WCR2_BPWS0     0        /* 0 wait states inserted from 2nd access */
713
#define SH7750_WCR2_BPWS1     1        /* 1 wait states inserted from 2nd access */
714
#define SH7750_WCR2_BPWS2     2        /* 2 wait states inserted from 2nd access */
715
#define SH7750_WCR2_BPWS3     3        /* 3 wait states inserted from 2nd access */
716
#define SH7750_WCR2_BPWS4     4        /* 4 wait states inserted from 2nd access */
717
#define SH7750_WCR2_BPWS5     5        /* 5 wait states inserted from 2nd access */
718
#define SH7750_WCR2_BPWS6     6        /* 6 wait states inserted from 2nd access */
719
#define SH7750_WCR2_BPWS7     7        /* 7 wait states inserted from 2nd access */
720

    
721
/* DRAM CAS\ Assertion Delay (area 3,2) */
722
#define SH7750_WCR2_DRAM_CAS_ASW1   0        /* 1 cycle */
723
#define SH7750_WCR2_DRAM_CAS_ASW2   1        /* 2 cycles */
724
#define SH7750_WCR2_DRAM_CAS_ASW3   2        /* 3 cycles */
725
#define SH7750_WCR2_DRAM_CAS_ASW4   3        /* 4 cycles */
726
#define SH7750_WCR2_DRAM_CAS_ASW7   4        /* 7 cycles */
727
#define SH7750_WCR2_DRAM_CAS_ASW10  5        /* 10 cycles */
728
#define SH7750_WCR2_DRAM_CAS_ASW13  6        /* 13 cycles */
729
#define SH7750_WCR2_DRAM_CAS_ASW16  7        /* 16 cycles */
730

    
731
/* SDRAM CAS\ Latency Cycles */
732
#define SH7750_WCR2_SDRAM_CAS_LAT1  1        /* 1 cycle */
733
#define SH7750_WCR2_SDRAM_CAS_LAT2  2        /* 2 cycles */
734
#define SH7750_WCR2_SDRAM_CAS_LAT3  3        /* 3 cycles */
735
#define SH7750_WCR2_SDRAM_CAS_LAT4  4        /* 4 cycles */
736
#define SH7750_WCR2_SDRAM_CAS_LAT5  5        /* 5 cycles */
737

    
738
/* Wait Control Register 3 - WCR3 */
739
#define SH7750_WCR3_REGOFS    0x800010        /* offset */
740
#define SH7750_WCR3           SH7750_P4_REG32(SH7750_WCR3_REGOFS)
741
#define SH7750_WCR3_A7        SH7750_A7_REG32(SH7750_WCR3_REGOFS)
742

    
743
#define SH7750_WCR3_A6S       0x04000000        /* Area 6 Write Strobe Setup time */
744
#define SH7750_WCR3_A6H       0x03000000        /* Area 6 Data Hold Time */
745
#define SH7750_WCR3_A6H_S     24
746
#define SH7750_WCR3_A5S       0x00400000        /* Area 5 Write Strobe Setup time */
747
#define SH7750_WCR3_A5H       0x00300000        /* Area 5 Data Hold Time */
748
#define SH7750_WCR3_A5H_S     20
749
#define SH7750_WCR3_A4S       0x00040000        /* Area 4 Write Strobe Setup time */
750
#define SH7750_WCR3_A4H       0x00030000        /* Area 4 Data Hold Time */
751
#define SH7750_WCR3_A4H_S     16
752
#define SH7750_WCR3_A3S       0x00004000        /* Area 3 Write Strobe Setup time */
753
#define SH7750_WCR3_A3H       0x00003000        /* Area 3 Data Hold Time */
754
#define SH7750_WCR3_A3H_S     12
755
#define SH7750_WCR3_A2S       0x00000400        /* Area 2 Write Strobe Setup time */
756
#define SH7750_WCR3_A2H       0x00000300        /* Area 2 Data Hold Time */
757
#define SH7750_WCR3_A2H_S     8
758
#define SH7750_WCR3_A1S       0x00000040        /* Area 1 Write Strobe Setup time */
759
#define SH7750_WCR3_A1H       0x00000030        /* Area 1 Data Hold Time */
760
#define SH7750_WCR3_A1H_S     4
761
#define SH7750_WCR3_A0S       0x00000004        /* Area 0 Write Strobe Setup time */
762
#define SH7750_WCR3_A0H       0x00000003        /* Area 0 Data Hold Time */
763
#define SH7750_WCR3_A0H_S     0
764

    
765
#define SH7750_WCR3_DHWS_0    0        /* 0 wait states data hold time */
766
#define SH7750_WCR3_DHWS_1    1        /* 1 wait states data hold time */
767
#define SH7750_WCR3_DHWS_2    2        /* 2 wait states data hold time */
768
#define SH7750_WCR3_DHWS_3    3        /* 3 wait states data hold time */
769

    
770
#define SH7750_MCR_REGOFS     0x800014        /* offset */
771
#define SH7750_MCR            SH7750_P4_REG32(SH7750_MCR_REGOFS)
772
#define SH7750_MCR_A7         SH7750_A7_REG32(SH7750_MCR_REGOFS)
773

    
774
#define SH7750_MCR_RASD       0x80000000        /* RAS Down mode */
775
#define SH7750_MCR_MRSET      0x40000000        /* SDRAM Mode Register Set */
776
#define SH7750_MCR_PALL       0x00000000        /* SDRAM Precharge All cmd. Mode */
777
#define SH7750_MCR_TRC        0x38000000        /* RAS Precharge Time at End of
778
                                                   Refresh: */
779
#define SH7750_MCR_TRC_0      0x00000000        /*    0 */
780
#define SH7750_MCR_TRC_3      0x08000000        /*    3 */
781
#define SH7750_MCR_TRC_6      0x10000000        /*    6 */
782
#define SH7750_MCR_TRC_9      0x18000000        /*    9 */
783
#define SH7750_MCR_TRC_12     0x20000000        /*    12 */
784
#define SH7750_MCR_TRC_15     0x28000000        /*    15 */
785
#define SH7750_MCR_TRC_18     0x30000000        /*    18 */
786
#define SH7750_MCR_TRC_21     0x38000000        /*    21 */
787

    
788
#define SH7750_MCR_TCAS       0x00800000        /* CAS Negation Period */
789
#define SH7750_MCR_TCAS_1     0x00000000        /*    1 */
790
#define SH7750_MCR_TCAS_2     0x00800000        /*    2 */
791

    
792
#define SH7750_MCR_TPC        0x00380000        /* DRAM: RAS Precharge Period
793
                                                   SDRAM: minimum number of cycles
794
                                                   until the next bank active cmd
795
                                                   is output after precharging */
796
#define SH7750_MCR_TPC_S      19
797
#define SH7750_MCR_TPC_SDRAM_1 0x00000000        /* 1 cycle */
798
#define SH7750_MCR_TPC_SDRAM_2 0x00080000        /* 2 cycles */
799
#define SH7750_MCR_TPC_SDRAM_3 0x00100000        /* 3 cycles */
800
#define SH7750_MCR_TPC_SDRAM_4 0x00180000        /* 4 cycles */
801
#define SH7750_MCR_TPC_SDRAM_5 0x00200000        /* 5 cycles */
802
#define SH7750_MCR_TPC_SDRAM_6 0x00280000        /* 6 cycles */
803
#define SH7750_MCR_TPC_SDRAM_7 0x00300000        /* 7 cycles */
804
#define SH7750_MCR_TPC_SDRAM_8 0x00380000        /* 8 cycles */
805

    
806
#define SH7750_MCR_RCD        0x00030000        /* DRAM: RAS-CAS Assertion Delay time
807
                                                   SDRAM: bank active-read/write cmd
808
                                                   delay time */
809
#define SH7750_MCR_RCD_DRAM_2  0x00000000        /* DRAM delay 2 clocks */
810
#define SH7750_MCR_RCD_DRAM_3  0x00010000        /* DRAM delay 3 clocks */
811
#define SH7750_MCR_RCD_DRAM_4  0x00020000        /* DRAM delay 4 clocks */
812
#define SH7750_MCR_RCD_DRAM_5  0x00030000        /* DRAM delay 5 clocks */
813
#define SH7750_MCR_RCD_SDRAM_2 0x00010000        /* DRAM delay 2 clocks */
814
#define SH7750_MCR_RCD_SDRAM_3 0x00020000        /* DRAM delay 3 clocks */
815
#define SH7750_MCR_RCD_SDRAM_4 0x00030000        /* DRAM delay 4 clocks */
816

    
817
#define SH7750_MCR_TRWL       0x0000E000        /* SDRAM Write Precharge Delay */
818
#define SH7750_MCR_TRWL_1     0x00000000        /*    1 */
819
#define SH7750_MCR_TRWL_2     0x00002000        /*    2 */
820
#define SH7750_MCR_TRWL_3     0x00004000        /*    3 */
821
#define SH7750_MCR_TRWL_4     0x00006000        /*    4 */
822
#define SH7750_MCR_TRWL_5     0x00008000        /*    5 */
823

    
824
#define SH7750_MCR_TRAS       0x00001C00        /* DRAM: CAS-Before-RAS Refresh RAS
825
                                                   asserting period
826
                                                   SDRAM: Command interval after
827
                                                   synchronous DRAM refresh */
828
#define SH7750_MCR_TRAS_DRAM_2         0x00000000        /* 2 */
829
#define SH7750_MCR_TRAS_DRAM_3         0x00000400        /* 3 */
830
#define SH7750_MCR_TRAS_DRAM_4         0x00000800        /* 4 */
831
#define SH7750_MCR_TRAS_DRAM_5         0x00000C00        /* 5 */
832
#define SH7750_MCR_TRAS_DRAM_6         0x00001000        /* 6 */
833
#define SH7750_MCR_TRAS_DRAM_7         0x00001400        /* 7 */
834
#define SH7750_MCR_TRAS_DRAM_8         0x00001800        /* 8 */
835
#define SH7750_MCR_TRAS_DRAM_9         0x00001C00        /* 9 */
836

    
837
#define SH7750_MCR_TRAS_SDRAM_TRC_4    0x00000000        /* 4 + TRC */
838
#define SH7750_MCR_TRAS_SDRAM_TRC_5    0x00000400        /* 5 + TRC */
839
#define SH7750_MCR_TRAS_SDRAM_TRC_6    0x00000800        /* 6 + TRC */
840
#define SH7750_MCR_TRAS_SDRAM_TRC_7    0x00000C00        /* 7 + TRC */
841
#define SH7750_MCR_TRAS_SDRAM_TRC_8    0x00001000        /* 8 + TRC */
842
#define SH7750_MCR_TRAS_SDRAM_TRC_9    0x00001400        /* 9 + TRC */
843
#define SH7750_MCR_TRAS_SDRAM_TRC_10   0x00001800        /* 10 + TRC */
844
#define SH7750_MCR_TRAS_SDRAM_TRC_11   0x00001C00        /* 11 + TRC */
845

    
846
#define SH7750_MCR_BE         0x00000200        /* Burst Enable */
847
#define SH7750_MCR_SZ         0x00000180        /* Memory Data Size */
848
#define SH7750_MCR_SZ_64      0x00000000        /*    64 bits */
849
#define SH7750_MCR_SZ_16      0x00000100        /*    16 bits */
850
#define SH7750_MCR_SZ_32      0x00000180        /*    32 bits */
851

    
852
#define SH7750_MCR_AMX        0x00000078        /* Address Multiplexing */
853
#define SH7750_MCR_AMX_S      3
854
#define SH7750_MCR_AMX_DRAM_8BIT_COL    0x00000000        /* 8-bit column addr */
855
#define SH7750_MCR_AMX_DRAM_9BIT_COL    0x00000008        /* 9-bit column addr */
856
#define SH7750_MCR_AMX_DRAM_10BIT_COL   0x00000010        /* 10-bit column addr */
857
#define SH7750_MCR_AMX_DRAM_11BIT_COL   0x00000018        /* 11-bit column addr */
858
#define SH7750_MCR_AMX_DRAM_12BIT_COL   0x00000020        /* 12-bit column addr */
859
/* See SH7750 Hardware Manual for SDRAM address multiplexor selection */
860

    
861
#define SH7750_MCR_RFSH       0x00000004        /* Refresh Control */
862
#define SH7750_MCR_RMODE      0x00000002        /* Refresh Mode: */
863
#define SH7750_MCR_RMODE_NORMAL 0x00000000        /* Normal Refresh Mode */
864
#define SH7750_MCR_RMODE_SELF   0x00000002        /* Self-Refresh Mode */
865
#define SH7750_MCR_RMODE_EDO    0x00000001        /* EDO Mode */
866

    
867
/* SDRAM Mode Set address */
868
#define SH7750_SDRAM_MODE_A2_BASE  0xFF900000
869
#define SH7750_SDRAM_MODE_A3_BASE  0xFF940000
870
#define SH7750_SDRAM_MODE_A2_32BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 2))
871
#define SH7750_SDRAM_MODE_A3_32BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 2))
872
#define SH7750_SDRAM_MODE_A2_64BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 3))
873
#define SH7750_SDRAM_MODE_A3_64BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 3))
874

    
875

    
876
/* PCMCIA Control Register (half) - PCR */
877
#define SH7750_PCR_REGOFS     0x800018        /* offset */
878
#define SH7750_PCR            SH7750_P4_REG32(SH7750_PCR_REGOFS)
879
#define SH7750_PCR_A7         SH7750_A7_REG32(SH7750_PCR_REGOFS)
880

    
881
#define SH7750_PCR_A5PCW      0xC000        /* Area 5 PCMCIA Wait - Number of wait
882
                                           states to be added to the number of
883
                                           waits specified by WCR2 in a low-speed
884
                                           PCMCIA wait cycle */
885
#define SH7750_PCR_A5PCW_0    0x0000        /*    0 waits inserted */
886
#define SH7750_PCR_A5PCW_15   0x4000        /*    15 waits inserted */
887
#define SH7750_PCR_A5PCW_30   0x8000        /*    30 waits inserted */
888
#define SH7750_PCR_A5PCW_50   0xC000        /*    50 waits inserted */
889

    
890
#define SH7750_PCR_A6PCW      0x3000        /* Area 6 PCMCIA Wait - Number of wait
891
                                           states to be added to the number of
892
                                           waits specified by WCR2 in a low-speed
893
                                           PCMCIA wait cycle */
894
#define SH7750_PCR_A6PCW_0    0x0000        /*    0 waits inserted */
895
#define SH7750_PCR_A6PCW_15   0x1000        /*    15 waits inserted */
896
#define SH7750_PCR_A6PCW_30   0x2000        /*    30 waits inserted */
897
#define SH7750_PCR_A6PCW_50   0x3000        /*    50 waits inserted */
898

    
899
#define SH7750_PCR_A5TED      0x0E00        /* Area 5 Address-OE\/WE\ Assertion Delay,
900
                                           delay time from address output to
901
                                           OE\/WE\ assertion on the connected
902
                                           PCMCIA interface */
903
#define SH7750_PCR_A5TED_S    9
904
#define SH7750_PCR_A6TED      0x01C0        /* Area 6 Address-OE\/WE\ Assertion Delay */
905
#define SH7750_PCR_A6TED_S    6
906

    
907
#define SH7750_PCR_TED_0WS    0        /* 0 Waits inserted */
908
#define SH7750_PCR_TED_1WS    1        /* 1 Waits inserted */
909
#define SH7750_PCR_TED_2WS    2        /* 2 Waits inserted */
910
#define SH7750_PCR_TED_3WS    3        /* 3 Waits inserted */
911
#define SH7750_PCR_TED_6WS    4        /* 6 Waits inserted */
912
#define SH7750_PCR_TED_9WS    5        /* 9 Waits inserted */
913
#define SH7750_PCR_TED_12WS   6        /* 12 Waits inserted */
914
#define SH7750_PCR_TED_15WS   7        /* 15 Waits inserted */
915

    
916
#define SH7750_PCR_A5TEH      0x0038        /* Area 5 OE\/WE\ Negation Address delay,
917
                                           address hold delay time from OE\/WE\
918
                                           negation in a write on the connected
919
                                           PCMCIA interface */
920
#define SH7750_PCR_A5TEH_S    3
921

    
922
#define SH7750_PCR_A6TEH      0x0007        /* Area 6 OE\/WE\ Negation Address delay */
923
#define SH7750_PCR_A6TEH_S    0
924

    
925
#define SH7750_PCR_TEH_0WS    0        /* 0 Waits inserted */
926
#define SH7750_PCR_TEH_1WS    1        /* 1 Waits inserted */
927
#define SH7750_PCR_TEH_2WS    2        /* 2 Waits inserted */
928
#define SH7750_PCR_TEH_3WS    3        /* 3 Waits inserted */
929
#define SH7750_PCR_TEH_6WS    4        /* 6 Waits inserted */
930
#define SH7750_PCR_TEH_9WS    5        /* 9 Waits inserted */
931
#define SH7750_PCR_TEH_12WS   6        /* 12 Waits inserted */
932
#define SH7750_PCR_TEH_15WS   7        /* 15 Waits inserted */
933

    
934
/* Refresh Timer Control/Status Register (half) - RTSCR */
935
#define SH7750_RTCSR_REGOFS   0x80001C        /* offset */
936
#define SH7750_RTCSR          SH7750_P4_REG32(SH7750_RTCSR_REGOFS)
937
#define SH7750_RTCSR_A7       SH7750_A7_REG32(SH7750_RTCSR_REGOFS)
938

    
939
#define SH7750_RTCSR_KEY      0xA500        /* RTCSR write key */
940
#define SH7750_RTCSR_CMF      0x0080        /* Compare-Match Flag (indicates a
941
                                           match between the refresh timer
942
                                           counter and refresh time constant) */
943
#define SH7750_RTCSR_CMIE     0x0040        /* Compare-Match Interrupt Enable */
944
#define SH7750_RTCSR_CKS      0x0038        /* Refresh Counter Clock Selects */
945
#define SH7750_RTCSR_CKS_DIS          0x0000        /* Clock Input Disabled */
946
#define SH7750_RTCSR_CKS_CKIO_DIV4    0x0008        /* Bus Clock / 4 */
947
#define SH7750_RTCSR_CKS_CKIO_DIV16   0x0010        /* Bus Clock / 16 */
948
#define SH7750_RTCSR_CKS_CKIO_DIV64   0x0018        /* Bus Clock / 64 */
949
#define SH7750_RTCSR_CKS_CKIO_DIV256  0x0020        /* Bus Clock / 256 */
950
#define SH7750_RTCSR_CKS_CKIO_DIV1024 0x0028        /* Bus Clock / 1024 */
951
#define SH7750_RTCSR_CKS_CKIO_DIV2048 0x0030        /* Bus Clock / 2048 */
952
#define SH7750_RTCSR_CKS_CKIO_DIV4096 0x0038        /* Bus Clock / 4096 */
953

    
954
#define SH7750_RTCSR_OVF      0x0004        /* Refresh Count Overflow Flag */
955
#define SH7750_RTCSR_OVIE     0x0002        /* Refresh Count Overflow Interrupt
956
                                           Enable */
957
#define SH7750_RTCSR_LMTS     0x0001        /* Refresh Count Overflow Limit Select */
958
#define SH7750_RTCSR_LMTS_1024 0x0000        /* Count Limit is 1024 */
959
#define SH7750_RTCSR_LMTS_512  0x0001        /* Count Limit is 512 */
960

    
961
/* Refresh Timer Counter (half) - RTCNT */
962
#define SH7750_RTCNT_REGOFS   0x800020        /* offset */
963
#define SH7750_RTCNT          SH7750_P4_REG32(SH7750_RTCNT_REGOFS)
964
#define SH7750_RTCNT_A7       SH7750_A7_REG32(SH7750_RTCNT_REGOFS)
965

    
966
#define SH7750_RTCNT_KEY      0xA500        /* RTCNT write key */
967

    
968
/* Refresh Time Constant Register (half) - RTCOR */
969
#define SH7750_RTCOR_REGOFS   0x800024        /* offset */
970
#define SH7750_RTCOR          SH7750_P4_REG32(SH7750_RTCOR_REGOFS)
971
#define SH7750_RTCOR_A7       SH7750_A7_REG32(SH7750_RTCOR_REGOFS)
972

    
973
#define SH7750_RTCOR_KEY      0xA500        /* RTCOR write key */
974

    
975
/* Refresh Count Register (half) - RFCR */
976
#define SH7750_RFCR_REGOFS    0x800028        /* offset */
977
#define SH7750_RFCR           SH7750_P4_REG32(SH7750_RFCR_REGOFS)
978
#define SH7750_RFCR_A7        SH7750_A7_REG32(SH7750_RFCR_REGOFS)
979

    
980
#define SH7750_RFCR_KEY       0xA400        /* RFCR write key */
981

    
982
/*
983
 * Direct Memory Access Controller (DMAC)
984
 */
985

    
986
/* DMA Source Address Register - SAR0, SAR1, SAR2, SAR3 */
987
#define SH7750_SAR_REGOFS(n)  (0xA00000 + ((n)*16))        /* offset */
988
#define SH7750_SAR(n)         SH7750_P4_REG32(SH7750_SAR_REGOFS(n))
989
#define SH7750_SAR_A7(n)      SH7750_A7_REG32(SH7750_SAR_REGOFS(n))
990
#define SH7750_SAR0           SH7750_SAR(0)
991
#define SH7750_SAR1           SH7750_SAR(1)
992
#define SH7750_SAR2           SH7750_SAR(2)
993
#define SH7750_SAR3           SH7750_SAR(3)
994
#define SH7750_SAR0_A7        SH7750_SAR_A7(0)
995
#define SH7750_SAR1_A7        SH7750_SAR_A7(1)
996
#define SH7750_SAR2_A7        SH7750_SAR_A7(2)
997
#define SH7750_SAR3_A7        SH7750_SAR_A7(3)
998

    
999
/* DMA Destination Address Register - DAR0, DAR1, DAR2, DAR3 */
1000
#define SH7750_DAR_REGOFS(n)  (0xA00004 + ((n)*16))        /* offset */
1001
#define SH7750_DAR(n)         SH7750_P4_REG32(SH7750_DAR_REGOFS(n))
1002
#define SH7750_DAR_A7(n)      SH7750_A7_REG32(SH7750_DAR_REGOFS(n))
1003
#define SH7750_DAR0           SH7750_DAR(0)
1004
#define SH7750_DAR1           SH7750_DAR(1)
1005
#define SH7750_DAR2           SH7750_DAR(2)
1006
#define SH7750_DAR3           SH7750_DAR(3)
1007
#define SH7750_DAR0_A7        SH7750_DAR_A7(0)
1008
#define SH7750_DAR1_A7        SH7750_DAR_A7(1)
1009
#define SH7750_DAR2_A7        SH7750_DAR_A7(2)
1010
#define SH7750_DAR3_A7        SH7750_DAR_A7(3)
1011

    
1012
/* DMA Transfer Count Register - DMATCR0, DMATCR1, DMATCR2, DMATCR3 */
1013
#define SH7750_DMATCR_REGOFS(n)  (0xA00008 + ((n)*16))        /* offset */
1014
#define SH7750_DMATCR(n)      SH7750_P4_REG32(SH7750_DMATCR_REGOFS(n))
1015
#define SH7750_DMATCR_A7(n)   SH7750_A7_REG32(SH7750_DMATCR_REGOFS(n))
1016
#define SH7750_DMATCR0_P4     SH7750_DMATCR(0)
1017
#define SH7750_DMATCR1_P4     SH7750_DMATCR(1)
1018
#define SH7750_DMATCR2_P4     SH7750_DMATCR(2)
1019
#define SH7750_DMATCR3_P4     SH7750_DMATCR(3)
1020
#define SH7750_DMATCR0_A7     SH7750_DMATCR_A7(0)
1021
#define SH7750_DMATCR1_A7     SH7750_DMATCR_A7(1)
1022
#define SH7750_DMATCR2_A7     SH7750_DMATCR_A7(2)
1023
#define SH7750_DMATCR3_A7     SH7750_DMATCR_A7(3)
1024

    
1025
/* DMA Channel Control Register - CHCR0, CHCR1, CHCR2, CHCR3 */
1026
#define SH7750_CHCR_REGOFS(n)  (0xA0000C + ((n)*16))        /* offset */
1027
#define SH7750_CHCR(n)        SH7750_P4_REG32(SH7750_CHCR_REGOFS(n))
1028
#define SH7750_CHCR_A7(n)     SH7750_A7_REG32(SH7750_CHCR_REGOFS(n))
1029
#define SH7750_CHCR0          SH7750_CHCR(0)
1030
#define SH7750_CHCR1          SH7750_CHCR(1)
1031
#define SH7750_CHCR2          SH7750_CHCR(2)
1032
#define SH7750_CHCR3          SH7750_CHCR(3)
1033
#define SH7750_CHCR0_A7       SH7750_CHCR_A7(0)
1034
#define SH7750_CHCR1_A7       SH7750_CHCR_A7(1)
1035
#define SH7750_CHCR2_A7       SH7750_CHCR_A7(2)
1036
#define SH7750_CHCR3_A7       SH7750_CHCR_A7(3)
1037

    
1038
#define SH7750_CHCR_SSA       0xE0000000        /* Source Address Space Attribute */
1039
#define SH7750_CHCR_SSA_PCMCIA  0x00000000        /* Reserved in PCMCIA access */
1040
#define SH7750_CHCR_SSA_DYNBSZ  0x20000000        /* Dynamic Bus Sizing I/O space */
1041
#define SH7750_CHCR_SSA_IO8     0x40000000        /* 8-bit I/O space */
1042
#define SH7750_CHCR_SSA_IO16    0x60000000        /* 16-bit I/O space */
1043
#define SH7750_CHCR_SSA_CMEM8   0x80000000        /* 8-bit common memory space */
1044
#define SH7750_CHCR_SSA_CMEM16  0xA0000000        /* 16-bit common memory space */
1045
#define SH7750_CHCR_SSA_AMEM8   0xC0000000        /* 8-bit attribute memory space */
1046
#define SH7750_CHCR_SSA_AMEM16  0xE0000000        /* 16-bit attribute memory space */
1047

    
1048
#define SH7750_CHCR_STC       0x10000000        /* Source Address Wait Control Select,
1049
                                                   specifies CS5 or CS6 space wait
1050
                                                   control for PCMCIA access */
1051

    
1052
#define SH7750_CHCR_DSA       0x0E000000        /* Source Address Space Attribute */
1053
#define SH7750_CHCR_DSA_PCMCIA  0x00000000        /* Reserved in PCMCIA access */
1054
#define SH7750_CHCR_DSA_DYNBSZ  0x02000000        /* Dynamic Bus Sizing I/O space */
1055
#define SH7750_CHCR_DSA_IO8     0x04000000        /* 8-bit I/O space */
1056
#define SH7750_CHCR_DSA_IO16    0x06000000        /* 16-bit I/O space */
1057
#define SH7750_CHCR_DSA_CMEM8   0x08000000        /* 8-bit common memory space */
1058
#define SH7750_CHCR_DSA_CMEM16  0x0A000000        /* 16-bit common memory space */
1059
#define SH7750_CHCR_DSA_AMEM8   0x0C000000        /* 8-bit attribute memory space */
1060
#define SH7750_CHCR_DSA_AMEM16  0x0E000000        /* 16-bit attribute memory space */
1061

    
1062
#define SH7750_CHCR_DTC       0x01000000        /* Destination Address Wait Control
1063
                                                   Select, specifies CS5 or CS6
1064
                                                   space wait control for PCMCIA
1065
                                                   access */
1066

    
1067
#define SH7750_CHCR_DS        0x00080000        /* DREQ\ Select : */
1068
#define SH7750_CHCR_DS_LOWLVL 0x00000000        /*     Low Level Detection */
1069
#define SH7750_CHCR_DS_FALL   0x00080000        /*     Falling Edge Detection */
1070

    
1071
#define SH7750_CHCR_RL        0x00040000        /* Request Check Level: */
1072
#define SH7750_CHCR_RL_ACTH   0x00000000        /*     DRAK is an active high out */
1073
#define SH7750_CHCR_RL_ACTL   0x00040000        /*     DRAK is an active low out */
1074

    
1075
#define SH7750_CHCR_AM        0x00020000        /* Acknowledge Mode: */
1076
#define SH7750_CHCR_AM_RD     0x00000000        /*     DACK is output in read cycle */
1077
#define SH7750_CHCR_AM_WR     0x00020000        /*     DACK is output in write cycle */
1078

    
1079
#define SH7750_CHCR_AL        0x00010000        /* Acknowledge Level: */
1080
#define SH7750_CHCR_AL_ACTH   0x00000000        /*     DACK is an active high out */
1081
#define SH7750_CHCR_AL_ACTL   0x00010000        /*     DACK is an active low out */
1082

    
1083
#define SH7750_CHCR_DM        0x0000C000        /* Destination Address Mode: */
1084
#define SH7750_CHCR_DM_FIX    0x00000000        /*     Destination Addr Fixed */
1085
#define SH7750_CHCR_DM_INC    0x00004000        /*     Destination Addr Incremented */
1086
#define SH7750_CHCR_DM_DEC    0x00008000        /*     Destination Addr Decremented */
1087

    
1088
#define SH7750_CHCR_SM        0x00003000        /* Source Address Mode: */
1089
#define SH7750_CHCR_SM_FIX    0x00000000        /*     Source Addr Fixed */
1090
#define SH7750_CHCR_SM_INC    0x00001000        /*     Source Addr Incremented */
1091
#define SH7750_CHCR_SM_DEC    0x00002000        /*     Source Addr Decremented */
1092

    
1093
#define SH7750_CHCR_RS        0x00000F00        /* Request Source Select: */
1094
#define SH7750_CHCR_RS_ER_DA_EA_TO_EA   0x000        /* External Request, Dual Address
1095
                                                   Mode (External Addr Space->
1096
                                                   External Addr Space) */
1097
#define SH7750_CHCR_RS_ER_SA_EA_TO_ED   0x200        /* External Request, Single
1098
                                                   Address Mode (External Addr
1099
                                                   Space -> External Device) */
1100
#define SH7750_CHCR_RS_ER_SA_ED_TO_EA   0x300        /* External Request, Single
1101
                                                   Address Mode, (External
1102
                                                   Device -> External Addr
1103
                                                   Space) */
1104
#define SH7750_CHCR_RS_AR_EA_TO_EA      0x400        /* Auto-Request (External Addr
1105
                                                   Space -> External Addr Space) */
1106

    
1107
#define SH7750_CHCR_RS_AR_EA_TO_OCP     0x500        /* Auto-Request (External Addr
1108
                                                   Space -> On-chip Peripheral
1109
                                                   Module) */
1110
#define SH7750_CHCR_RS_AR_OCP_TO_EA     0x600        /* Auto-Request (On-chip
1111
                                                   Peripheral Module ->
1112
                                                   External Addr Space */
1113
#define SH7750_CHCR_RS_SCITX_EA_TO_SC   0x800        /* SCI Transmit-Data-Empty intr
1114
                                                   transfer request (external
1115
                                                   address space -> SCTDR1) */
1116
#define SH7750_CHCR_RS_SCIRX_SC_TO_EA   0x900        /* SCI Receive-Data-Full intr
1117
                                                   transfer request (SCRDR1 ->
1118
                                                   External Addr Space) */
1119
#define SH7750_CHCR_RS_SCIFTX_EA_TO_SC  0xA00        /* SCIF Transmit-Data-Empty intr
1120
                                                   transfer request (external
1121
                                                   address space -> SCFTDR1) */
1122
#define SH7750_CHCR_RS_SCIFRX_SC_TO_EA  0xB00        /* SCIF Receive-Data-Full intr
1123
                                                   transfer request (SCFRDR2 ->
1124
                                                   External Addr Space) */
1125
#define SH7750_CHCR_RS_TMU2_EA_TO_EA    0xC00        /* TMU Channel 2 (input capture
1126
                                                   interrupt), (external address
1127
                                                   space -> external address
1128
                                                   space) */
1129
#define SH7750_CHCR_RS_TMU2_EA_TO_OCP   0xD00        /* TMU Channel 2 (input capture
1130
                                                   interrupt), (external address
1131
                                                   space -> on-chip peripheral
1132
                                                   module) */
1133
#define SH7750_CHCR_RS_TMU2_OCP_TO_EA   0xE00        /* TMU Channel 2 (input capture
1134
                                                   interrupt), (on-chip
1135
                                                   peripheral module -> external
1136
                                                   address space) */
1137

    
1138
#define SH7750_CHCR_TM        0x00000080        /* Transmit mode: */
1139
#define SH7750_CHCR_TM_CSTEAL 0x00000000        /*     Cycle Steal Mode */
1140
#define SH7750_CHCR_TM_BURST  0x00000080        /*     Burst Mode */
1141

    
1142
#define SH7750_CHCR_TS        0x00000070        /* Transmit Size: */
1143
#define SH7750_CHCR_TS_QUAD   0x00000000        /*     Quadword Size (64 bits) */
1144
#define SH7750_CHCR_TS_BYTE   0x00000010        /*     Byte Size (8 bit) */
1145
#define SH7750_CHCR_TS_WORD   0x00000020        /*     Word Size (16 bit) */
1146
#define SH7750_CHCR_TS_LONG   0x00000030        /*     Longword Size (32 bit) */
1147
#define SH7750_CHCR_TS_BLOCK  0x00000040        /*     32-byte block transfer */
1148

    
1149
#define SH7750_CHCR_IE        0x00000004        /* Interrupt Enable */
1150
#define SH7750_CHCR_TE        0x00000002        /* Transfer End */
1151
#define SH7750_CHCR_DE        0x00000001        /* DMAC Enable */
1152

    
1153
/* DMA Operation Register - DMAOR */
1154
#define SH7750_DMAOR_REGOFS   0xA00040        /* offset */
1155
#define SH7750_DMAOR          SH7750_P4_REG32(SH7750_DMAOR_REGOFS)
1156
#define SH7750_DMAOR_A7       SH7750_A7_REG32(SH7750_DMAOR_REGOFS)
1157

    
1158
#define SH7750_DMAOR_DDT      0x00008000        /* On-Demand Data Transfer Mode */
1159

    
1160
#define SH7750_DMAOR_PR       0x00000300        /* Priority Mode: */
1161
#define SH7750_DMAOR_PR_0123  0x00000000        /*     CH0 > CH1 > CH2 > CH3 */
1162
#define SH7750_DMAOR_PR_0231  0x00000100        /*     CH0 > CH2 > CH3 > CH1 */
1163
#define SH7750_DMAOR_PR_2013  0x00000200        /*     CH2 > CH0 > CH1 > CH3 */
1164
#define SH7750_DMAOR_PR_RR    0x00000300        /*     Round-robin mode */
1165

    
1166
#define SH7750_DMAOR_COD      0x00000010        /* Check Overrun for DREQ\ */
1167
#define SH7750_DMAOR_AE       0x00000004        /* Address Error flag */
1168
#define SH7750_DMAOR_NMIF     0x00000002        /* NMI Flag */
1169
#define SH7750_DMAOR_DME      0x00000001        /* DMAC Master Enable */
1170

    
1171
/*
1172
 * I/O Ports
1173
 */
1174
/* Port Control Register A - PCTRA */
1175
#define SH7750_PCTRA_REGOFS   0x80002C        /* offset */
1176
#define SH7750_PCTRA          SH7750_P4_REG32(SH7750_PCTRA_REGOFS)
1177
#define SH7750_PCTRA_A7       SH7750_A7_REG32(SH7750_PCTRA_REGOFS)
1178

    
1179
#define SH7750_PCTRA_PBPUP(n) 0        /* Bit n is pulled up */
1180
#define SH7750_PCTRA_PBNPUP(n) (1 << ((n)*2+1))        /* Bit n is not pulled up */
1181
#define SH7750_PCTRA_PBINP(n) 0        /* Bit n is an input */
1182
#define SH7750_PCTRA_PBOUT(n) (1 << ((n)*2))        /* Bit n is an output */
1183

    
1184
/* Port Data Register A - PDTRA(half) */
1185
#define SH7750_PDTRA_REGOFS   0x800030        /* offset */
1186
#define SH7750_PDTRA          SH7750_P4_REG32(SH7750_PDTRA_REGOFS)
1187
#define SH7750_PDTRA_A7       SH7750_A7_REG32(SH7750_PDTRA_REGOFS)
1188

    
1189
#define SH7750_PDTRA_BIT(n) (1 << (n))
1190

    
1191
/* Port Control Register B - PCTRB */
1192
#define SH7750_PCTRB_REGOFS   0x800040        /* offset */
1193
#define SH7750_PCTRB          SH7750_P4_REG32(SH7750_PCTRB_REGOFS)
1194
#define SH7750_PCTRB_A7       SH7750_A7_REG32(SH7750_PCTRB_REGOFS)
1195

    
1196
#define SH7750_PCTRB_PBPUP(n) 0        /* Bit n is pulled up */
1197
#define SH7750_PCTRB_PBNPUP(n) (1 << ((n-16)*2+1))        /* Bit n is not pulled up */
1198
#define SH7750_PCTRB_PBINP(n) 0        /* Bit n is an input */
1199
#define SH7750_PCTRB_PBOUT(n) (1 << ((n-16)*2))        /* Bit n is an output */
1200

    
1201
/* Port Data Register B - PDTRB(half) */
1202
#define SH7750_PDTRB_REGOFS   0x800044        /* offset */
1203
#define SH7750_PDTRB          SH7750_P4_REG32(SH7750_PDTRB_REGOFS)
1204
#define SH7750_PDTRB_A7       SH7750_A7_REG32(SH7750_PDTRB_REGOFS)
1205

    
1206
#define SH7750_PDTRB_BIT(n) (1 << ((n)-16))
1207

    
1208
/* GPIO Interrupt Control Register - GPIOIC(half) */
1209
#define SH7750_GPIOIC_REGOFS  0x800048        /* offset */
1210
#define SH7750_GPIOIC         SH7750_P4_REG32(SH7750_GPIOIC_REGOFS)
1211
#define SH7750_GPIOIC_A7      SH7750_A7_REG32(SH7750_GPIOIC_REGOFS)
1212

    
1213
#define SH7750_GPIOIC_PTIREN(n) (1 << (n))        /* Port n is used as a GPIO int */
1214

    
1215
/*
1216
 * Interrupt Controller - INTC
1217
 */
1218
/* Interrupt Control Register - ICR (half) */
1219
#define SH7750_ICR_REGOFS     0xD00000        /* offset */
1220
#define SH7750_ICR            SH7750_P4_REG32(SH7750_ICR_REGOFS)
1221
#define SH7750_ICR_A7         SH7750_A7_REG32(SH7750_ICR_REGOFS)
1222

    
1223
#define SH7750_ICR_NMIL       0x8000        /* NMI Input Level */
1224
#define SH7750_ICR_MAI        0x4000        /* NMI Interrupt Mask */
1225

    
1226
#define SH7750_ICR_NMIB       0x0200        /* NMI Block Mode: */
1227
#define SH7750_ICR_NMIB_BLK   0x0000        /*   NMI requests held pending while
1228
                                           SR.BL bit is set to 1 */
1229
#define SH7750_ICR_NMIB_NBLK  0x0200        /*   NMI requests detected when SR.BL bit
1230
                                           set to 1 */
1231

    
1232
#define SH7750_ICR_NMIE       0x0100        /* NMI Edge Select: */
1233
#define SH7750_ICR_NMIE_FALL  0x0000        /*   Interrupt request detected on falling
1234
                                           edge of NMI input */
1235
#define SH7750_ICR_NMIE_RISE  0x0100        /*   Interrupt request detected on rising
1236
                                           edge of NMI input */
1237

    
1238
#define SH7750_ICR_IRLM       0x0080        /* IRL Pin Mode: */
1239
#define SH7750_ICR_IRLM_ENC   0x0000        /*   IRL\ pins used as a level-encoded
1240
                                           interrupt requests */
1241
#define SH7750_ICR_IRLM_RAW   0x0080        /*   IRL\ pins used as a four independent
1242
                                           interrupt requests */
1243

    
1244
/*
1245
 * User Break Controller registers
1246
 */
1247
#define SH7750_BARA           0x200000        /* Break address regiser A */
1248
#define SH7750_BAMRA          0x200004        /* Break address mask regiser A */
1249
#define SH7750_BBRA           0x200008        /* Break bus cycle regiser A */
1250
#define SH7750_BARB           0x20000c        /* Break address regiser B */
1251
#define SH7750_BAMRB          0x200010        /* Break address mask regiser B */
1252
#define SH7750_BBRB           0x200014        /* Break bus cycle regiser B */
1253
#define SH7750_BASRB          0x000018        /* Break ASID regiser B */
1254
#define SH7750_BDRB           0x200018        /* Break data regiser B */
1255
#define SH7750_BDMRB          0x20001c        /* Break data mask regiser B */
1256
#define SH7750_BRCR           0x200020        /* Break control register */
1257

    
1258
#define SH7750_BRCR_UDBE        0x0001        /* User break debug enable bit */
1259

    
1260
/*
1261
 * Missing in RTEMS, added for QEMU
1262
 */
1263
#define SH7750_BCR3_A7       0x1f800050
1264
#define SH7750_BCR4_A7       0x1e0a00f0
1265
#define SH7750_PRECHARGE0_A7 0x1f900088
1266
#define SH7750_PRECHARGE1_A7 0x1f940088
1267

    
1268
#endif