root / hw / serial.c @ 81174dae
History | View | Annotate | Download (24.7 kB)
| 1 |
/*
|
|---|---|
| 2 |
* QEMU 16550A UART emulation
|
| 3 |
*
|
| 4 |
* Copyright (c) 2003-2004 Fabrice Bellard
|
| 5 |
* Copyright (c) 2008 Citrix Systems, Inc.
|
| 6 |
*
|
| 7 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
| 8 |
* of this software and associated documentation files (the "Software"), to deal
|
| 9 |
* in the Software without restriction, including without limitation the rights
|
| 10 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
| 11 |
* copies of the Software, and to permit persons to whom the Software is
|
| 12 |
* furnished to do so, subject to the following conditions:
|
| 13 |
*
|
| 14 |
* The above copyright notice and this permission notice shall be included in
|
| 15 |
* all copies or substantial portions of the Software.
|
| 16 |
*
|
| 17 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
| 18 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
| 19 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
| 20 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
| 21 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
| 22 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
| 23 |
* THE SOFTWARE.
|
| 24 |
*/
|
| 25 |
#include "hw.h" |
| 26 |
#include "qemu-char.h" |
| 27 |
#include "isa.h" |
| 28 |
#include "pc.h" |
| 29 |
#include "qemu-timer.h" |
| 30 |
|
| 31 |
//#define DEBUG_SERIAL
|
| 32 |
|
| 33 |
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
| 34 |
|
| 35 |
#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
| 36 |
#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
| 37 |
#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
| 38 |
#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
| 39 |
|
| 40 |
#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
| 41 |
#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
| 42 |
|
| 43 |
#define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
| 44 |
#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
| 45 |
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
| 46 |
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
| 47 |
#define UART_IIR_CTI 0x0C /* Character Timeout Indication */ |
| 48 |
|
| 49 |
#define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */ |
| 50 |
#define UART_IIR_FE 0xC0 /* Fifo enabled */ |
| 51 |
|
| 52 |
/*
|
| 53 |
* These are the definitions for the Modem Control Register
|
| 54 |
*/
|
| 55 |
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
| 56 |
#define UART_MCR_OUT2 0x08 /* Out2 complement */ |
| 57 |
#define UART_MCR_OUT1 0x04 /* Out1 complement */ |
| 58 |
#define UART_MCR_RTS 0x02 /* RTS complement */ |
| 59 |
#define UART_MCR_DTR 0x01 /* DTR complement */ |
| 60 |
|
| 61 |
/*
|
| 62 |
* These are the definitions for the Modem Status Register
|
| 63 |
*/
|
| 64 |
#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
| 65 |
#define UART_MSR_RI 0x40 /* Ring Indicator */ |
| 66 |
#define UART_MSR_DSR 0x20 /* Data Set Ready */ |
| 67 |
#define UART_MSR_CTS 0x10 /* Clear to Send */ |
| 68 |
#define UART_MSR_DDCD 0x08 /* Delta DCD */ |
| 69 |
#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
| 70 |
#define UART_MSR_DDSR 0x02 /* Delta DSR */ |
| 71 |
#define UART_MSR_DCTS 0x01 /* Delta CTS */ |
| 72 |
#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ |
| 73 |
|
| 74 |
#define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
| 75 |
#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
| 76 |
#define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
| 77 |
#define UART_LSR_FE 0x08 /* Frame error indicator */ |
| 78 |
#define UART_LSR_PE 0x04 /* Parity error indicator */ |
| 79 |
#define UART_LSR_OE 0x02 /* Overrun error indicator */ |
| 80 |
#define UART_LSR_DR 0x01 /* Receiver data ready */ |
| 81 |
#define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */ |
| 82 |
|
| 83 |
/* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
|
| 84 |
|
| 85 |
#define UART_FCR_ITL_1 0x00 /* 1 byte ITL */ |
| 86 |
#define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */ |
| 87 |
#define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */ |
| 88 |
#define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */ |
| 89 |
|
| 90 |
#define UART_FCR_DMS 0x08 /* DMA Mode Select */ |
| 91 |
#define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */ |
| 92 |
#define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */ |
| 93 |
#define UART_FCR_FE 0x01 /* FIFO Enable */ |
| 94 |
|
| 95 |
#define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */ |
| 96 |
|
| 97 |
#define XMIT_FIFO 0 |
| 98 |
#define RECV_FIFO 1 |
| 99 |
#define MAX_XMIT_RETRY 4 |
| 100 |
|
| 101 |
struct SerialFIFO {
|
| 102 |
uint8_t data[UART_FIFO_LENGTH]; |
| 103 |
uint8_t count; |
| 104 |
uint8_t itl; /* Interrupt Trigger Level */
|
| 105 |
uint8_t tail; |
| 106 |
uint8_t head; |
| 107 |
} typedef SerialFIFO;
|
| 108 |
|
| 109 |
struct SerialState {
|
| 110 |
uint16_t divider; |
| 111 |
uint8_t rbr; /* receive register */
|
| 112 |
uint8_t thr; /* transmit holding register */
|
| 113 |
uint8_t tsr; /* transmit shift register */
|
| 114 |
uint8_t ier; |
| 115 |
uint8_t iir; /* read only */
|
| 116 |
uint8_t lcr; |
| 117 |
uint8_t mcr; |
| 118 |
uint8_t lsr; /* read only */
|
| 119 |
uint8_t msr; /* read only */
|
| 120 |
uint8_t scr; |
| 121 |
uint8_t fcr; |
| 122 |
/* NOTE: this hidden state is necessary for tx irq generation as
|
| 123 |
it can be reset while reading iir */
|
| 124 |
int thr_ipending;
|
| 125 |
qemu_irq irq; |
| 126 |
CharDriverState *chr; |
| 127 |
int last_break_enable;
|
| 128 |
target_phys_addr_t base; |
| 129 |
int it_shift;
|
| 130 |
int baudbase;
|
| 131 |
int tsr_retry;
|
| 132 |
|
| 133 |
uint64_t last_xmit_ts; /* Time when the last byte was successfully sent out of the tsr */
|
| 134 |
SerialFIFO recv_fifo; |
| 135 |
SerialFIFO xmit_fifo; |
| 136 |
|
| 137 |
struct QEMUTimer *fifo_timeout_timer;
|
| 138 |
int timeout_ipending; /* timeout interrupt pending state */ |
| 139 |
struct QEMUTimer *transmit_timer;
|
| 140 |
|
| 141 |
|
| 142 |
uint64_t char_transmit_time; /* time to transmit a char in ticks*/
|
| 143 |
int poll_msl;
|
| 144 |
|
| 145 |
struct QEMUTimer *modem_status_poll;
|
| 146 |
}; |
| 147 |
|
| 148 |
static void serial_receive1(void *opaque, const uint8_t *buf, int size); |
| 149 |
|
| 150 |
static void fifo_clear(SerialState *s, int fifo) |
| 151 |
{
|
| 152 |
SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; |
| 153 |
memset(f->data, 0, UART_FIFO_LENGTH);
|
| 154 |
f->count = 0;
|
| 155 |
f->head = 0;
|
| 156 |
f->tail = 0;
|
| 157 |
} |
| 158 |
|
| 159 |
static int fifo_put(SerialState *s, int fifo, uint8_t chr) |
| 160 |
{
|
| 161 |
SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; |
| 162 |
|
| 163 |
f->data[f->head++] = chr; |
| 164 |
|
| 165 |
if (f->head == UART_FIFO_LENGTH)
|
| 166 |
f->head = 0;
|
| 167 |
f->count++; |
| 168 |
|
| 169 |
return 1; |
| 170 |
} |
| 171 |
|
| 172 |
static uint8_t fifo_get(SerialState *s, int fifo) |
| 173 |
{
|
| 174 |
SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; |
| 175 |
uint8_t c; |
| 176 |
|
| 177 |
if(f->count == 0) |
| 178 |
return 0; |
| 179 |
|
| 180 |
c = f->data[f->tail++]; |
| 181 |
if (f->tail == UART_FIFO_LENGTH)
|
| 182 |
f->tail = 0;
|
| 183 |
f->count--; |
| 184 |
|
| 185 |
return c;
|
| 186 |
} |
| 187 |
|
| 188 |
static void serial_update_irq(SerialState *s) |
| 189 |
{
|
| 190 |
uint8_t tmp_iir = UART_IIR_NO_INT; |
| 191 |
|
| 192 |
if (!s->ier) {
|
| 193 |
qemu_irq_lower(s->irq); |
| 194 |
return;
|
| 195 |
} |
| 196 |
|
| 197 |
if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
|
| 198 |
tmp_iir = UART_IIR_RLSI; |
| 199 |
} else if (s->timeout_ipending) { |
| 200 |
tmp_iir = UART_IIR_CTI; |
| 201 |
} else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR)) { |
| 202 |
if (!(s->fcr & UART_FCR_FE)) {
|
| 203 |
tmp_iir = UART_IIR_RDI; |
| 204 |
} else if (s->recv_fifo.count >= s->recv_fifo.itl) { |
| 205 |
tmp_iir = UART_IIR_RDI; |
| 206 |
} |
| 207 |
} else if ((s->ier & UART_IER_THRI) && s->thr_ipending) { |
| 208 |
tmp_iir = UART_IIR_THRI; |
| 209 |
} else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) { |
| 210 |
tmp_iir = UART_IIR_MSI; |
| 211 |
} |
| 212 |
|
| 213 |
s->iir = tmp_iir | (s->iir & 0xF0);
|
| 214 |
|
| 215 |
if (tmp_iir != UART_IIR_NO_INT) {
|
| 216 |
qemu_irq_raise(s->irq); |
| 217 |
} else {
|
| 218 |
qemu_irq_lower(s->irq); |
| 219 |
} |
| 220 |
} |
| 221 |
|
| 222 |
static void serial_update_parameters(SerialState *s) |
| 223 |
{
|
| 224 |
int speed, parity, data_bits, stop_bits, frame_size;
|
| 225 |
QEMUSerialSetParams ssp; |
| 226 |
|
| 227 |
if (s->divider == 0) |
| 228 |
return;
|
| 229 |
|
| 230 |
frame_size = 1;
|
| 231 |
if (s->lcr & 0x08) { |
| 232 |
if (s->lcr & 0x10) |
| 233 |
parity = 'E';
|
| 234 |
else
|
| 235 |
parity = 'O';
|
| 236 |
} else {
|
| 237 |
parity = 'N';
|
| 238 |
frame_size = 0;
|
| 239 |
} |
| 240 |
if (s->lcr & 0x04) |
| 241 |
stop_bits = 2;
|
| 242 |
else
|
| 243 |
stop_bits = 1;
|
| 244 |
|
| 245 |
data_bits = (s->lcr & 0x03) + 5; |
| 246 |
frame_size += data_bits + stop_bits; |
| 247 |
speed = s->baudbase / s->divider; |
| 248 |
ssp.speed = speed; |
| 249 |
ssp.parity = parity; |
| 250 |
ssp.data_bits = data_bits; |
| 251 |
ssp.stop_bits = stop_bits; |
| 252 |
s->char_transmit_time = (ticks_per_sec / speed) * frame_size; |
| 253 |
qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
| 254 |
#if 0
|
| 255 |
printf("speed=%d parity=%c data=%d stop=%d\n",
|
| 256 |
speed, parity, data_bits, stop_bits);
|
| 257 |
#endif
|
| 258 |
} |
| 259 |
|
| 260 |
static void serial_update_msl(SerialState *s) |
| 261 |
{
|
| 262 |
uint8_t omsr; |
| 263 |
int flags;
|
| 264 |
|
| 265 |
qemu_del_timer(s->modem_status_poll); |
| 266 |
|
| 267 |
if (qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
|
| 268 |
s->poll_msl = -1;
|
| 269 |
return;
|
| 270 |
} |
| 271 |
|
| 272 |
omsr = s->msr; |
| 273 |
|
| 274 |
s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS; |
| 275 |
s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR; |
| 276 |
s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD; |
| 277 |
s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI; |
| 278 |
|
| 279 |
if (s->msr != omsr) {
|
| 280 |
/* Set delta bits */
|
| 281 |
s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4)); |
| 282 |
/* UART_MSR_TERI only if change was from 1 -> 0 */
|
| 283 |
if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
|
| 284 |
s->msr &= ~UART_MSR_TERI; |
| 285 |
serial_update_irq(s); |
| 286 |
} |
| 287 |
|
| 288 |
/* The real 16550A apparently has a 250ns response latency to line status changes.
|
| 289 |
We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
|
| 290 |
|
| 291 |
if (s->poll_msl)
|
| 292 |
qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + ticks_per_sec / 100);
|
| 293 |
} |
| 294 |
|
| 295 |
static void serial_xmit(void *opaque) |
| 296 |
{
|
| 297 |
SerialState *s = opaque; |
| 298 |
uint64_t new_xmit_ts = qemu_get_clock(vm_clock); |
| 299 |
|
| 300 |
if (s->tsr_retry <= 0) { |
| 301 |
if (s->fcr & UART_FCR_FE) {
|
| 302 |
s->tsr = fifo_get(s,XMIT_FIFO); |
| 303 |
if (!s->xmit_fifo.count)
|
| 304 |
s->lsr |= UART_LSR_THRE; |
| 305 |
} else {
|
| 306 |
s->tsr = s->thr; |
| 307 |
s->lsr |= UART_LSR_THRE; |
| 308 |
} |
| 309 |
} |
| 310 |
|
| 311 |
if (s->mcr & UART_MCR_LOOP) {
|
| 312 |
/* in loopback mode, say that we just received a char */
|
| 313 |
serial_receive1(s, &s->tsr, 1);
|
| 314 |
} else if (qemu_chr_write(s->chr, &s->tsr, 1) != 1) { |
| 315 |
if ((s->tsr_retry > 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) { |
| 316 |
s->tsr_retry++; |
| 317 |
qemu_mod_timer(s->transmit_timer, new_xmit_ts + s->char_transmit_time); |
| 318 |
return;
|
| 319 |
} else if (s->poll_msl < 0) { |
| 320 |
/* If we exceed MAX_XMIT_RETRY and the backend is not a real serial port, then
|
| 321 |
drop any further failed writes instantly, until we get one that goes through.
|
| 322 |
This is to prevent guests that log to unconnected pipes or pty's from stalling. */
|
| 323 |
s->tsr_retry = -1;
|
| 324 |
} |
| 325 |
} |
| 326 |
else {
|
| 327 |
s->tsr_retry = 0;
|
| 328 |
} |
| 329 |
|
| 330 |
s->last_xmit_ts = qemu_get_clock(vm_clock); |
| 331 |
if (!(s->lsr & UART_LSR_THRE))
|
| 332 |
qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time); |
| 333 |
|
| 334 |
if (s->lsr & UART_LSR_THRE) {
|
| 335 |
s->lsr |= UART_LSR_TEMT; |
| 336 |
s->thr_ipending = 1;
|
| 337 |
serial_update_irq(s); |
| 338 |
} |
| 339 |
} |
| 340 |
|
| 341 |
|
| 342 |
static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
| 343 |
{
|
| 344 |
SerialState *s = opaque; |
| 345 |
|
| 346 |
addr &= 7;
|
| 347 |
#ifdef DEBUG_SERIAL
|
| 348 |
printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
|
| 349 |
#endif
|
| 350 |
switch(addr) {
|
| 351 |
default:
|
| 352 |
case 0: |
| 353 |
if (s->lcr & UART_LCR_DLAB) {
|
| 354 |
s->divider = (s->divider & 0xff00) | val;
|
| 355 |
serial_update_parameters(s); |
| 356 |
} else {
|
| 357 |
s->thr = (uint8_t) val; |
| 358 |
if(s->fcr & UART_FCR_FE) {
|
| 359 |
fifo_put(s, XMIT_FIFO, s->thr); |
| 360 |
s->thr_ipending = 0;
|
| 361 |
s->lsr &= ~UART_LSR_TEMT; |
| 362 |
s->lsr &= ~UART_LSR_THRE; |
| 363 |
serial_update_irq(s); |
| 364 |
} else {
|
| 365 |
s->thr_ipending = 0;
|
| 366 |
s->lsr &= ~UART_LSR_THRE; |
| 367 |
serial_update_irq(s); |
| 368 |
} |
| 369 |
serial_xmit(s); |
| 370 |
} |
| 371 |
break;
|
| 372 |
case 1: |
| 373 |
if (s->lcr & UART_LCR_DLAB) {
|
| 374 |
s->divider = (s->divider & 0x00ff) | (val << 8); |
| 375 |
serial_update_parameters(s); |
| 376 |
} else {
|
| 377 |
s->ier = val & 0x0f;
|
| 378 |
/* If the backend device is a real serial port, turn polling of the modem
|
| 379 |
status lines on physical port on or off depending on UART_IER_MSI state */
|
| 380 |
if (s->poll_msl >= 0) { |
| 381 |
if (s->ier & UART_IER_MSI) {
|
| 382 |
s->poll_msl = 1;
|
| 383 |
serial_update_msl(s); |
| 384 |
} else {
|
| 385 |
qemu_del_timer(s->modem_status_poll); |
| 386 |
s->poll_msl = 0;
|
| 387 |
} |
| 388 |
} |
| 389 |
if (s->lsr & UART_LSR_THRE) {
|
| 390 |
s->thr_ipending = 1;
|
| 391 |
serial_update_irq(s); |
| 392 |
} |
| 393 |
} |
| 394 |
break;
|
| 395 |
case 2: |
| 396 |
val = val & 0xFF;
|
| 397 |
|
| 398 |
if (s->fcr == val)
|
| 399 |
break;
|
| 400 |
|
| 401 |
/* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
|
| 402 |
if ((val ^ s->fcr) & UART_FCR_FE)
|
| 403 |
val |= UART_FCR_XFR | UART_FCR_RFR; |
| 404 |
|
| 405 |
/* FIFO clear */
|
| 406 |
|
| 407 |
if (val & UART_FCR_RFR) {
|
| 408 |
qemu_del_timer(s->fifo_timeout_timer); |
| 409 |
s->timeout_ipending=0;
|
| 410 |
fifo_clear(s,RECV_FIFO); |
| 411 |
} |
| 412 |
|
| 413 |
if (val & UART_FCR_XFR) {
|
| 414 |
fifo_clear(s,XMIT_FIFO); |
| 415 |
} |
| 416 |
|
| 417 |
if (val & UART_FCR_FE) {
|
| 418 |
s->iir |= UART_IIR_FE; |
| 419 |
/* Set RECV_FIFO trigger Level */
|
| 420 |
switch (val & 0xC0) { |
| 421 |
case UART_FCR_ITL_1:
|
| 422 |
s->recv_fifo.itl = 1;
|
| 423 |
break;
|
| 424 |
case UART_FCR_ITL_2:
|
| 425 |
s->recv_fifo.itl = 4;
|
| 426 |
break;
|
| 427 |
case UART_FCR_ITL_3:
|
| 428 |
s->recv_fifo.itl = 8;
|
| 429 |
break;
|
| 430 |
case UART_FCR_ITL_4:
|
| 431 |
s->recv_fifo.itl = 14;
|
| 432 |
break;
|
| 433 |
} |
| 434 |
} else
|
| 435 |
s->iir &= ~UART_IIR_FE; |
| 436 |
|
| 437 |
/* Set fcr - or at least the bits in it that are supposed to "stick" */
|
| 438 |
s->fcr = val & 0xC9;
|
| 439 |
serial_update_irq(s); |
| 440 |
break;
|
| 441 |
case 3: |
| 442 |
{
|
| 443 |
int break_enable;
|
| 444 |
s->lcr = val; |
| 445 |
serial_update_parameters(s); |
| 446 |
break_enable = (val >> 6) & 1; |
| 447 |
if (break_enable != s->last_break_enable) {
|
| 448 |
s->last_break_enable = break_enable; |
| 449 |
qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, |
| 450 |
&break_enable); |
| 451 |
} |
| 452 |
} |
| 453 |
break;
|
| 454 |
case 4: |
| 455 |
{
|
| 456 |
int flags;
|
| 457 |
int old_mcr = s->mcr;
|
| 458 |
s->mcr = val & 0x1f;
|
| 459 |
if (val & UART_MCR_LOOP)
|
| 460 |
break;
|
| 461 |
|
| 462 |
if (s->poll_msl >= 0 && old_mcr != s->mcr) { |
| 463 |
|
| 464 |
qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags); |
| 465 |
|
| 466 |
flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR); |
| 467 |
|
| 468 |
if (val & UART_MCR_RTS)
|
| 469 |
flags |= CHR_TIOCM_RTS; |
| 470 |
if (val & UART_MCR_DTR)
|
| 471 |
flags |= CHR_TIOCM_DTR; |
| 472 |
|
| 473 |
qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags); |
| 474 |
/* Update the modem status after a one-character-send wait-time, since there may be a response
|
| 475 |
from the device/computer at the other end of the serial line */
|
| 476 |
qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + s->char_transmit_time); |
| 477 |
} |
| 478 |
} |
| 479 |
break;
|
| 480 |
case 5: |
| 481 |
break;
|
| 482 |
case 6: |
| 483 |
break;
|
| 484 |
case 7: |
| 485 |
s->scr = val; |
| 486 |
break;
|
| 487 |
} |
| 488 |
} |
| 489 |
|
| 490 |
static uint32_t serial_ioport_read(void *opaque, uint32_t addr) |
| 491 |
{
|
| 492 |
SerialState *s = opaque; |
| 493 |
uint32_t ret; |
| 494 |
|
| 495 |
addr &= 7;
|
| 496 |
switch(addr) {
|
| 497 |
default:
|
| 498 |
case 0: |
| 499 |
if (s->lcr & UART_LCR_DLAB) {
|
| 500 |
ret = s->divider & 0xff;
|
| 501 |
} else {
|
| 502 |
if(s->fcr & UART_FCR_FE) {
|
| 503 |
ret = fifo_get(s,RECV_FIFO); |
| 504 |
if (s->recv_fifo.count == 0) |
| 505 |
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
| 506 |
else
|
| 507 |
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
|
| 508 |
s->timeout_ipending = 0;
|
| 509 |
} else {
|
| 510 |
ret = s->rbr; |
| 511 |
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
| 512 |
} |
| 513 |
serial_update_irq(s); |
| 514 |
if (!(s->mcr & UART_MCR_LOOP)) {
|
| 515 |
/* in loopback mode, don't receive any data */
|
| 516 |
qemu_chr_accept_input(s->chr); |
| 517 |
} |
| 518 |
} |
| 519 |
break;
|
| 520 |
case 1: |
| 521 |
if (s->lcr & UART_LCR_DLAB) {
|
| 522 |
ret = (s->divider >> 8) & 0xff; |
| 523 |
} else {
|
| 524 |
ret = s->ier; |
| 525 |
} |
| 526 |
break;
|
| 527 |
case 2: |
| 528 |
ret = s->iir; |
| 529 |
s->thr_ipending = 0;
|
| 530 |
serial_update_irq(s); |
| 531 |
break;
|
| 532 |
case 3: |
| 533 |
ret = s->lcr; |
| 534 |
break;
|
| 535 |
case 4: |
| 536 |
ret = s->mcr; |
| 537 |
break;
|
| 538 |
case 5: |
| 539 |
ret = s->lsr; |
| 540 |
/* Clear break interrupt */
|
| 541 |
if (s->lsr & UART_LSR_BI) {
|
| 542 |
s->lsr &= ~UART_LSR_BI; |
| 543 |
serial_update_irq(s); |
| 544 |
} |
| 545 |
break;
|
| 546 |
case 6: |
| 547 |
if (s->mcr & UART_MCR_LOOP) {
|
| 548 |
/* in loopback, the modem output pins are connected to the
|
| 549 |
inputs */
|
| 550 |
ret = (s->mcr & 0x0c) << 4; |
| 551 |
ret |= (s->mcr & 0x02) << 3; |
| 552 |
ret |= (s->mcr & 0x01) << 5; |
| 553 |
} else {
|
| 554 |
if (s->poll_msl >= 0) |
| 555 |
serial_update_msl(s); |
| 556 |
ret = s->msr; |
| 557 |
/* Clear delta bits & msr int after read, if they were set */
|
| 558 |
if (s->msr & UART_MSR_ANY_DELTA) {
|
| 559 |
s->msr &= 0xF0;
|
| 560 |
serial_update_irq(s); |
| 561 |
} |
| 562 |
} |
| 563 |
break;
|
| 564 |
case 7: |
| 565 |
ret = s->scr; |
| 566 |
break;
|
| 567 |
} |
| 568 |
#ifdef DEBUG_SERIAL
|
| 569 |
printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
|
| 570 |
#endif
|
| 571 |
return ret;
|
| 572 |
} |
| 573 |
|
| 574 |
static int serial_can_receive(SerialState *s) |
| 575 |
{
|
| 576 |
if(s->fcr & UART_FCR_FE) {
|
| 577 |
if(s->recv_fifo.count < UART_FIFO_LENGTH)
|
| 578 |
/* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is
|
| 579 |
advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond,
|
| 580 |
effectively overriding the ITL that the guest has set. */
|
| 581 |
return (s->recv_fifo.count <= s->recv_fifo.itl) ? s->recv_fifo.itl - s->recv_fifo.count : 1; |
| 582 |
else
|
| 583 |
return 0; |
| 584 |
} else {
|
| 585 |
return !(s->lsr & UART_LSR_DR);
|
| 586 |
} |
| 587 |
} |
| 588 |
|
| 589 |
static void serial_receive_break(SerialState *s) |
| 590 |
{
|
| 591 |
s->rbr = 0;
|
| 592 |
s->lsr |= UART_LSR_BI | UART_LSR_DR; |
| 593 |
serial_update_irq(s); |
| 594 |
} |
| 595 |
|
| 596 |
/* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
|
| 597 |
static void fifo_timeout_int (void *opaque) { |
| 598 |
SerialState *s = opaque; |
| 599 |
if (s->recv_fifo.count) {
|
| 600 |
s->timeout_ipending = 1;
|
| 601 |
serial_update_irq(s); |
| 602 |
} |
| 603 |
} |
| 604 |
|
| 605 |
static int serial_can_receive1(void *opaque) |
| 606 |
{
|
| 607 |
SerialState *s = opaque; |
| 608 |
return serial_can_receive(s);
|
| 609 |
} |
| 610 |
|
| 611 |
static void serial_receive1(void *opaque, const uint8_t *buf, int size) |
| 612 |
{
|
| 613 |
SerialState *s = opaque; |
| 614 |
if(s->fcr & UART_FCR_FE) {
|
| 615 |
int i;
|
| 616 |
for (i = 0; i < size; i++) { |
| 617 |
fifo_put(s, RECV_FIFO, buf[i]); |
| 618 |
} |
| 619 |
s->lsr |= UART_LSR_DR; |
| 620 |
/* call the timeout receive callback in 4 char transmit time */
|
| 621 |
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
|
| 622 |
} else {
|
| 623 |
s->rbr = buf[0];
|
| 624 |
s->lsr |= UART_LSR_DR; |
| 625 |
} |
| 626 |
serial_update_irq(s); |
| 627 |
} |
| 628 |
|
| 629 |
static void serial_event(void *opaque, int event) |
| 630 |
{
|
| 631 |
SerialState *s = opaque; |
| 632 |
#ifdef DEBUG_SERIAL
|
| 633 |
printf("serial: event %x\n", event);
|
| 634 |
#endif
|
| 635 |
if (event == CHR_EVENT_BREAK)
|
| 636 |
serial_receive_break(s); |
| 637 |
} |
| 638 |
|
| 639 |
static void serial_save(QEMUFile *f, void *opaque) |
| 640 |
{
|
| 641 |
SerialState *s = opaque; |
| 642 |
|
| 643 |
qemu_put_be16s(f,&s->divider); |
| 644 |
qemu_put_8s(f,&s->rbr); |
| 645 |
qemu_put_8s(f,&s->ier); |
| 646 |
qemu_put_8s(f,&s->iir); |
| 647 |
qemu_put_8s(f,&s->lcr); |
| 648 |
qemu_put_8s(f,&s->mcr); |
| 649 |
qemu_put_8s(f,&s->lsr); |
| 650 |
qemu_put_8s(f,&s->msr); |
| 651 |
qemu_put_8s(f,&s->scr); |
| 652 |
qemu_put_8s(f,&s->fcr); |
| 653 |
} |
| 654 |
|
| 655 |
static int serial_load(QEMUFile *f, void *opaque, int version_id) |
| 656 |
{
|
| 657 |
SerialState *s = opaque; |
| 658 |
uint8_t fcr = 0;
|
| 659 |
|
| 660 |
if(version_id > 3) |
| 661 |
return -EINVAL;
|
| 662 |
|
| 663 |
if (version_id >= 2) |
| 664 |
qemu_get_be16s(f, &s->divider); |
| 665 |
else
|
| 666 |
s->divider = qemu_get_byte(f); |
| 667 |
qemu_get_8s(f,&s->rbr); |
| 668 |
qemu_get_8s(f,&s->ier); |
| 669 |
qemu_get_8s(f,&s->iir); |
| 670 |
qemu_get_8s(f,&s->lcr); |
| 671 |
qemu_get_8s(f,&s->mcr); |
| 672 |
qemu_get_8s(f,&s->lsr); |
| 673 |
qemu_get_8s(f,&s->msr); |
| 674 |
qemu_get_8s(f,&s->scr); |
| 675 |
|
| 676 |
if (version_id >= 3) |
| 677 |
qemu_get_8s(f,&fcr); |
| 678 |
|
| 679 |
/* Initialize fcr via setter to perform essential side-effects */
|
| 680 |
serial_ioport_write(s, 0x02, fcr);
|
| 681 |
return 0; |
| 682 |
} |
| 683 |
|
| 684 |
static void serial_reset(void *opaque) |
| 685 |
{
|
| 686 |
SerialState *s = opaque; |
| 687 |
|
| 688 |
s->rbr = 0;
|
| 689 |
s->ier = 0;
|
| 690 |
s->iir = UART_IIR_NO_INT; |
| 691 |
s->lcr = 0;
|
| 692 |
s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
| 693 |
s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; |
| 694 |
/* Default to 9600 baud, no parity, one stop bit */
|
| 695 |
s->divider = 0x0C;
|
| 696 |
s->mcr = UART_MCR_OUT2; |
| 697 |
s->scr = 0;
|
| 698 |
s->tsr_retry = 0;
|
| 699 |
s->char_transmit_time = (ticks_per_sec / 9600) * 9; |
| 700 |
s->poll_msl = 0;
|
| 701 |
|
| 702 |
fifo_clear(s,RECV_FIFO); |
| 703 |
fifo_clear(s,XMIT_FIFO); |
| 704 |
|
| 705 |
s->last_xmit_ts = qemu_get_clock(vm_clock); |
| 706 |
|
| 707 |
s->thr_ipending = 0;
|
| 708 |
s->last_break_enable = 0;
|
| 709 |
qemu_irq_lower(s->irq); |
| 710 |
} |
| 711 |
|
| 712 |
static void serial_init_core(SerialState *s, qemu_irq irq, int baudbase, |
| 713 |
CharDriverState *chr) |
| 714 |
{
|
| 715 |
s->irq = irq; |
| 716 |
s->baudbase = baudbase; |
| 717 |
s->chr = chr; |
| 718 |
|
| 719 |
s->modem_status_poll = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_update_msl, s); |
| 720 |
|
| 721 |
s->fifo_timeout_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s); |
| 722 |
s->transmit_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_xmit, s); |
| 723 |
|
| 724 |
qemu_register_reset(serial_reset, s); |
| 725 |
serial_reset(s); |
| 726 |
|
| 727 |
} |
| 728 |
|
| 729 |
/* If fd is zero, it means that the serial device uses the console */
|
| 730 |
SerialState *serial_init(int base, qemu_irq irq, int baudbase, |
| 731 |
CharDriverState *chr) |
| 732 |
{
|
| 733 |
SerialState *s; |
| 734 |
|
| 735 |
s = qemu_mallocz(sizeof(SerialState));
|
| 736 |
if (!s)
|
| 737 |
return NULL; |
| 738 |
|
| 739 |
serial_init_core(s, irq, baudbase, chr); |
| 740 |
|
| 741 |
register_savevm("serial", base, 3, serial_save, serial_load, s); |
| 742 |
|
| 743 |
register_ioport_write(base, 8, 1, serial_ioport_write, s); |
| 744 |
register_ioport_read(base, 8, 1, serial_ioport_read, s); |
| 745 |
qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1, |
| 746 |
serial_event, s); |
| 747 |
return s;
|
| 748 |
} |
| 749 |
|
| 750 |
/* Memory mapped interface */
|
| 751 |
uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
|
| 752 |
{
|
| 753 |
SerialState *s = opaque; |
| 754 |
|
| 755 |
return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF; |
| 756 |
} |
| 757 |
|
| 758 |
void serial_mm_writeb (void *opaque, |
| 759 |
target_phys_addr_t addr, uint32_t value) |
| 760 |
{
|
| 761 |
SerialState *s = opaque; |
| 762 |
|
| 763 |
serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
|
| 764 |
} |
| 765 |
|
| 766 |
uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
|
| 767 |
{
|
| 768 |
SerialState *s = opaque; |
| 769 |
uint32_t val; |
| 770 |
|
| 771 |
val = serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
|
| 772 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 773 |
val = bswap16(val); |
| 774 |
#endif
|
| 775 |
return val;
|
| 776 |
} |
| 777 |
|
| 778 |
void serial_mm_writew (void *opaque, |
| 779 |
target_phys_addr_t addr, uint32_t value) |
| 780 |
{
|
| 781 |
SerialState *s = opaque; |
| 782 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 783 |
value = bswap16(value); |
| 784 |
#endif
|
| 785 |
serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
|
| 786 |
} |
| 787 |
|
| 788 |
uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
|
| 789 |
{
|
| 790 |
SerialState *s = opaque; |
| 791 |
uint32_t val; |
| 792 |
|
| 793 |
val = serial_ioport_read(s, (addr - s->base) >> s->it_shift); |
| 794 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 795 |
val = bswap32(val); |
| 796 |
#endif
|
| 797 |
return val;
|
| 798 |
} |
| 799 |
|
| 800 |
void serial_mm_writel (void *opaque, |
| 801 |
target_phys_addr_t addr, uint32_t value) |
| 802 |
{
|
| 803 |
SerialState *s = opaque; |
| 804 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 805 |
value = bswap32(value); |
| 806 |
#endif
|
| 807 |
serial_ioport_write(s, (addr - s->base) >> s->it_shift, value); |
| 808 |
} |
| 809 |
|
| 810 |
static CPUReadMemoryFunc *serial_mm_read[] = {
|
| 811 |
&serial_mm_readb, |
| 812 |
&serial_mm_readw, |
| 813 |
&serial_mm_readl, |
| 814 |
}; |
| 815 |
|
| 816 |
static CPUWriteMemoryFunc *serial_mm_write[] = {
|
| 817 |
&serial_mm_writeb, |
| 818 |
&serial_mm_writew, |
| 819 |
&serial_mm_writel, |
| 820 |
}; |
| 821 |
|
| 822 |
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
|
| 823 |
qemu_irq irq, int baudbase,
|
| 824 |
CharDriverState *chr, int ioregister)
|
| 825 |
{
|
| 826 |
SerialState *s; |
| 827 |
int s_io_memory;
|
| 828 |
|
| 829 |
s = qemu_mallocz(sizeof(SerialState));
|
| 830 |
if (!s)
|
| 831 |
return NULL; |
| 832 |
|
| 833 |
s->base = base; |
| 834 |
s->it_shift = it_shift; |
| 835 |
|
| 836 |
serial_init_core(s, irq, baudbase, chr); |
| 837 |
register_savevm("serial", base, 3, serial_save, serial_load, s); |
| 838 |
|
| 839 |
if (ioregister) {
|
| 840 |
s_io_memory = cpu_register_io_memory(0, serial_mm_read,
|
| 841 |
serial_mm_write, s); |
| 842 |
cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
|
| 843 |
} |
| 844 |
qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1, |
| 845 |
serial_event, s); |
| 846 |
serial_update_msl(s); |
| 847 |
return s;
|
| 848 |
} |