root / hw / pcie_aer.c @ 81486b55
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1 | 34e65944 | Isaku Yamahata | /*
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2 | 34e65944 | Isaku Yamahata | * pcie_aer.c
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3 | 34e65944 | Isaku Yamahata | *
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4 | 34e65944 | Isaku Yamahata | * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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5 | 34e65944 | Isaku Yamahata | * VA Linux Systems Japan K.K.
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6 | 34e65944 | Isaku Yamahata | *
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7 | 34e65944 | Isaku Yamahata | * This program is free software; you can redistribute it and/or modify
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8 | 34e65944 | Isaku Yamahata | * it under the terms of the GNU General Public License as published by
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9 | 34e65944 | Isaku Yamahata | * the Free Software Foundation; either version 2 of the License, or
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10 | 34e65944 | Isaku Yamahata | * (at your option) any later version.
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11 | 34e65944 | Isaku Yamahata | *
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12 | 34e65944 | Isaku Yamahata | * This program is distributed in the hope that it will be useful,
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13 | 34e65944 | Isaku Yamahata | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 34e65944 | Isaku Yamahata | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | 34e65944 | Isaku Yamahata | * GNU General Public License for more details.
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16 | 34e65944 | Isaku Yamahata | *
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17 | 34e65944 | Isaku Yamahata | * You should have received a copy of the GNU General Public License along
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18 | 34e65944 | Isaku Yamahata | * with this program; if not, see <http://www.gnu.org/licenses/>.
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19 | 34e65944 | Isaku Yamahata | */
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20 | 34e65944 | Isaku Yamahata | |
21 | 34e65944 | Isaku Yamahata | #include "sysemu.h" |
22 | 2ae63bda | Isaku Yamahata | #include "qemu-objects.h" |
23 | 2ae63bda | Isaku Yamahata | #include "monitor.h" |
24 | 34e65944 | Isaku Yamahata | #include "pci_bridge.h" |
25 | 34e65944 | Isaku Yamahata | #include "pcie.h" |
26 | 34e65944 | Isaku Yamahata | #include "msix.h" |
27 | 34e65944 | Isaku Yamahata | #include "msi.h" |
28 | 34e65944 | Isaku Yamahata | #include "pci_internals.h" |
29 | 34e65944 | Isaku Yamahata | #include "pcie_regs.h" |
30 | 34e65944 | Isaku Yamahata | |
31 | 34e65944 | Isaku Yamahata | //#define DEBUG_PCIE
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32 | 34e65944 | Isaku Yamahata | #ifdef DEBUG_PCIE
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33 | 34e65944 | Isaku Yamahata | # define PCIE_DPRINTF(fmt, ...) \
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34 | 34e65944 | Isaku Yamahata | fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__) |
35 | 34e65944 | Isaku Yamahata | #else
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36 | 34e65944 | Isaku Yamahata | # define PCIE_DPRINTF(fmt, ...) do {} while (0) |
37 | 34e65944 | Isaku Yamahata | #endif
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38 | 34e65944 | Isaku Yamahata | #define PCIE_DEV_PRINTF(dev, fmt, ...) \
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39 | 34e65944 | Isaku Yamahata | PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__) |
40 | 34e65944 | Isaku Yamahata | |
41 | 81486b55 | Jan Kiszka | #define PCI_ERR_SRC_COR_OFFS 0 |
42 | 81486b55 | Jan Kiszka | #define PCI_ERR_SRC_UNCOR_OFFS 2 |
43 | 81486b55 | Jan Kiszka | |
44 | 34e65944 | Isaku Yamahata | /* From 6.2.7 Error Listing and Rules. Table 6-2, 6-3 and 6-4 */
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45 | 34e65944 | Isaku Yamahata | static uint32_t pcie_aer_uncor_default_severity(uint32_t status)
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46 | 34e65944 | Isaku Yamahata | { |
47 | 34e65944 | Isaku Yamahata | switch (status) {
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48 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_INTN:
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49 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_DLP:
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50 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_SDN:
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51 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_RX_OVER:
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52 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_FCP:
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53 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_MALF_TLP:
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54 | 34e65944 | Isaku Yamahata | return PCI_ERR_ROOT_CMD_FATAL_EN;
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55 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_POISON_TLP:
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56 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_ECRC:
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57 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_UNSUP:
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58 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_COMP_TIME:
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59 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_COMP_ABORT:
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60 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_UNX_COMP:
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61 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_ACSV:
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62 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_MCBTLP:
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63 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_ATOP_EBLOCKED:
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64 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_TLP_PRF_BLOCKED:
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65 | 34e65944 | Isaku Yamahata | return PCI_ERR_ROOT_CMD_NONFATAL_EN;
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66 | 34e65944 | Isaku Yamahata | default:
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67 | 34e65944 | Isaku Yamahata | abort(); |
68 | 34e65944 | Isaku Yamahata | break;
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69 | 34e65944 | Isaku Yamahata | } |
70 | 34e65944 | Isaku Yamahata | return PCI_ERR_ROOT_CMD_FATAL_EN;
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71 | 34e65944 | Isaku Yamahata | } |
72 | 34e65944 | Isaku Yamahata | |
73 | 34e65944 | Isaku Yamahata | static int aer_log_add_err(PCIEAERLog *aer_log, const PCIEAERErr *err) |
74 | 34e65944 | Isaku Yamahata | { |
75 | 34e65944 | Isaku Yamahata | if (aer_log->log_num == aer_log->log_max) {
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76 | 34e65944 | Isaku Yamahata | return -1; |
77 | 34e65944 | Isaku Yamahata | } |
78 | 34e65944 | Isaku Yamahata | memcpy(&aer_log->log[aer_log->log_num], err, sizeof *err);
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79 | 34e65944 | Isaku Yamahata | aer_log->log_num++; |
80 | 34e65944 | Isaku Yamahata | return 0; |
81 | 34e65944 | Isaku Yamahata | } |
82 | 34e65944 | Isaku Yamahata | |
83 | 34e65944 | Isaku Yamahata | static void aer_log_del_err(PCIEAERLog *aer_log, PCIEAERErr *err) |
84 | 34e65944 | Isaku Yamahata | { |
85 | 34e65944 | Isaku Yamahata | assert(aer_log->log_num); |
86 | 34e65944 | Isaku Yamahata | *err = aer_log->log[0];
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87 | 34e65944 | Isaku Yamahata | aer_log->log_num--; |
88 | 34e65944 | Isaku Yamahata | memmove(&aer_log->log[0], &aer_log->log[1], |
89 | 34e65944 | Isaku Yamahata | aer_log->log_num * sizeof *err);
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90 | 34e65944 | Isaku Yamahata | } |
91 | 34e65944 | Isaku Yamahata | |
92 | 34e65944 | Isaku Yamahata | static void aer_log_clear_all_err(PCIEAERLog *aer_log) |
93 | 34e65944 | Isaku Yamahata | { |
94 | 34e65944 | Isaku Yamahata | aer_log->log_num = 0;
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95 | 34e65944 | Isaku Yamahata | } |
96 | 34e65944 | Isaku Yamahata | |
97 | 34e65944 | Isaku Yamahata | int pcie_aer_init(PCIDevice *dev, uint16_t offset)
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98 | 34e65944 | Isaku Yamahata | { |
99 | 34e65944 | Isaku Yamahata | PCIExpressDevice *exp; |
100 | 34e65944 | Isaku Yamahata | |
101 | 34e65944 | Isaku Yamahata | pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, PCI_ERR_VER, |
102 | 34e65944 | Isaku Yamahata | offset, PCI_ERR_SIZEOF); |
103 | 34e65944 | Isaku Yamahata | exp = &dev->exp; |
104 | 34e65944 | Isaku Yamahata | exp->aer_cap = offset; |
105 | 34e65944 | Isaku Yamahata | |
106 | 34e65944 | Isaku Yamahata | /* log_max is property */
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107 | 34e65944 | Isaku Yamahata | if (dev->exp.aer_log.log_max == PCIE_AER_LOG_MAX_UNSET) {
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108 | 34e65944 | Isaku Yamahata | dev->exp.aer_log.log_max = PCIE_AER_LOG_MAX_DEFAULT; |
109 | 34e65944 | Isaku Yamahata | } |
110 | 34e65944 | Isaku Yamahata | /* clip down the value to avoid unreasobale memory usage */
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111 | 34e65944 | Isaku Yamahata | if (dev->exp.aer_log.log_max > PCIE_AER_LOG_MAX_LIMIT) {
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112 | 34e65944 | Isaku Yamahata | return -EINVAL;
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113 | 34e65944 | Isaku Yamahata | } |
114 | 34e65944 | Isaku Yamahata | dev->exp.aer_log.log = qemu_mallocz(sizeof dev->exp.aer_log.log[0] * |
115 | 34e65944 | Isaku Yamahata | dev->exp.aer_log.log_max); |
116 | 34e65944 | Isaku Yamahata | |
117 | 34e65944 | Isaku Yamahata | pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS, |
118 | 34e65944 | Isaku Yamahata | PCI_ERR_UNC_SUPPORTED); |
119 | 34e65944 | Isaku Yamahata | |
120 | 34e65944 | Isaku Yamahata | pci_set_long(dev->config + offset + PCI_ERR_UNCOR_SEVER, |
121 | 34e65944 | Isaku Yamahata | PCI_ERR_UNC_SEVERITY_DEFAULT); |
122 | 34e65944 | Isaku Yamahata | pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_SEVER, |
123 | 34e65944 | Isaku Yamahata | PCI_ERR_UNC_SUPPORTED); |
124 | 34e65944 | Isaku Yamahata | |
125 | 34e65944 | Isaku Yamahata | pci_long_test_and_set_mask(dev->w1cmask + offset + PCI_ERR_COR_STATUS, |
126 | 34e65944 | Isaku Yamahata | PCI_ERR_COR_STATUS); |
127 | 34e65944 | Isaku Yamahata | |
128 | 34e65944 | Isaku Yamahata | pci_set_long(dev->config + offset + PCI_ERR_COR_MASK, |
129 | 34e65944 | Isaku Yamahata | PCI_ERR_COR_MASK_DEFAULT); |
130 | 34e65944 | Isaku Yamahata | pci_set_long(dev->wmask + offset + PCI_ERR_COR_MASK, |
131 | 34e65944 | Isaku Yamahata | PCI_ERR_COR_SUPPORTED); |
132 | 34e65944 | Isaku Yamahata | |
133 | 34e65944 | Isaku Yamahata | /* capabilities and control. multiple header logging is supported */
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134 | 34e65944 | Isaku Yamahata | if (dev->exp.aer_log.log_max > 0) { |
135 | 34e65944 | Isaku Yamahata | pci_set_long(dev->config + offset + PCI_ERR_CAP, |
136 | 34e65944 | Isaku Yamahata | PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_CHKC | |
137 | 34e65944 | Isaku Yamahata | PCI_ERR_CAP_MHRC); |
138 | 34e65944 | Isaku Yamahata | pci_set_long(dev->wmask + offset + PCI_ERR_CAP, |
139 | 34e65944 | Isaku Yamahata | PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE | |
140 | 34e65944 | Isaku Yamahata | PCI_ERR_CAP_MHRE); |
141 | 34e65944 | Isaku Yamahata | } else {
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142 | 34e65944 | Isaku Yamahata | pci_set_long(dev->config + offset + PCI_ERR_CAP, |
143 | 34e65944 | Isaku Yamahata | PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_CHKC); |
144 | 34e65944 | Isaku Yamahata | pci_set_long(dev->wmask + offset + PCI_ERR_CAP, |
145 | 34e65944 | Isaku Yamahata | PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); |
146 | 34e65944 | Isaku Yamahata | } |
147 | 34e65944 | Isaku Yamahata | |
148 | 34e65944 | Isaku Yamahata | switch (pcie_cap_get_type(dev)) {
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149 | 34e65944 | Isaku Yamahata | case PCI_EXP_TYPE_ROOT_PORT:
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150 | 34e65944 | Isaku Yamahata | /* this case will be set by pcie_aer_root_init() */
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151 | 34e65944 | Isaku Yamahata | /* fallthrough */
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152 | 34e65944 | Isaku Yamahata | case PCI_EXP_TYPE_DOWNSTREAM:
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153 | 34e65944 | Isaku Yamahata | case PCI_EXP_TYPE_UPSTREAM:
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154 | 34e65944 | Isaku Yamahata | pci_word_test_and_set_mask(dev->wmask + PCI_BRIDGE_CONTROL, |
155 | 34e65944 | Isaku Yamahata | PCI_BRIDGE_CTL_SERR); |
156 | 34e65944 | Isaku Yamahata | pci_long_test_and_set_mask(dev->w1cmask + PCI_STATUS, |
157 | 34e65944 | Isaku Yamahata | PCI_SEC_STATUS_RCV_SYSTEM_ERROR); |
158 | 34e65944 | Isaku Yamahata | break;
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159 | 34e65944 | Isaku Yamahata | default:
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160 | 34e65944 | Isaku Yamahata | /* nothing */
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161 | 34e65944 | Isaku Yamahata | break;
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162 | 34e65944 | Isaku Yamahata | } |
163 | 34e65944 | Isaku Yamahata | return 0; |
164 | 34e65944 | Isaku Yamahata | } |
165 | 34e65944 | Isaku Yamahata | |
166 | 34e65944 | Isaku Yamahata | void pcie_aer_exit(PCIDevice *dev)
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167 | 34e65944 | Isaku Yamahata | { |
168 | 34e65944 | Isaku Yamahata | qemu_free(dev->exp.aer_log.log); |
169 | 34e65944 | Isaku Yamahata | } |
170 | 34e65944 | Isaku Yamahata | |
171 | 34e65944 | Isaku Yamahata | static void pcie_aer_update_uncor_status(PCIDevice *dev) |
172 | 34e65944 | Isaku Yamahata | { |
173 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap = dev->config + dev->exp.aer_cap; |
174 | 34e65944 | Isaku Yamahata | PCIEAERLog *aer_log = &dev->exp.aer_log; |
175 | 34e65944 | Isaku Yamahata | |
176 | 34e65944 | Isaku Yamahata | uint16_t i; |
177 | 34e65944 | Isaku Yamahata | for (i = 0; i < aer_log->log_num; i++) { |
178 | 34e65944 | Isaku Yamahata | pci_long_test_and_set_mask(aer_cap + PCI_ERR_UNCOR_STATUS, |
179 | 34e65944 | Isaku Yamahata | dev->exp.aer_log.log[i].status); |
180 | 34e65944 | Isaku Yamahata | } |
181 | 34e65944 | Isaku Yamahata | } |
182 | 34e65944 | Isaku Yamahata | |
183 | 34e65944 | Isaku Yamahata | /*
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184 | 34e65944 | Isaku Yamahata | * return value:
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185 | 247c97f3 | Michael S. Tsirkin | * true: error message needs to be sent up
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186 | 34e65944 | Isaku Yamahata | * false: error message is masked
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187 | 34e65944 | Isaku Yamahata | *
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188 | 34e65944 | Isaku Yamahata | * 6.2.6 Error Message Control
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189 | 34e65944 | Isaku Yamahata | * Figure 6-3
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190 | 34e65944 | Isaku Yamahata | * all pci express devices part
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191 | 34e65944 | Isaku Yamahata | */
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192 | 34e65944 | Isaku Yamahata | static bool |
193 | 34e65944 | Isaku Yamahata | pcie_aer_msg_alldev(PCIDevice *dev, const PCIEAERMsg *msg)
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194 | 34e65944 | Isaku Yamahata | { |
195 | 34e65944 | Isaku Yamahata | if (!(pcie_aer_msg_is_uncor(msg) &&
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196 | 34e65944 | Isaku Yamahata | (pci_get_word(dev->config + PCI_COMMAND) & PCI_COMMAND_SERR))) { |
197 | 34e65944 | Isaku Yamahata | return false; |
198 | 34e65944 | Isaku Yamahata | } |
199 | 34e65944 | Isaku Yamahata | |
200 | 34e65944 | Isaku Yamahata | /* Signaled System Error
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201 | 34e65944 | Isaku Yamahata | *
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202 | 34e65944 | Isaku Yamahata | * 7.5.1.1 Command register
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203 | 34e65944 | Isaku Yamahata | * Bit 8 SERR# Enable
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204 | 34e65944 | Isaku Yamahata | *
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205 | 34e65944 | Isaku Yamahata | * When Set, this bit enables reporting of Non-fatal and Fatal
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206 | 34e65944 | Isaku Yamahata | * errors detected by the Function to the Root Complex. Note that
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207 | 34e65944 | Isaku Yamahata | * errors are reported if enabled either through this bit or through
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208 | 34e65944 | Isaku Yamahata | * the PCI Express specific bits in the Device Control register (see
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209 | 34e65944 | Isaku Yamahata | * Section 7.8.4).
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210 | 34e65944 | Isaku Yamahata | */
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211 | 34e65944 | Isaku Yamahata | pci_word_test_and_set_mask(dev->config + PCI_STATUS, |
212 | 34e65944 | Isaku Yamahata | PCI_STATUS_SIG_SYSTEM_ERROR); |
213 | 34e65944 | Isaku Yamahata | |
214 | 34e65944 | Isaku Yamahata | if (!(msg->severity &
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215 | 34e65944 | Isaku Yamahata | pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL))) { |
216 | 34e65944 | Isaku Yamahata | return false; |
217 | 34e65944 | Isaku Yamahata | } |
218 | 34e65944 | Isaku Yamahata | |
219 | 34e65944 | Isaku Yamahata | /* send up error message */
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220 | 247c97f3 | Michael S. Tsirkin | return true; |
221 | 247c97f3 | Michael S. Tsirkin | } |
222 | 247c97f3 | Michael S. Tsirkin | |
223 | 34e65944 | Isaku Yamahata | /*
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224 | 34e65944 | Isaku Yamahata | * return value:
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225 | 34e65944 | Isaku Yamahata | * true: error message is sent up
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226 | 34e65944 | Isaku Yamahata | * false: error message is masked
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227 | 34e65944 | Isaku Yamahata | *
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228 | 34e65944 | Isaku Yamahata | * 6.2.6 Error Message Control
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229 | 34e65944 | Isaku Yamahata | * Figure 6-3
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230 | 34e65944 | Isaku Yamahata | * virtual pci bridge part
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231 | 34e65944 | Isaku Yamahata | */
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232 | 34e65944 | Isaku Yamahata | static bool pcie_aer_msg_vbridge(PCIDevice *dev, const PCIEAERMsg *msg) |
233 | 34e65944 | Isaku Yamahata | { |
234 | 34e65944 | Isaku Yamahata | uint16_t bridge_control = pci_get_word(dev->config + PCI_BRIDGE_CONTROL); |
235 | 34e65944 | Isaku Yamahata | |
236 | 34e65944 | Isaku Yamahata | if (pcie_aer_msg_is_uncor(msg)) {
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237 | 34e65944 | Isaku Yamahata | /* Received System Error */
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238 | 34e65944 | Isaku Yamahata | pci_word_test_and_set_mask(dev->config + PCI_SEC_STATUS, |
239 | 34e65944 | Isaku Yamahata | PCI_SEC_STATUS_RCV_SYSTEM_ERROR); |
240 | 34e65944 | Isaku Yamahata | } |
241 | 34e65944 | Isaku Yamahata | |
242 | 34e65944 | Isaku Yamahata | if (!(bridge_control & PCI_BRIDGE_CTL_SERR)) {
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243 | 34e65944 | Isaku Yamahata | return false; |
244 | 34e65944 | Isaku Yamahata | } |
245 | 34e65944 | Isaku Yamahata | return true; |
246 | 34e65944 | Isaku Yamahata | } |
247 | 34e65944 | Isaku Yamahata | |
248 | 34e65944 | Isaku Yamahata | void pcie_aer_root_set_vector(PCIDevice *dev, unsigned int vector) |
249 | 34e65944 | Isaku Yamahata | { |
250 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap = dev->config + dev->exp.aer_cap; |
251 | 34e65944 | Isaku Yamahata | assert(vector < PCI_ERR_ROOT_IRQ_MAX); |
252 | 34e65944 | Isaku Yamahata | pci_long_test_and_clear_mask(aer_cap + PCI_ERR_ROOT_STATUS, |
253 | 34e65944 | Isaku Yamahata | PCI_ERR_ROOT_IRQ); |
254 | 34e65944 | Isaku Yamahata | pci_long_test_and_set_mask(aer_cap + PCI_ERR_ROOT_STATUS, |
255 | 34e65944 | Isaku Yamahata | vector << PCI_ERR_ROOT_IRQ_SHIFT); |
256 | 34e65944 | Isaku Yamahata | } |
257 | 34e65944 | Isaku Yamahata | |
258 | 34e65944 | Isaku Yamahata | static unsigned int pcie_aer_root_get_vector(PCIDevice *dev) |
259 | 34e65944 | Isaku Yamahata | { |
260 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap = dev->config + dev->exp.aer_cap; |
261 | 34e65944 | Isaku Yamahata | uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS); |
262 | 34e65944 | Isaku Yamahata | return (root_status & PCI_ERR_ROOT_IRQ) >> PCI_ERR_ROOT_IRQ_SHIFT;
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263 | 34e65944 | Isaku Yamahata | } |
264 | 34e65944 | Isaku Yamahata | |
265 | c3f33667 | Michael S. Tsirkin | /* Given a status register, get corresponding bits in the command register */
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266 | c3f33667 | Michael S. Tsirkin | static uint32_t pcie_aer_status_to_cmd(uint32_t status)
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267 | c3f33667 | Michael S. Tsirkin | { |
268 | c3f33667 | Michael S. Tsirkin | uint32_t cmd = 0;
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269 | c3f33667 | Michael S. Tsirkin | if (status & PCI_ERR_ROOT_COR_RCV) {
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270 | c3f33667 | Michael S. Tsirkin | cmd |= PCI_ERR_ROOT_CMD_COR_EN; |
271 | c3f33667 | Michael S. Tsirkin | } |
272 | c3f33667 | Michael S. Tsirkin | if (status & PCI_ERR_ROOT_NONFATAL_RCV) {
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273 | c3f33667 | Michael S. Tsirkin | cmd |= PCI_ERR_ROOT_CMD_NONFATAL_EN; |
274 | c3f33667 | Michael S. Tsirkin | } |
275 | c3f33667 | Michael S. Tsirkin | if (status & PCI_ERR_ROOT_FATAL_RCV) {
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276 | c3f33667 | Michael S. Tsirkin | cmd |= PCI_ERR_ROOT_CMD_FATAL_EN; |
277 | c3f33667 | Michael S. Tsirkin | } |
278 | c3f33667 | Michael S. Tsirkin | return cmd;
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279 | c3f33667 | Michael S. Tsirkin | } |
280 | c3f33667 | Michael S. Tsirkin | |
281 | 513691b7 | Michael S. Tsirkin | static void pcie_aer_root_notify(PCIDevice *dev) |
282 | 513691b7 | Michael S. Tsirkin | { |
283 | 513691b7 | Michael S. Tsirkin | if (msix_enabled(dev)) {
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284 | 513691b7 | Michael S. Tsirkin | msix_notify(dev, pcie_aer_root_get_vector(dev)); |
285 | 513691b7 | Michael S. Tsirkin | } else if (msi_enabled(dev)) { |
286 | 513691b7 | Michael S. Tsirkin | msi_notify(dev, pcie_aer_root_get_vector(dev)); |
287 | 513691b7 | Michael S. Tsirkin | } else {
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288 | 513691b7 | Michael S. Tsirkin | qemu_set_irq(dev->irq[dev->exp.aer_intx], 1);
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289 | 513691b7 | Michael S. Tsirkin | } |
290 | 513691b7 | Michael S. Tsirkin | } |
291 | 513691b7 | Michael S. Tsirkin | |
292 | 34e65944 | Isaku Yamahata | /*
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293 | 34e65944 | Isaku Yamahata | * 6.2.6 Error Message Control
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294 | 34e65944 | Isaku Yamahata | * Figure 6-3
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295 | 34e65944 | Isaku Yamahata | * root port part
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296 | 34e65944 | Isaku Yamahata | */
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297 | 5f47c187 | Michael S. Tsirkin | static void pcie_aer_msg_root_port(PCIDevice *dev, const PCIEAERMsg *msg) |
298 | 34e65944 | Isaku Yamahata | { |
299 | 34e65944 | Isaku Yamahata | uint16_t cmd; |
300 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap; |
301 | 34e65944 | Isaku Yamahata | uint32_t root_cmd; |
302 | c3f33667 | Michael S. Tsirkin | uint32_t root_status, prev_status; |
303 | 34e65944 | Isaku Yamahata | |
304 | 34e65944 | Isaku Yamahata | cmd = pci_get_word(dev->config + PCI_COMMAND); |
305 | 34e65944 | Isaku Yamahata | aer_cap = dev->config + dev->exp.aer_cap; |
306 | 34e65944 | Isaku Yamahata | root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND); |
307 | c3f33667 | Michael S. Tsirkin | prev_status = root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS); |
308 | 34e65944 | Isaku Yamahata | |
309 | 34e65944 | Isaku Yamahata | if (cmd & PCI_COMMAND_SERR) {
|
310 | 34e65944 | Isaku Yamahata | /* System Error.
|
311 | 34e65944 | Isaku Yamahata | *
|
312 | 34e65944 | Isaku Yamahata | * The way to report System Error is platform specific and
|
313 | 34e65944 | Isaku Yamahata | * it isn't implemented in qemu right now.
|
314 | 34e65944 | Isaku Yamahata | * So just discard the error for now.
|
315 | 34e65944 | Isaku Yamahata | * OS which cares of aer would receive errors via
|
316 | 34e65944 | Isaku Yamahata | * native aer mechanims, so this wouldn't matter.
|
317 | 34e65944 | Isaku Yamahata | */
|
318 | 34e65944 | Isaku Yamahata | } |
319 | 34e65944 | Isaku Yamahata | |
320 | 34e65944 | Isaku Yamahata | /* Errro Message Received: Root Error Status register */
|
321 | 34e65944 | Isaku Yamahata | switch (msg->severity) {
|
322 | 34e65944 | Isaku Yamahata | case PCI_ERR_ROOT_CMD_COR_EN:
|
323 | 34e65944 | Isaku Yamahata | if (root_status & PCI_ERR_ROOT_COR_RCV) {
|
324 | 34e65944 | Isaku Yamahata | root_status |= PCI_ERR_ROOT_MULTI_COR_RCV; |
325 | 34e65944 | Isaku Yamahata | } else {
|
326 | 81486b55 | Jan Kiszka | pci_set_word(aer_cap + PCI_ERR_ROOT_ERR_SRC + PCI_ERR_SRC_COR_OFFS, |
327 | 81486b55 | Jan Kiszka | msg->source_id); |
328 | 34e65944 | Isaku Yamahata | } |
329 | 34e65944 | Isaku Yamahata | root_status |= PCI_ERR_ROOT_COR_RCV; |
330 | 34e65944 | Isaku Yamahata | break;
|
331 | 34e65944 | Isaku Yamahata | case PCI_ERR_ROOT_CMD_NONFATAL_EN:
|
332 | 34e65944 | Isaku Yamahata | root_status |= PCI_ERR_ROOT_NONFATAL_RCV; |
333 | 34e65944 | Isaku Yamahata | break;
|
334 | 34e65944 | Isaku Yamahata | case PCI_ERR_ROOT_CMD_FATAL_EN:
|
335 | 34e65944 | Isaku Yamahata | if (!(root_status & PCI_ERR_ROOT_UNCOR_RCV)) {
|
336 | 34e65944 | Isaku Yamahata | root_status |= PCI_ERR_ROOT_FIRST_FATAL; |
337 | 34e65944 | Isaku Yamahata | } |
338 | 34e65944 | Isaku Yamahata | root_status |= PCI_ERR_ROOT_FATAL_RCV; |
339 | 34e65944 | Isaku Yamahata | break;
|
340 | 34e65944 | Isaku Yamahata | default:
|
341 | 34e65944 | Isaku Yamahata | abort(); |
342 | 34e65944 | Isaku Yamahata | break;
|
343 | 34e65944 | Isaku Yamahata | } |
344 | 34e65944 | Isaku Yamahata | if (pcie_aer_msg_is_uncor(msg)) {
|
345 | 34e65944 | Isaku Yamahata | if (root_status & PCI_ERR_ROOT_UNCOR_RCV) {
|
346 | 34e65944 | Isaku Yamahata | root_status |= PCI_ERR_ROOT_MULTI_UNCOR_RCV; |
347 | 34e65944 | Isaku Yamahata | } else {
|
348 | 81486b55 | Jan Kiszka | pci_set_word(aer_cap + PCI_ERR_ROOT_ERR_SRC + |
349 | 81486b55 | Jan Kiszka | PCI_ERR_SRC_UNCOR_OFFS, msg->source_id); |
350 | 34e65944 | Isaku Yamahata | } |
351 | 34e65944 | Isaku Yamahata | root_status |= PCI_ERR_ROOT_UNCOR_RCV; |
352 | 34e65944 | Isaku Yamahata | } |
353 | 34e65944 | Isaku Yamahata | pci_set_long(aer_cap + PCI_ERR_ROOT_STATUS, root_status); |
354 | 34e65944 | Isaku Yamahata | |
355 | c3f33667 | Michael S. Tsirkin | /* 6.2.4.1.2 Interrupt Generation */
|
356 | c3f33667 | Michael S. Tsirkin | /* All the above did was set some bits in the status register.
|
357 | c3f33667 | Michael S. Tsirkin | * Specifically these that match message severity.
|
358 | c3f33667 | Michael S. Tsirkin | * The below code relies on this fact. */
|
359 | c3f33667 | Michael S. Tsirkin | if (!(root_cmd & msg->severity) ||
|
360 | c3f33667 | Michael S. Tsirkin | (pcie_aer_status_to_cmd(prev_status) & root_cmd)) { |
361 | c3f33667 | Michael S. Tsirkin | /* Condition is not being set or was already true so nothing to do. */
|
362 | 5f47c187 | Michael S. Tsirkin | return;
|
363 | c3f33667 | Michael S. Tsirkin | } |
364 | c3f33667 | Michael S. Tsirkin | |
365 | 513691b7 | Michael S. Tsirkin | pcie_aer_root_notify(dev); |
366 | 34e65944 | Isaku Yamahata | } |
367 | 34e65944 | Isaku Yamahata | |
368 | 34e65944 | Isaku Yamahata | /*
|
369 | 34e65944 | Isaku Yamahata | * 6.2.6 Error Message Control Figure 6-3
|
370 | 247c97f3 | Michael S. Tsirkin | *
|
371 | d33d9156 | Michael S. Tsirkin | * Walk up the bus tree from the device, propagate the error message.
|
372 | 34e65944 | Isaku Yamahata | */
|
373 | d33d9156 | Michael S. Tsirkin | static void pcie_aer_msg(PCIDevice *dev, const PCIEAERMsg *msg) |
374 | 34e65944 | Isaku Yamahata | { |
375 | 34e65944 | Isaku Yamahata | uint8_t type; |
376 | 34e65944 | Isaku Yamahata | |
377 | d33d9156 | Michael S. Tsirkin | while (dev) {
|
378 | d33d9156 | Michael S. Tsirkin | if (!pci_is_express(dev)) {
|
379 | d33d9156 | Michael S. Tsirkin | /* just ignore it */
|
380 | d33d9156 | Michael S. Tsirkin | /* TODO: Shouldn't we set PCI_STATUS_SIG_SYSTEM_ERROR?
|
381 | d33d9156 | Michael S. Tsirkin | * Consider e.g. a PCI bridge above a PCI Express device. */
|
382 | 34e65944 | Isaku Yamahata | return;
|
383 | 34e65944 | Isaku Yamahata | } |
384 | 247c97f3 | Michael S. Tsirkin | |
385 | d33d9156 | Michael S. Tsirkin | type = pcie_cap_get_type(dev); |
386 | d33d9156 | Michael S. Tsirkin | if ((type == PCI_EXP_TYPE_ROOT_PORT ||
|
387 | d33d9156 | Michael S. Tsirkin | type == PCI_EXP_TYPE_UPSTREAM || |
388 | d33d9156 | Michael S. Tsirkin | type == PCI_EXP_TYPE_DOWNSTREAM) && |
389 | d33d9156 | Michael S. Tsirkin | !pcie_aer_msg_vbridge(dev, msg)) { |
390 | d33d9156 | Michael S. Tsirkin | return;
|
391 | d33d9156 | Michael S. Tsirkin | } |
392 | d33d9156 | Michael S. Tsirkin | if (!pcie_aer_msg_alldev(dev, msg)) {
|
393 | d33d9156 | Michael S. Tsirkin | return;
|
394 | d33d9156 | Michael S. Tsirkin | } |
395 | d33d9156 | Michael S. Tsirkin | if (type == PCI_EXP_TYPE_ROOT_PORT) {
|
396 | d33d9156 | Michael S. Tsirkin | pcie_aer_msg_root_port(dev, msg); |
397 | d33d9156 | Michael S. Tsirkin | /* Root port can notify system itself,
|
398 | d33d9156 | Michael S. Tsirkin | or send the error message to root complex event collector. */
|
399 | d33d9156 | Michael S. Tsirkin | /*
|
400 | d33d9156 | Michael S. Tsirkin | * if root port is associated with an event collector,
|
401 | d33d9156 | Michael S. Tsirkin | * return the root complex event collector here.
|
402 | d33d9156 | Michael S. Tsirkin | * For now root complex event collector isn't supported.
|
403 | d33d9156 | Michael S. Tsirkin | */
|
404 | 247c97f3 | Michael S. Tsirkin | return;
|
405 | 247c97f3 | Michael S. Tsirkin | } |
406 | d33d9156 | Michael S. Tsirkin | dev = pci_bridge_get_device(dev->bus); |
407 | 247c97f3 | Michael S. Tsirkin | } |
408 | 34e65944 | Isaku Yamahata | } |
409 | 34e65944 | Isaku Yamahata | |
410 | 34e65944 | Isaku Yamahata | static void pcie_aer_update_log(PCIDevice *dev, const PCIEAERErr *err) |
411 | 34e65944 | Isaku Yamahata | { |
412 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap = dev->config + dev->exp.aer_cap; |
413 | e6e055c9 | Blue Swirl | uint8_t first_bit = ffs(err->status) - 1;
|
414 | 34e65944 | Isaku Yamahata | uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP); |
415 | 34e65944 | Isaku Yamahata | int i;
|
416 | 34e65944 | Isaku Yamahata | |
417 | 34e65944 | Isaku Yamahata | assert(err->status); |
418 | 34e65944 | Isaku Yamahata | assert(err->status & (err->status - 1));
|
419 | 34e65944 | Isaku Yamahata | |
420 | 34e65944 | Isaku Yamahata | errcap &= ~(PCI_ERR_CAP_FEP_MASK | PCI_ERR_CAP_TLP); |
421 | 34e65944 | Isaku Yamahata | errcap |= PCI_ERR_CAP_FEP(first_bit); |
422 | 34e65944 | Isaku Yamahata | |
423 | 34e65944 | Isaku Yamahata | if (err->flags & PCIE_AER_ERR_HEADER_VALID) {
|
424 | 34e65944 | Isaku Yamahata | for (i = 0; i < ARRAY_SIZE(err->header); ++i) { |
425 | 34e65944 | Isaku Yamahata | /* 7.10.8 Header Log Register */
|
426 | 34e65944 | Isaku Yamahata | uint8_t *header_log = |
427 | 34e65944 | Isaku Yamahata | aer_cap + PCI_ERR_HEADER_LOG + i * sizeof err->header[0]; |
428 | 34e65944 | Isaku Yamahata | cpu_to_be32wu((uint32_t*)header_log, err->header[i]); |
429 | 34e65944 | Isaku Yamahata | } |
430 | 34e65944 | Isaku Yamahata | } else {
|
431 | 34e65944 | Isaku Yamahata | assert(!(err->flags & PCIE_AER_ERR_TLP_PREFIX_PRESENT)); |
432 | 34e65944 | Isaku Yamahata | memset(aer_cap + PCI_ERR_HEADER_LOG, 0, PCI_ERR_HEADER_LOG_SIZE);
|
433 | 34e65944 | Isaku Yamahata | } |
434 | 34e65944 | Isaku Yamahata | |
435 | 34e65944 | Isaku Yamahata | if ((err->flags & PCIE_AER_ERR_TLP_PREFIX_PRESENT) &&
|
436 | 34e65944 | Isaku Yamahata | (pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) & |
437 | 34e65944 | Isaku Yamahata | PCI_EXP_DEVCAP2_EETLPP)) { |
438 | 34e65944 | Isaku Yamahata | for (i = 0; i < ARRAY_SIZE(err->prefix); ++i) { |
439 | 34e65944 | Isaku Yamahata | /* 7.10.12 tlp prefix log register */
|
440 | 34e65944 | Isaku Yamahata | uint8_t *prefix_log = |
441 | 34e65944 | Isaku Yamahata | aer_cap + PCI_ERR_TLP_PREFIX_LOG + i * sizeof err->prefix[0]; |
442 | 34e65944 | Isaku Yamahata | cpu_to_be32wu((uint32_t*)prefix_log, err->prefix[i]); |
443 | 34e65944 | Isaku Yamahata | } |
444 | 34e65944 | Isaku Yamahata | errcap |= PCI_ERR_CAP_TLP; |
445 | 34e65944 | Isaku Yamahata | } else {
|
446 | 34e65944 | Isaku Yamahata | memset(aer_cap + PCI_ERR_TLP_PREFIX_LOG, 0,
|
447 | 34e65944 | Isaku Yamahata | PCI_ERR_TLP_PREFIX_LOG_SIZE); |
448 | 34e65944 | Isaku Yamahata | } |
449 | 34e65944 | Isaku Yamahata | pci_set_long(aer_cap + PCI_ERR_CAP, errcap); |
450 | 34e65944 | Isaku Yamahata | } |
451 | 34e65944 | Isaku Yamahata | |
452 | 34e65944 | Isaku Yamahata | static void pcie_aer_clear_log(PCIDevice *dev) |
453 | 34e65944 | Isaku Yamahata | { |
454 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap = dev->config + dev->exp.aer_cap; |
455 | 34e65944 | Isaku Yamahata | |
456 | 34e65944 | Isaku Yamahata | pci_long_test_and_clear_mask(aer_cap + PCI_ERR_CAP, |
457 | 34e65944 | Isaku Yamahata | PCI_ERR_CAP_FEP_MASK | PCI_ERR_CAP_TLP); |
458 | 34e65944 | Isaku Yamahata | |
459 | 34e65944 | Isaku Yamahata | memset(aer_cap + PCI_ERR_HEADER_LOG, 0, PCI_ERR_HEADER_LOG_SIZE);
|
460 | 34e65944 | Isaku Yamahata | memset(aer_cap + PCI_ERR_TLP_PREFIX_LOG, 0, PCI_ERR_TLP_PREFIX_LOG_SIZE);
|
461 | 34e65944 | Isaku Yamahata | } |
462 | 34e65944 | Isaku Yamahata | |
463 | 34e65944 | Isaku Yamahata | static void pcie_aer_clear_error(PCIDevice *dev) |
464 | 34e65944 | Isaku Yamahata | { |
465 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap = dev->config + dev->exp.aer_cap; |
466 | 34e65944 | Isaku Yamahata | uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP); |
467 | 34e65944 | Isaku Yamahata | PCIEAERLog *aer_log = &dev->exp.aer_log; |
468 | 34e65944 | Isaku Yamahata | PCIEAERErr err; |
469 | 34e65944 | Isaku Yamahata | |
470 | 34e65944 | Isaku Yamahata | if (!(errcap & PCI_ERR_CAP_MHRE) || !aer_log->log_num) {
|
471 | 34e65944 | Isaku Yamahata | pcie_aer_clear_log(dev); |
472 | 34e65944 | Isaku Yamahata | return;
|
473 | 34e65944 | Isaku Yamahata | } |
474 | 34e65944 | Isaku Yamahata | |
475 | 34e65944 | Isaku Yamahata | /*
|
476 | 34e65944 | Isaku Yamahata | * If more errors are queued, set corresponding bits in uncorrectable
|
477 | 34e65944 | Isaku Yamahata | * error status.
|
478 | 34e65944 | Isaku Yamahata | * We emulate uncorrectable error status register as W1CS.
|
479 | 34e65944 | Isaku Yamahata | * So set bit in uncorrectable error status here again for multiple
|
480 | 34e65944 | Isaku Yamahata | * error recording support.
|
481 | 34e65944 | Isaku Yamahata | *
|
482 | 34e65944 | Isaku Yamahata | * 6.2.4.2 Multiple Error Handling(Advanced Error Reporting Capability)
|
483 | 34e65944 | Isaku Yamahata | */
|
484 | 34e65944 | Isaku Yamahata | pcie_aer_update_uncor_status(dev); |
485 | 34e65944 | Isaku Yamahata | |
486 | 34e65944 | Isaku Yamahata | aer_log_del_err(aer_log, &err); |
487 | 34e65944 | Isaku Yamahata | pcie_aer_update_log(dev, &err); |
488 | 34e65944 | Isaku Yamahata | } |
489 | 34e65944 | Isaku Yamahata | |
490 | 34e65944 | Isaku Yamahata | static int pcie_aer_record_error(PCIDevice *dev, |
491 | 34e65944 | Isaku Yamahata | const PCIEAERErr *err)
|
492 | 34e65944 | Isaku Yamahata | { |
493 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap = dev->config + dev->exp.aer_cap; |
494 | 34e65944 | Isaku Yamahata | uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP); |
495 | 34e65944 | Isaku Yamahata | int fep = PCI_ERR_CAP_FEP(errcap);
|
496 | 34e65944 | Isaku Yamahata | |
497 | 34e65944 | Isaku Yamahata | assert(err->status); |
498 | 34e65944 | Isaku Yamahata | assert(err->status & (err->status - 1));
|
499 | 34e65944 | Isaku Yamahata | |
500 | 34e65944 | Isaku Yamahata | if (errcap & PCI_ERR_CAP_MHRE &&
|
501 | 34e65944 | Isaku Yamahata | (pci_get_long(aer_cap + PCI_ERR_UNCOR_STATUS) & (1U << fep))) {
|
502 | 34e65944 | Isaku Yamahata | /* Not first error. queue error */
|
503 | 34e65944 | Isaku Yamahata | if (aer_log_add_err(&dev->exp.aer_log, err) < 0) { |
504 | 34e65944 | Isaku Yamahata | /* overflow */
|
505 | 34e65944 | Isaku Yamahata | return -1; |
506 | 34e65944 | Isaku Yamahata | } |
507 | 34e65944 | Isaku Yamahata | return 0; |
508 | 34e65944 | Isaku Yamahata | } |
509 | 34e65944 | Isaku Yamahata | |
510 | 34e65944 | Isaku Yamahata | pcie_aer_update_log(dev, err); |
511 | 34e65944 | Isaku Yamahata | return 0; |
512 | 34e65944 | Isaku Yamahata | } |
513 | 34e65944 | Isaku Yamahata | |
514 | 34e65944 | Isaku Yamahata | typedef struct PCIEAERInject { |
515 | 34e65944 | Isaku Yamahata | PCIDevice *dev; |
516 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap; |
517 | 34e65944 | Isaku Yamahata | const PCIEAERErr *err;
|
518 | 34e65944 | Isaku Yamahata | uint16_t devctl; |
519 | 34e65944 | Isaku Yamahata | uint16_t devsta; |
520 | 34e65944 | Isaku Yamahata | uint32_t error_status; |
521 | 34e65944 | Isaku Yamahata | bool unsupported_request;
|
522 | 34e65944 | Isaku Yamahata | bool log_overflow;
|
523 | 34e65944 | Isaku Yamahata | PCIEAERMsg msg; |
524 | 34e65944 | Isaku Yamahata | } PCIEAERInject; |
525 | 34e65944 | Isaku Yamahata | |
526 | 34e65944 | Isaku Yamahata | static bool pcie_aer_inject_cor_error(PCIEAERInject *inj, |
527 | 34e65944 | Isaku Yamahata | uint32_t uncor_status, |
528 | 34e65944 | Isaku Yamahata | bool is_advisory_nonfatal)
|
529 | 34e65944 | Isaku Yamahata | { |
530 | 34e65944 | Isaku Yamahata | PCIDevice *dev = inj->dev; |
531 | 34e65944 | Isaku Yamahata | |
532 | 34e65944 | Isaku Yamahata | inj->devsta |= PCI_EXP_DEVSTA_CED; |
533 | 34e65944 | Isaku Yamahata | if (inj->unsupported_request) {
|
534 | 34e65944 | Isaku Yamahata | inj->devsta |= PCI_EXP_DEVSTA_URD; |
535 | 34e65944 | Isaku Yamahata | } |
536 | 34e65944 | Isaku Yamahata | pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_DEVSTA, inj->devsta); |
537 | 34e65944 | Isaku Yamahata | |
538 | 34e65944 | Isaku Yamahata | if (inj->aer_cap) {
|
539 | 34e65944 | Isaku Yamahata | uint32_t mask; |
540 | 34e65944 | Isaku Yamahata | pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_COR_STATUS, |
541 | 34e65944 | Isaku Yamahata | inj->error_status); |
542 | 34e65944 | Isaku Yamahata | mask = pci_get_long(inj->aer_cap + PCI_ERR_COR_MASK); |
543 | 34e65944 | Isaku Yamahata | if (mask & inj->error_status) {
|
544 | 34e65944 | Isaku Yamahata | return false; |
545 | 34e65944 | Isaku Yamahata | } |
546 | 34e65944 | Isaku Yamahata | if (is_advisory_nonfatal) {
|
547 | 34e65944 | Isaku Yamahata | uint32_t uncor_mask = |
548 | 34e65944 | Isaku Yamahata | pci_get_long(inj->aer_cap + PCI_ERR_UNCOR_MASK); |
549 | 34e65944 | Isaku Yamahata | if (!(uncor_mask & uncor_status)) {
|
550 | 34e65944 | Isaku Yamahata | inj->log_overflow = !!pcie_aer_record_error(dev, inj->err); |
551 | 34e65944 | Isaku Yamahata | } |
552 | 34e65944 | Isaku Yamahata | pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS, |
553 | 34e65944 | Isaku Yamahata | uncor_status); |
554 | 34e65944 | Isaku Yamahata | } |
555 | 34e65944 | Isaku Yamahata | } |
556 | 34e65944 | Isaku Yamahata | |
557 | 34e65944 | Isaku Yamahata | if (inj->unsupported_request && !(inj->devctl & PCI_EXP_DEVCTL_URRE)) {
|
558 | 34e65944 | Isaku Yamahata | return false; |
559 | 34e65944 | Isaku Yamahata | } |
560 | 34e65944 | Isaku Yamahata | if (!(inj->devctl & PCI_EXP_DEVCTL_CERE)) {
|
561 | 34e65944 | Isaku Yamahata | return false; |
562 | 34e65944 | Isaku Yamahata | } |
563 | 34e65944 | Isaku Yamahata | |
564 | 34e65944 | Isaku Yamahata | inj->msg.severity = PCI_ERR_ROOT_CMD_COR_EN; |
565 | 34e65944 | Isaku Yamahata | return true; |
566 | 34e65944 | Isaku Yamahata | } |
567 | 34e65944 | Isaku Yamahata | |
568 | 34e65944 | Isaku Yamahata | static bool pcie_aer_inject_uncor_error(PCIEAERInject *inj, bool is_fatal) |
569 | 34e65944 | Isaku Yamahata | { |
570 | 34e65944 | Isaku Yamahata | PCIDevice *dev = inj->dev; |
571 | 34e65944 | Isaku Yamahata | uint16_t cmd; |
572 | 34e65944 | Isaku Yamahata | |
573 | 34e65944 | Isaku Yamahata | if (is_fatal) {
|
574 | 34e65944 | Isaku Yamahata | inj->devsta |= PCI_EXP_DEVSTA_FED; |
575 | 34e65944 | Isaku Yamahata | } else {
|
576 | 34e65944 | Isaku Yamahata | inj->devsta |= PCI_EXP_DEVSTA_NFED; |
577 | 34e65944 | Isaku Yamahata | } |
578 | 34e65944 | Isaku Yamahata | if (inj->unsupported_request) {
|
579 | 34e65944 | Isaku Yamahata | inj->devsta |= PCI_EXP_DEVSTA_URD; |
580 | 34e65944 | Isaku Yamahata | } |
581 | 34e65944 | Isaku Yamahata | pci_set_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVSTA, inj->devsta); |
582 | 34e65944 | Isaku Yamahata | |
583 | 34e65944 | Isaku Yamahata | if (inj->aer_cap) {
|
584 | 34e65944 | Isaku Yamahata | uint32_t mask = pci_get_long(inj->aer_cap + PCI_ERR_UNCOR_MASK); |
585 | 34e65944 | Isaku Yamahata | if (mask & inj->error_status) {
|
586 | 34e65944 | Isaku Yamahata | pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS, |
587 | 34e65944 | Isaku Yamahata | inj->error_status); |
588 | 34e65944 | Isaku Yamahata | return false; |
589 | 34e65944 | Isaku Yamahata | } |
590 | 34e65944 | Isaku Yamahata | |
591 | 34e65944 | Isaku Yamahata | inj->log_overflow = !!pcie_aer_record_error(dev, inj->err); |
592 | 34e65944 | Isaku Yamahata | pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS, |
593 | 34e65944 | Isaku Yamahata | inj->error_status); |
594 | 34e65944 | Isaku Yamahata | } |
595 | 34e65944 | Isaku Yamahata | |
596 | 34e65944 | Isaku Yamahata | cmd = pci_get_word(dev->config + PCI_COMMAND); |
597 | 34e65944 | Isaku Yamahata | if (inj->unsupported_request &&
|
598 | 34e65944 | Isaku Yamahata | !(inj->devctl & PCI_EXP_DEVCTL_URRE) && !(cmd & PCI_COMMAND_SERR)) { |
599 | 34e65944 | Isaku Yamahata | return false; |
600 | 34e65944 | Isaku Yamahata | } |
601 | 34e65944 | Isaku Yamahata | if (is_fatal) {
|
602 | 34e65944 | Isaku Yamahata | if (!((cmd & PCI_COMMAND_SERR) ||
|
603 | 34e65944 | Isaku Yamahata | (inj->devctl & PCI_EXP_DEVCTL_FERE))) { |
604 | 34e65944 | Isaku Yamahata | return false; |
605 | 34e65944 | Isaku Yamahata | } |
606 | 34e65944 | Isaku Yamahata | inj->msg.severity = PCI_ERR_ROOT_CMD_FATAL_EN; |
607 | 34e65944 | Isaku Yamahata | } else {
|
608 | 34e65944 | Isaku Yamahata | if (!((cmd & PCI_COMMAND_SERR) ||
|
609 | 34e65944 | Isaku Yamahata | (inj->devctl & PCI_EXP_DEVCTL_NFERE))) { |
610 | 34e65944 | Isaku Yamahata | return false; |
611 | 34e65944 | Isaku Yamahata | } |
612 | 34e65944 | Isaku Yamahata | inj->msg.severity = PCI_ERR_ROOT_CMD_NONFATAL_EN; |
613 | 34e65944 | Isaku Yamahata | } |
614 | 34e65944 | Isaku Yamahata | return true; |
615 | 34e65944 | Isaku Yamahata | } |
616 | 34e65944 | Isaku Yamahata | |
617 | 34e65944 | Isaku Yamahata | /*
|
618 | 34e65944 | Isaku Yamahata | * non-Function specific error must be recorded in all functions.
|
619 | 34e65944 | Isaku Yamahata | * It is the responsibility of the caller of this function.
|
620 | 34e65944 | Isaku Yamahata | * It is also caller's responsiblity to determine which function should
|
621 | 34e65944 | Isaku Yamahata | * report the rerror.
|
622 | 34e65944 | Isaku Yamahata | *
|
623 | 34e65944 | Isaku Yamahata | * 6.2.4 Error Logging
|
624 | 34e65944 | Isaku Yamahata | * 6.2.5 Sqeunce of Device Error Signaling and Logging Operations
|
625 | 34e65944 | Isaku Yamahata | * table 6-2: Flowchard Showing Sequence of Device Error Signaling and Logging
|
626 | 34e65944 | Isaku Yamahata | * Operations
|
627 | 34e65944 | Isaku Yamahata | */
|
628 | 34e65944 | Isaku Yamahata | int pcie_aer_inject_error(PCIDevice *dev, const PCIEAERErr *err) |
629 | 34e65944 | Isaku Yamahata | { |
630 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap = NULL;
|
631 | 34e65944 | Isaku Yamahata | uint16_t devctl = 0;
|
632 | 34e65944 | Isaku Yamahata | uint16_t devsta = 0;
|
633 | 34e65944 | Isaku Yamahata | uint32_t error_status = err->status; |
634 | 34e65944 | Isaku Yamahata | PCIEAERInject inj; |
635 | 34e65944 | Isaku Yamahata | |
636 | 34e65944 | Isaku Yamahata | if (!pci_is_express(dev)) {
|
637 | 34e65944 | Isaku Yamahata | return -ENOSYS;
|
638 | 34e65944 | Isaku Yamahata | } |
639 | 34e65944 | Isaku Yamahata | |
640 | 34e65944 | Isaku Yamahata | if (err->flags & PCIE_AER_ERR_IS_CORRECTABLE) {
|
641 | 34e65944 | Isaku Yamahata | error_status &= PCI_ERR_COR_SUPPORTED; |
642 | 34e65944 | Isaku Yamahata | } else {
|
643 | 34e65944 | Isaku Yamahata | error_status &= PCI_ERR_UNC_SUPPORTED; |
644 | 34e65944 | Isaku Yamahata | } |
645 | 34e65944 | Isaku Yamahata | |
646 | 34e65944 | Isaku Yamahata | /* invalid status bit. one and only one bit must be set */
|
647 | 34e65944 | Isaku Yamahata | if (!error_status || (error_status & (error_status - 1))) { |
648 | 34e65944 | Isaku Yamahata | return -EINVAL;
|
649 | 34e65944 | Isaku Yamahata | } |
650 | 34e65944 | Isaku Yamahata | |
651 | 34e65944 | Isaku Yamahata | if (dev->exp.aer_cap) {
|
652 | 34e65944 | Isaku Yamahata | uint8_t *exp_cap = dev->config + dev->exp.exp_cap; |
653 | 34e65944 | Isaku Yamahata | aer_cap = dev->config + dev->exp.aer_cap; |
654 | 34e65944 | Isaku Yamahata | devctl = pci_get_long(exp_cap + PCI_EXP_DEVCTL); |
655 | 34e65944 | Isaku Yamahata | devsta = pci_get_long(exp_cap + PCI_EXP_DEVSTA); |
656 | 34e65944 | Isaku Yamahata | } |
657 | 34e65944 | Isaku Yamahata | |
658 | 34e65944 | Isaku Yamahata | inj.dev = dev; |
659 | 34e65944 | Isaku Yamahata | inj.aer_cap = aer_cap; |
660 | 34e65944 | Isaku Yamahata | inj.err = err; |
661 | 34e65944 | Isaku Yamahata | inj.devctl = devctl; |
662 | 34e65944 | Isaku Yamahata | inj.devsta = devsta; |
663 | 34e65944 | Isaku Yamahata | inj.error_status = error_status; |
664 | 34e65944 | Isaku Yamahata | inj.unsupported_request = !(err->flags & PCIE_AER_ERR_IS_CORRECTABLE) && |
665 | 34e65944 | Isaku Yamahata | err->status == PCI_ERR_UNC_UNSUP; |
666 | 34e65944 | Isaku Yamahata | inj.log_overflow = false;
|
667 | 34e65944 | Isaku Yamahata | |
668 | 34e65944 | Isaku Yamahata | if (err->flags & PCIE_AER_ERR_IS_CORRECTABLE) {
|
669 | 34e65944 | Isaku Yamahata | if (!pcie_aer_inject_cor_error(&inj, 0, false)) { |
670 | 34e65944 | Isaku Yamahata | return 0; |
671 | 34e65944 | Isaku Yamahata | } |
672 | 34e65944 | Isaku Yamahata | } else {
|
673 | 34e65944 | Isaku Yamahata | bool is_fatal =
|
674 | 34e65944 | Isaku Yamahata | pcie_aer_uncor_default_severity(error_status) == |
675 | 34e65944 | Isaku Yamahata | PCI_ERR_ROOT_CMD_FATAL_EN; |
676 | 34e65944 | Isaku Yamahata | if (aer_cap) {
|
677 | 34e65944 | Isaku Yamahata | is_fatal = |
678 | 34e65944 | Isaku Yamahata | error_status & pci_get_long(aer_cap + PCI_ERR_UNCOR_SEVER); |
679 | 34e65944 | Isaku Yamahata | } |
680 | 34e65944 | Isaku Yamahata | if (!is_fatal && (err->flags & PCIE_AER_ERR_MAYBE_ADVISORY)) {
|
681 | 34e65944 | Isaku Yamahata | inj.error_status = PCI_ERR_COR_ADV_NONFATAL; |
682 | 34e65944 | Isaku Yamahata | if (!pcie_aer_inject_cor_error(&inj, error_status, true)) { |
683 | 34e65944 | Isaku Yamahata | return 0; |
684 | 34e65944 | Isaku Yamahata | } |
685 | 34e65944 | Isaku Yamahata | } else {
|
686 | 34e65944 | Isaku Yamahata | if (!pcie_aer_inject_uncor_error(&inj, is_fatal)) {
|
687 | 34e65944 | Isaku Yamahata | return 0; |
688 | 34e65944 | Isaku Yamahata | } |
689 | 34e65944 | Isaku Yamahata | } |
690 | 34e65944 | Isaku Yamahata | } |
691 | 34e65944 | Isaku Yamahata | |
692 | 34e65944 | Isaku Yamahata | /* send up error message */
|
693 | 34e65944 | Isaku Yamahata | inj.msg.source_id = err->source_id; |
694 | 34e65944 | Isaku Yamahata | pcie_aer_msg(dev, &inj.msg); |
695 | 34e65944 | Isaku Yamahata | |
696 | 34e65944 | Isaku Yamahata | if (inj.log_overflow) {
|
697 | 34e65944 | Isaku Yamahata | PCIEAERErr header_log_overflow = { |
698 | 34e65944 | Isaku Yamahata | .status = PCI_ERR_COR_HL_OVERFLOW, |
699 | 34e65944 | Isaku Yamahata | .flags = PCIE_AER_ERR_IS_CORRECTABLE, |
700 | 34e65944 | Isaku Yamahata | }; |
701 | 34e65944 | Isaku Yamahata | int ret = pcie_aer_inject_error(dev, &header_log_overflow);
|
702 | 34e65944 | Isaku Yamahata | assert(!ret); |
703 | 34e65944 | Isaku Yamahata | } |
704 | 34e65944 | Isaku Yamahata | return 0; |
705 | 34e65944 | Isaku Yamahata | } |
706 | 34e65944 | Isaku Yamahata | |
707 | 34e65944 | Isaku Yamahata | void pcie_aer_write_config(PCIDevice *dev,
|
708 | 34e65944 | Isaku Yamahata | uint32_t addr, uint32_t val, int len)
|
709 | 34e65944 | Isaku Yamahata | { |
710 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap = dev->config + dev->exp.aer_cap; |
711 | 34e65944 | Isaku Yamahata | uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP); |
712 | 34e65944 | Isaku Yamahata | uint32_t first_error = 1U << PCI_ERR_CAP_FEP(errcap);
|
713 | 34e65944 | Isaku Yamahata | uint32_t uncorsta = pci_get_long(aer_cap + PCI_ERR_UNCOR_STATUS); |
714 | 34e65944 | Isaku Yamahata | |
715 | 34e65944 | Isaku Yamahata | /* uncorrectable error */
|
716 | 34e65944 | Isaku Yamahata | if (!(uncorsta & first_error)) {
|
717 | 34e65944 | Isaku Yamahata | /* the bit that corresponds to the first error is cleared */
|
718 | 34e65944 | Isaku Yamahata | pcie_aer_clear_error(dev); |
719 | 34e65944 | Isaku Yamahata | } else if (errcap & PCI_ERR_CAP_MHRE) { |
720 | 34e65944 | Isaku Yamahata | /* When PCI_ERR_CAP_MHRE is enabled and the first error isn't cleared
|
721 | 34e65944 | Isaku Yamahata | * nothing should happen. So we have to revert the modification to
|
722 | 34e65944 | Isaku Yamahata | * the register.
|
723 | 34e65944 | Isaku Yamahata | */
|
724 | 34e65944 | Isaku Yamahata | pcie_aer_update_uncor_status(dev); |
725 | 34e65944 | Isaku Yamahata | } else {
|
726 | 34e65944 | Isaku Yamahata | /* capability & control
|
727 | 34e65944 | Isaku Yamahata | * PCI_ERR_CAP_MHRE might be cleared, so clear of header log.
|
728 | 34e65944 | Isaku Yamahata | */
|
729 | 34e65944 | Isaku Yamahata | aer_log_clear_all_err(&dev->exp.aer_log); |
730 | 34e65944 | Isaku Yamahata | } |
731 | 34e65944 | Isaku Yamahata | } |
732 | 34e65944 | Isaku Yamahata | |
733 | 34e65944 | Isaku Yamahata | void pcie_aer_root_init(PCIDevice *dev)
|
734 | 34e65944 | Isaku Yamahata | { |
735 | 34e65944 | Isaku Yamahata | uint16_t pos = dev->exp.aer_cap; |
736 | 34e65944 | Isaku Yamahata | |
737 | 34e65944 | Isaku Yamahata | pci_set_long(dev->wmask + pos + PCI_ERR_ROOT_COMMAND, |
738 | 34e65944 | Isaku Yamahata | PCI_ERR_ROOT_CMD_EN_MASK); |
739 | 34e65944 | Isaku Yamahata | pci_set_long(dev->w1cmask + pos + PCI_ERR_ROOT_STATUS, |
740 | 34e65944 | Isaku Yamahata | PCI_ERR_ROOT_STATUS_REPORT_MASK); |
741 | 34e65944 | Isaku Yamahata | } |
742 | 34e65944 | Isaku Yamahata | |
743 | 34e65944 | Isaku Yamahata | void pcie_aer_root_reset(PCIDevice *dev)
|
744 | 34e65944 | Isaku Yamahata | { |
745 | 34e65944 | Isaku Yamahata | uint8_t* aer_cap = dev->config + dev->exp.aer_cap; |
746 | 34e65944 | Isaku Yamahata | |
747 | 34e65944 | Isaku Yamahata | pci_set_long(aer_cap + PCI_ERR_ROOT_COMMAND, 0);
|
748 | 34e65944 | Isaku Yamahata | |
749 | 34e65944 | Isaku Yamahata | /*
|
750 | 34e65944 | Isaku Yamahata | * Advanced Error Interrupt Message Number in Root Error Status Register
|
751 | 34e65944 | Isaku Yamahata | * must be updated by chip dependent code because it's chip dependent
|
752 | 34e65944 | Isaku Yamahata | * which number is used.
|
753 | 34e65944 | Isaku Yamahata | */
|
754 | 34e65944 | Isaku Yamahata | } |
755 | 34e65944 | Isaku Yamahata | |
756 | 34e65944 | Isaku Yamahata | void pcie_aer_root_write_config(PCIDevice *dev,
|
757 | 34e65944 | Isaku Yamahata | uint32_t addr, uint32_t val, int len,
|
758 | 34e65944 | Isaku Yamahata | uint32_t root_cmd_prev) |
759 | 34e65944 | Isaku Yamahata | { |
760 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap = dev->config + dev->exp.aer_cap; |
761 | 2b3cb353 | Michael S. Tsirkin | uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS); |
762 | 2b3cb353 | Michael S. Tsirkin | uint32_t enabled_cmd = pcie_aer_status_to_cmd(root_status); |
763 | 34e65944 | Isaku Yamahata | uint32_t root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND); |
764 | 2b3cb353 | Michael S. Tsirkin | /* 6.2.4.1.2 Interrupt Generation */
|
765 | 2b3cb353 | Michael S. Tsirkin | if (!msix_enabled(dev) && !msi_enabled(dev)) {
|
766 | 2b3cb353 | Michael S. Tsirkin | qemu_set_irq(dev->irq[dev->exp.aer_intx], !!(root_cmd & enabled_cmd)); |
767 | 2b3cb353 | Michael S. Tsirkin | return;
|
768 | 2b3cb353 | Michael S. Tsirkin | } |
769 | 34e65944 | Isaku Yamahata | |
770 | 2b3cb353 | Michael S. Tsirkin | if ((root_cmd_prev & enabled_cmd) || !(root_cmd & enabled_cmd)) {
|
771 | 2b3cb353 | Michael S. Tsirkin | /* Send MSI on transition from false to true. */
|
772 | 2b3cb353 | Michael S. Tsirkin | return;
|
773 | 2b3cb353 | Michael S. Tsirkin | } |
774 | 34e65944 | Isaku Yamahata | |
775 | 513691b7 | Michael S. Tsirkin | pcie_aer_root_notify(dev); |
776 | 34e65944 | Isaku Yamahata | } |
777 | 34e65944 | Isaku Yamahata | |
778 | 34e65944 | Isaku Yamahata | static const VMStateDescription vmstate_pcie_aer_err = { |
779 | 34e65944 | Isaku Yamahata | .name = "PCIE_AER_ERROR",
|
780 | 34e65944 | Isaku Yamahata | .version_id = 1,
|
781 | 34e65944 | Isaku Yamahata | .minimum_version_id = 1,
|
782 | 34e65944 | Isaku Yamahata | .minimum_version_id_old = 1,
|
783 | 34e65944 | Isaku Yamahata | .fields = (VMStateField[]) { |
784 | 34e65944 | Isaku Yamahata | VMSTATE_UINT32(status, PCIEAERErr), |
785 | 34e65944 | Isaku Yamahata | VMSTATE_UINT16(source_id, PCIEAERErr), |
786 | 34e65944 | Isaku Yamahata | VMSTATE_UINT16(flags, PCIEAERErr), |
787 | 34e65944 | Isaku Yamahata | VMSTATE_UINT32_ARRAY(header, PCIEAERErr, 4),
|
788 | 34e65944 | Isaku Yamahata | VMSTATE_UINT32_ARRAY(prefix, PCIEAERErr, 4),
|
789 | 34e65944 | Isaku Yamahata | VMSTATE_END_OF_LIST() |
790 | 34e65944 | Isaku Yamahata | } |
791 | 34e65944 | Isaku Yamahata | }; |
792 | 34e65944 | Isaku Yamahata | |
793 | 34e65944 | Isaku Yamahata | const VMStateDescription vmstate_pcie_aer_log = {
|
794 | 34e65944 | Isaku Yamahata | .name = "PCIE_AER_ERROR_LOG",
|
795 | 34e65944 | Isaku Yamahata | .version_id = 1,
|
796 | 34e65944 | Isaku Yamahata | .minimum_version_id = 1,
|
797 | 34e65944 | Isaku Yamahata | .minimum_version_id_old = 1,
|
798 | 34e65944 | Isaku Yamahata | .fields = (VMStateField[]) { |
799 | 34e65944 | Isaku Yamahata | VMSTATE_UINT16(log_num, PCIEAERLog), |
800 | 34e65944 | Isaku Yamahata | VMSTATE_UINT16(log_max, PCIEAERLog), |
801 | 47188700 | Dmitry Eremin-Solenikov | VMSTATE_STRUCT_VARRAY_POINTER_UINT16(log, PCIEAERLog, log_num, |
802 | 34e65944 | Isaku Yamahata | vmstate_pcie_aer_err, PCIEAERErr), |
803 | 34e65944 | Isaku Yamahata | VMSTATE_END_OF_LIST() |
804 | 34e65944 | Isaku Yamahata | } |
805 | 34e65944 | Isaku Yamahata | }; |
806 | 2ae63bda | Isaku Yamahata | |
807 | 2ae63bda | Isaku Yamahata | void pcie_aer_inject_error_print(Monitor *mon, const QObject *data) |
808 | 2ae63bda | Isaku Yamahata | { |
809 | 2ae63bda | Isaku Yamahata | QDict *qdict; |
810 | 2ae63bda | Isaku Yamahata | int devfn;
|
811 | 2ae63bda | Isaku Yamahata | assert(qobject_type(data) == QTYPE_QDICT); |
812 | 2ae63bda | Isaku Yamahata | qdict = qobject_to_qdict(data); |
813 | 2ae63bda | Isaku Yamahata | |
814 | 2ae63bda | Isaku Yamahata | devfn = (int)qdict_get_int(qdict, "devfn"); |
815 | 2ae63bda | Isaku Yamahata | monitor_printf(mon, "OK id: %s domain: %x, bus: %x devfn: %x.%x\n",
|
816 | 2ae63bda | Isaku Yamahata | qdict_get_str(qdict, "id"),
|
817 | 2ae63bda | Isaku Yamahata | (int) qdict_get_int(qdict, "domain"), |
818 | 2ae63bda | Isaku Yamahata | (int) qdict_get_int(qdict, "bus"), |
819 | 2ae63bda | Isaku Yamahata | PCI_SLOT(devfn), PCI_FUNC(devfn)); |
820 | 2ae63bda | Isaku Yamahata | } |
821 | 2ae63bda | Isaku Yamahata | |
822 | 2ae63bda | Isaku Yamahata | typedef struct PCIEAERErrorName { |
823 | 2ae63bda | Isaku Yamahata | const char *name; |
824 | 2ae63bda | Isaku Yamahata | uint32_t val; |
825 | 2ae63bda | Isaku Yamahata | bool correctable;
|
826 | 2ae63bda | Isaku Yamahata | } PCIEAERErrorName; |
827 | 2ae63bda | Isaku Yamahata | |
828 | 2ae63bda | Isaku Yamahata | /*
|
829 | 2ae63bda | Isaku Yamahata | * AER error name -> value convertion table
|
830 | 2ae63bda | Isaku Yamahata | * This naming scheme is same to linux aer-injection tool.
|
831 | 2ae63bda | Isaku Yamahata | */
|
832 | 2ae63bda | Isaku Yamahata | static const struct PCIEAERErrorName pcie_aer_error_list[] = { |
833 | 2ae63bda | Isaku Yamahata | { |
834 | 2ae63bda | Isaku Yamahata | .name = "TRAIN",
|
835 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_UNC_TRAIN, |
836 | 2ae63bda | Isaku Yamahata | .correctable = false,
|
837 | 2ae63bda | Isaku Yamahata | }, { |
838 | 2ae63bda | Isaku Yamahata | .name = "DLP",
|
839 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_UNC_DLP, |
840 | 2ae63bda | Isaku Yamahata | .correctable = false,
|
841 | 2ae63bda | Isaku Yamahata | }, { |
842 | 2ae63bda | Isaku Yamahata | .name = "SDN",
|
843 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_UNC_SDN, |
844 | 2ae63bda | Isaku Yamahata | .correctable = false,
|
845 | 2ae63bda | Isaku Yamahata | }, { |
846 | 2ae63bda | Isaku Yamahata | .name = "POISON_TLP",
|
847 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_UNC_POISON_TLP, |
848 | 2ae63bda | Isaku Yamahata | .correctable = false,
|
849 | 2ae63bda | Isaku Yamahata | }, { |
850 | 2ae63bda | Isaku Yamahata | .name = "FCP",
|
851 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_UNC_FCP, |
852 | 2ae63bda | Isaku Yamahata | .correctable = false,
|
853 | 2ae63bda | Isaku Yamahata | }, { |
854 | 2ae63bda | Isaku Yamahata | .name = "COMP_TIME",
|
855 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_UNC_COMP_TIME, |
856 | 2ae63bda | Isaku Yamahata | .correctable = false,
|
857 | 2ae63bda | Isaku Yamahata | }, { |
858 | 2ae63bda | Isaku Yamahata | .name = "COMP_ABORT",
|
859 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_UNC_COMP_ABORT, |
860 | 2ae63bda | Isaku Yamahata | .correctable = false,
|
861 | 2ae63bda | Isaku Yamahata | }, { |
862 | 2ae63bda | Isaku Yamahata | .name = "UNX_COMP",
|
863 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_UNC_UNX_COMP, |
864 | 2ae63bda | Isaku Yamahata | .correctable = false,
|
865 | 2ae63bda | Isaku Yamahata | }, { |
866 | 2ae63bda | Isaku Yamahata | .name = "RX_OVER",
|
867 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_UNC_RX_OVER, |
868 | 2ae63bda | Isaku Yamahata | .correctable = false,
|
869 | 2ae63bda | Isaku Yamahata | }, { |
870 | 2ae63bda | Isaku Yamahata | .name = "MALF_TLP",
|
871 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_UNC_MALF_TLP, |
872 | 2ae63bda | Isaku Yamahata | .correctable = false,
|
873 | 2ae63bda | Isaku Yamahata | }, { |
874 | 2ae63bda | Isaku Yamahata | .name = "ECRC",
|
875 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_UNC_ECRC, |
876 | 2ae63bda | Isaku Yamahata | .correctable = false,
|
877 | 2ae63bda | Isaku Yamahata | }, { |
878 | 2ae63bda | Isaku Yamahata | .name = "UNSUP",
|
879 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_UNC_UNSUP, |
880 | 2ae63bda | Isaku Yamahata | .correctable = false,
|
881 | 2ae63bda | Isaku Yamahata | }, { |
882 | 2ae63bda | Isaku Yamahata | .name = "ACSV",
|
883 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_UNC_ACSV, |
884 | 2ae63bda | Isaku Yamahata | .correctable = false,
|
885 | 2ae63bda | Isaku Yamahata | }, { |
886 | 2ae63bda | Isaku Yamahata | .name = "INTN",
|
887 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_UNC_INTN, |
888 | 2ae63bda | Isaku Yamahata | .correctable = false,
|
889 | 2ae63bda | Isaku Yamahata | }, { |
890 | 2ae63bda | Isaku Yamahata | .name = "MCBTLP",
|
891 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_UNC_MCBTLP, |
892 | 2ae63bda | Isaku Yamahata | .correctable = false,
|
893 | 2ae63bda | Isaku Yamahata | }, { |
894 | 2ae63bda | Isaku Yamahata | .name = "ATOP_EBLOCKED",
|
895 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_UNC_ATOP_EBLOCKED, |
896 | 2ae63bda | Isaku Yamahata | .correctable = false,
|
897 | 2ae63bda | Isaku Yamahata | }, { |
898 | 2ae63bda | Isaku Yamahata | .name = "TLP_PRF_BLOCKED",
|
899 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_UNC_TLP_PRF_BLOCKED, |
900 | 2ae63bda | Isaku Yamahata | .correctable = false,
|
901 | 2ae63bda | Isaku Yamahata | }, { |
902 | 2ae63bda | Isaku Yamahata | .name = "RCVR",
|
903 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_COR_RCVR, |
904 | 2ae63bda | Isaku Yamahata | .correctable = true,
|
905 | 2ae63bda | Isaku Yamahata | }, { |
906 | 2ae63bda | Isaku Yamahata | .name = "BAD_TLP",
|
907 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_COR_BAD_TLP, |
908 | 2ae63bda | Isaku Yamahata | .correctable = true,
|
909 | 2ae63bda | Isaku Yamahata | }, { |
910 | 2ae63bda | Isaku Yamahata | .name = "BAD_DLLP",
|
911 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_COR_BAD_DLLP, |
912 | 2ae63bda | Isaku Yamahata | .correctable = true,
|
913 | 2ae63bda | Isaku Yamahata | }, { |
914 | 2ae63bda | Isaku Yamahata | .name = "REP_ROLL",
|
915 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_COR_REP_ROLL, |
916 | 2ae63bda | Isaku Yamahata | .correctable = true,
|
917 | 2ae63bda | Isaku Yamahata | }, { |
918 | 2ae63bda | Isaku Yamahata | .name = "REP_TIMER",
|
919 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_COR_REP_TIMER, |
920 | 2ae63bda | Isaku Yamahata | .correctable = true,
|
921 | 2ae63bda | Isaku Yamahata | }, { |
922 | 2ae63bda | Isaku Yamahata | .name = "ADV_NONFATAL",
|
923 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_COR_ADV_NONFATAL, |
924 | 2ae63bda | Isaku Yamahata | .correctable = true,
|
925 | 2ae63bda | Isaku Yamahata | }, { |
926 | 2ae63bda | Isaku Yamahata | .name = "INTERNAL",
|
927 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_COR_INTERNAL, |
928 | 2ae63bda | Isaku Yamahata | .correctable = true,
|
929 | 2ae63bda | Isaku Yamahata | }, { |
930 | 2ae63bda | Isaku Yamahata | .name = "HL_OVERFLOW",
|
931 | 2ae63bda | Isaku Yamahata | .val = PCI_ERR_COR_HL_OVERFLOW, |
932 | 2ae63bda | Isaku Yamahata | .correctable = true,
|
933 | 2ae63bda | Isaku Yamahata | }, |
934 | 2ae63bda | Isaku Yamahata | }; |
935 | 2ae63bda | Isaku Yamahata | |
936 | 2ae63bda | Isaku Yamahata | static int pcie_aer_parse_error_string(const char *error_name, |
937 | 2ae63bda | Isaku Yamahata | uint32_t *status, bool *correctable)
|
938 | 2ae63bda | Isaku Yamahata | { |
939 | 2ae63bda | Isaku Yamahata | int i;
|
940 | 2ae63bda | Isaku Yamahata | |
941 | 2ae63bda | Isaku Yamahata | for (i = 0; i < ARRAY_SIZE(pcie_aer_error_list); i++) { |
942 | 2ae63bda | Isaku Yamahata | const PCIEAERErrorName *e = &pcie_aer_error_list[i];
|
943 | 2ae63bda | Isaku Yamahata | if (strcmp(error_name, e->name)) {
|
944 | 2ae63bda | Isaku Yamahata | continue;
|
945 | 2ae63bda | Isaku Yamahata | } |
946 | 2ae63bda | Isaku Yamahata | |
947 | 2ae63bda | Isaku Yamahata | *status = e->val; |
948 | 2ae63bda | Isaku Yamahata | *correctable = e->correctable; |
949 | 2ae63bda | Isaku Yamahata | return 0; |
950 | 2ae63bda | Isaku Yamahata | } |
951 | 2ae63bda | Isaku Yamahata | return -EINVAL;
|
952 | 2ae63bda | Isaku Yamahata | } |
953 | 2ae63bda | Isaku Yamahata | |
954 | 2ae63bda | Isaku Yamahata | int do_pcie_aer_inejct_error(Monitor *mon,
|
955 | 2ae63bda | Isaku Yamahata | const QDict *qdict, QObject **ret_data)
|
956 | 2ae63bda | Isaku Yamahata | { |
957 | 2ae63bda | Isaku Yamahata | const char *id = qdict_get_str(qdict, "id"); |
958 | 2ae63bda | Isaku Yamahata | const char *error_name; |
959 | 2ae63bda | Isaku Yamahata | uint32_t error_status; |
960 | 2ae63bda | Isaku Yamahata | bool correctable;
|
961 | 2ae63bda | Isaku Yamahata | PCIDevice *dev; |
962 | 2ae63bda | Isaku Yamahata | PCIEAERErr err; |
963 | 2ae63bda | Isaku Yamahata | int ret;
|
964 | 2ae63bda | Isaku Yamahata | |
965 | 2ae63bda | Isaku Yamahata | ret = pci_qdev_find_device(id, &dev); |
966 | 2ae63bda | Isaku Yamahata | if (ret < 0) { |
967 | 2ae63bda | Isaku Yamahata | monitor_printf(mon, |
968 | 2ae63bda | Isaku Yamahata | "id or pci device path is invalid or device not "
|
969 | 2ae63bda | Isaku Yamahata | "found. %s\n", id);
|
970 | 2ae63bda | Isaku Yamahata | return ret;
|
971 | 2ae63bda | Isaku Yamahata | } |
972 | 2ae63bda | Isaku Yamahata | if (!pci_is_express(dev)) {
|
973 | 2ae63bda | Isaku Yamahata | monitor_printf(mon, "the device doesn't support pci express. %s\n",
|
974 | 2ae63bda | Isaku Yamahata | id); |
975 | 2ae63bda | Isaku Yamahata | return -ENOSYS;
|
976 | 2ae63bda | Isaku Yamahata | } |
977 | 2ae63bda | Isaku Yamahata | |
978 | 2ae63bda | Isaku Yamahata | error_name = qdict_get_str(qdict, "error_status");
|
979 | 2ae63bda | Isaku Yamahata | if (pcie_aer_parse_error_string(error_name, &error_status, &correctable)) {
|
980 | 2ae63bda | Isaku Yamahata | char *e = NULL; |
981 | 2ae63bda | Isaku Yamahata | error_status = strtoul(error_name, &e, 0);
|
982 | 2ae63bda | Isaku Yamahata | correctable = !!qdict_get_int(qdict, "correctable");
|
983 | 2ae63bda | Isaku Yamahata | if (!e || *e != '\0') { |
984 | 2ae63bda | Isaku Yamahata | monitor_printf(mon, "invalid error status value. \"%s\"",
|
985 | 2ae63bda | Isaku Yamahata | error_name); |
986 | 2ae63bda | Isaku Yamahata | return -EINVAL;
|
987 | 2ae63bda | Isaku Yamahata | } |
988 | 2ae63bda | Isaku Yamahata | } |
989 | 2ae63bda | Isaku Yamahata | err.source_id = (pci_bus_num(dev->bus) << 8) | dev->devfn;
|
990 | 2ae63bda | Isaku Yamahata | |
991 | 2ae63bda | Isaku Yamahata | err.flags = 0;
|
992 | 2ae63bda | Isaku Yamahata | if (correctable) {
|
993 | 2ae63bda | Isaku Yamahata | err.flags |= PCIE_AER_ERR_IS_CORRECTABLE; |
994 | 2ae63bda | Isaku Yamahata | } |
995 | 2ae63bda | Isaku Yamahata | if (qdict_get_int(qdict, "advisory_non_fatal")) { |
996 | 2ae63bda | Isaku Yamahata | err.flags |= PCIE_AER_ERR_MAYBE_ADVISORY; |
997 | 2ae63bda | Isaku Yamahata | } |
998 | 2ae63bda | Isaku Yamahata | if (qdict_haskey(qdict, "header0")) { |
999 | 2ae63bda | Isaku Yamahata | err.flags |= PCIE_AER_ERR_HEADER_VALID; |
1000 | 2ae63bda | Isaku Yamahata | } |
1001 | 2ae63bda | Isaku Yamahata | if (qdict_haskey(qdict, "prefix0")) { |
1002 | 2ae63bda | Isaku Yamahata | err.flags |= PCIE_AER_ERR_TLP_PREFIX_PRESENT; |
1003 | 2ae63bda | Isaku Yamahata | } |
1004 | 2ae63bda | Isaku Yamahata | |
1005 | 2ae63bda | Isaku Yamahata | err.header[0] = qdict_get_try_int(qdict, "header0", 0); |
1006 | 2ae63bda | Isaku Yamahata | err.header[1] = qdict_get_try_int(qdict, "header1", 0); |
1007 | 2ae63bda | Isaku Yamahata | err.header[2] = qdict_get_try_int(qdict, "header2", 0); |
1008 | 2ae63bda | Isaku Yamahata | err.header[3] = qdict_get_try_int(qdict, "header3", 0); |
1009 | 2ae63bda | Isaku Yamahata | |
1010 | 2ae63bda | Isaku Yamahata | err.prefix[0] = qdict_get_try_int(qdict, "prefix0", 0); |
1011 | 2ae63bda | Isaku Yamahata | err.prefix[1] = qdict_get_try_int(qdict, "prefix1", 0); |
1012 | 2ae63bda | Isaku Yamahata | err.prefix[2] = qdict_get_try_int(qdict, "prefix2", 0); |
1013 | 2ae63bda | Isaku Yamahata | err.prefix[3] = qdict_get_try_int(qdict, "prefix3", 0); |
1014 | 2ae63bda | Isaku Yamahata | |
1015 | 2ae63bda | Isaku Yamahata | ret = pcie_aer_inject_error(dev, &err); |
1016 | 2ae63bda | Isaku Yamahata | *ret_data = qobject_from_jsonf("{'id': %s, "
|
1017 | 2ae63bda | Isaku Yamahata | "'domain': %d, 'bus': %d, 'devfn': %d, "
|
1018 | 2ae63bda | Isaku Yamahata | "'ret': %d}",
|
1019 | 2ae63bda | Isaku Yamahata | id, |
1020 | 2ae63bda | Isaku Yamahata | pci_find_domain(dev->bus), |
1021 | 2ae63bda | Isaku Yamahata | pci_bus_num(dev->bus), dev->devfn, |
1022 | 2ae63bda | Isaku Yamahata | ret); |
1023 | 2ae63bda | Isaku Yamahata | assert(*ret_data); |
1024 | 2ae63bda | Isaku Yamahata | |
1025 | 2ae63bda | Isaku Yamahata | return 0; |
1026 | 2ae63bda | Isaku Yamahata | } |