300 |
300 |
#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
|
301 |
301 |
#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */
|
302 |
302 |
|
303 |
|
/* MSI-X registers (these are at offset PCI_MSIX_FLAGS) */
|
|
303 |
/* MSI-X registers */
|
304 |
304 |
#define PCI_MSIX_FLAGS 2
|
305 |
305 |
#define PCI_MSIX_FLAGS_QSIZE 0x7FF
|
306 |
306 |
#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
|
307 |
307 |
#define PCI_MSIX_FLAGS_MASKALL (1 << 14)
|
308 |
|
#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
|
|
308 |
#define PCI_MSIX_TABLE 4
|
|
309 |
#define PCI_MSIX_PBA 8
|
|
310 |
#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
|
|
311 |
|
|
312 |
/* MSI-X entry's format */
|
|
313 |
#define PCI_MSIX_ENTRY_SIZE 16
|
|
314 |
#define PCI_MSIX_ENTRY_LOWER_ADDR 0
|
|
315 |
#define PCI_MSIX_ENTRY_UPPER_ADDR 4
|
|
316 |
#define PCI_MSIX_ENTRY_DATA 8
|
|
317 |
#define PCI_MSIX_ENTRY_VECTOR_CTRL 12
|
|
318 |
#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
|
309 |
319 |
|
310 |
320 |
/* CompactPCI Hotswap Register */
|
311 |
321 |
|
... | ... | |
365 |
375 |
#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
|
366 |
376 |
#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
|
367 |
377 |
|
|
378 |
/* PCI Bridge Subsystem ID registers */
|
|
379 |
|
|
380 |
#define PCI_SSVID_VENDOR_ID 4 /* PCI-Bridge subsystem vendor id register */
|
|
381 |
#define PCI_SSVID_DEVICE_ID 6 /* PCI-Bridge subsystem device id register */
|
|
382 |
|
368 |
383 |
/* PCI Express capability registers */
|
369 |
384 |
|
370 |
385 |
#define PCI_EXP_FLAGS 2 /* Capabilities register */
|
... | ... | |
420 |
435 |
#define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
|
421 |
436 |
#define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */
|
422 |
437 |
#define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* L1 Clock Power Management */
|
423 |
|
#define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Suprise Down Error Reporting Capable */
|
|
438 |
#define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Surprise Down Error Reporting Capable */
|
424 |
439 |
#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
|
425 |
440 |
#define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */
|
426 |
441 |
#define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */
|
... | ... | |
437 |
452 |
#define PCI_EXP_LNKCTL_LABIE 0x0800 /* Lnk Autonomous Bandwidth Interrupt Enable */
|
438 |
453 |
#define PCI_EXP_LNKSTA 18 /* Link Status */
|
439 |
454 |
#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
|
|
455 |
#define PCI_EXP_LNKSTA_CLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */
|
|
456 |
#define PCI_EXP_LNKSTA_CLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */
|
440 |
457 |
#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Nogotiated Link Width */
|
|
458 |
#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */
|
441 |
459 |
#define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */
|
442 |
460 |
#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */
|
443 |
461 |
#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
|
... | ... | |
486 |
504 |
#define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */
|
487 |
505 |
#define PCI_EXP_RTCAP 30 /* Root Capabilities */
|
488 |
506 |
#define PCI_EXP_RTSTA 32 /* Root Status */
|
|
507 |
#define PCI_EXP_RTSTA_PME 0x10000 /* PME status */
|
|
508 |
#define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */
|
489 |
509 |
#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
|
490 |
510 |
#define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */
|
|
511 |
#define PCI_EXP_DEVCAP2_LTR 0x800 /* Latency tolerance reporting */
|
|
512 |
#define PCI_EXP_OBFF_MASK 0xc0000 /* OBFF support mechanism */
|
|
513 |
#define PCI_EXP_OBFF_MSG 0x40000 /* New message signaling */
|
|
514 |
#define PCI_EXP_OBFF_WAKE 0x80000 /* Re-use WAKE# for OBFF */
|
491 |
515 |
#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
|
492 |
516 |
#define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */
|
|
517 |
#define PCI_EXP_IDO_REQ_EN 0x100 /* ID-based ordering request enable */
|
|
518 |
#define PCI_EXP_IDO_CMP_EN 0x200 /* ID-based ordering completion enable */
|
|
519 |
#define PCI_EXP_LTR_EN 0x400 /* Latency tolerance reporting */
|
|
520 |
#define PCI_EXP_OBFF_MSGA_EN 0x2000 /* OBFF enable with Message type A */
|
|
521 |
#define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */
|
|
522 |
#define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */
|
493 |
523 |
#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
|
494 |
524 |
#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */
|
495 |
525 |
|
... | ... | |
502 |
532 |
#define PCI_EXT_CAP_ID_VC 2
|
503 |
533 |
#define PCI_EXT_CAP_ID_DSN 3
|
504 |
534 |
#define PCI_EXT_CAP_ID_PWR 4
|
|
535 |
#define PCI_EXT_CAP_ID_VNDR 11
|
|
536 |
#define PCI_EXT_CAP_ID_ACS 13
|
505 |
537 |
#define PCI_EXT_CAP_ID_ARI 14
|
506 |
538 |
#define PCI_EXT_CAP_ID_ATS 15
|
507 |
539 |
#define PCI_EXT_CAP_ID_SRIOV 16
|
|
540 |
#define PCI_EXT_CAP_ID_LTR 24
|
508 |
541 |
|
509 |
542 |
/* Advanced Error Reporting */
|
510 |
543 |
#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
|
... | ... | |
556 |
589 |
#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Fatal */
|
557 |
590 |
#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
|
558 |
591 |
#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
|
559 |
|
#define PCI_ERR_ROOT_COR_SRC 52
|
560 |
|
#define PCI_ERR_ROOT_SRC 54
|
|
592 |
#define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */
|
561 |
593 |
|
562 |
594 |
/* Virtual Channel */
|
563 |
595 |
#define PCI_VC_PORT_REG1 4
|
... | ... | |
662 |
694 |
#define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */
|
663 |
695 |
#define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */
|
664 |
696 |
|
|
697 |
#define PCI_LTR_MAX_SNOOP_LAT 0x4
|
|
698 |
#define PCI_LTR_MAX_NOSNOOP_LAT 0x6
|
|
699 |
#define PCI_LTR_VALUE_MASK 0x000003ff
|
|
700 |
#define PCI_LTR_SCALE_MASK 0x00001c00
|
|
701 |
#define PCI_LTR_SCALE_SHIFT 10
|
|
702 |
|
|
703 |
/* Access Control Service */
|
|
704 |
#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
|
|
705 |
#define PCI_ACS_SV 0x01 /* Source Validation */
|
|
706 |
#define PCI_ACS_TB 0x02 /* Translation Blocking */
|
|
707 |
#define PCI_ACS_RR 0x04 /* P2P Request Redirect */
|
|
708 |
#define PCI_ACS_CR 0x08 /* P2P Completion Redirect */
|
|
709 |
#define PCI_ACS_UF 0x10 /* Upstream Forwarding */
|
|
710 |
#define PCI_ACS_EC 0x20 /* P2P Egress Control */
|
|
711 |
#define PCI_ACS_DT 0x40 /* Direct Translated P2P */
|
|
712 |
#define PCI_ACS_CTRL 0x06 /* ACS Control Register */
|
|
713 |
#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */
|
|
714 |
|
665 |
715 |
#endif /* LINUX_PCI_REGS_H */
|