Revision 81486b55 hw/pci_regs.h
b/hw/pci_regs.h | ||
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300 | 300 |
#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ |
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#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */ |
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/* MSI-X registers (these are at offset PCI_MSIX_FLAGS) */
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/* MSI-X registers */ |
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304 | 304 |
#define PCI_MSIX_FLAGS 2 |
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#define PCI_MSIX_FLAGS_QSIZE 0x7FF |
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#define PCI_MSIX_FLAGS_ENABLE (1 << 15) |
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#define PCI_MSIX_FLAGS_MASKALL (1 << 14) |
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#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) |
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#define PCI_MSIX_TABLE 4 |
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#define PCI_MSIX_PBA 8 |
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#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) |
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/* MSI-X entry's format */ |
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#define PCI_MSIX_ENTRY_SIZE 16 |
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#define PCI_MSIX_ENTRY_LOWER_ADDR 0 |
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#define PCI_MSIX_ENTRY_UPPER_ADDR 4 |
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#define PCI_MSIX_ENTRY_DATA 8 |
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#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 |
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#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1 |
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309 | 319 |
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310 | 320 |
/* CompactPCI Hotswap Register */ |
311 | 321 |
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... | ... | |
365 | 375 |
#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ |
366 | 376 |
#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ |
367 | 377 |
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/* PCI Bridge Subsystem ID registers */ |
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#define PCI_SSVID_VENDOR_ID 4 /* PCI-Bridge subsystem vendor id register */ |
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#define PCI_SSVID_DEVICE_ID 6 /* PCI-Bridge subsystem device id register */ |
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368 | 383 |
/* PCI Express capability registers */ |
369 | 384 |
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370 | 385 |
#define PCI_EXP_FLAGS 2 /* Capabilities register */ |
... | ... | |
420 | 435 |
#define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */ |
421 | 436 |
#define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */ |
422 | 437 |
#define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* L1 Clock Power Management */ |
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#define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Suprise Down Error Reporting Capable */ |
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#define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Surprise Down Error Reporting Capable */
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424 | 439 |
#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ |
425 | 440 |
#define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */ |
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#define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */ |
... | ... | |
437 | 452 |
#define PCI_EXP_LNKCTL_LABIE 0x0800 /* Lnk Autonomous Bandwidth Interrupt Enable */ |
438 | 453 |
#define PCI_EXP_LNKSTA 18 /* Link Status */ |
439 | 454 |
#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ |
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#define PCI_EXP_LNKSTA_CLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */ |
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#define PCI_EXP_LNKSTA_CLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */ |
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440 | 457 |
#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Nogotiated Link Width */ |
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#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ |
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441 | 459 |
#define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ |
442 | 460 |
#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ |
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#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ |
... | ... | |
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#define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */ |
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#define PCI_EXP_RTCAP 30 /* Root Capabilities */ |
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#define PCI_EXP_RTSTA 32 /* Root Status */ |
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#define PCI_EXP_RTSTA_PME 0x10000 /* PME status */ |
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#define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */ |
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489 | 509 |
#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ |
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#define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */ |
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#define PCI_EXP_DEVCAP2_LTR 0x800 /* Latency tolerance reporting */ |
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#define PCI_EXP_OBFF_MASK 0xc0000 /* OBFF support mechanism */ |
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#define PCI_EXP_OBFF_MSG 0x40000 /* New message signaling */ |
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#define PCI_EXP_OBFF_WAKE 0x80000 /* Re-use WAKE# for OBFF */ |
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#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ |
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#define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */ |
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#define PCI_EXP_IDO_REQ_EN 0x100 /* ID-based ordering request enable */ |
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#define PCI_EXP_IDO_CMP_EN 0x200 /* ID-based ordering completion enable */ |
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#define PCI_EXP_LTR_EN 0x400 /* Latency tolerance reporting */ |
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#define PCI_EXP_OBFF_MSGA_EN 0x2000 /* OBFF enable with Message type A */ |
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#define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */ |
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#define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ |
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493 | 523 |
#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ |
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#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */ |
495 | 525 |
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... | ... | |
502 | 532 |
#define PCI_EXT_CAP_ID_VC 2 |
503 | 533 |
#define PCI_EXT_CAP_ID_DSN 3 |
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#define PCI_EXT_CAP_ID_PWR 4 |
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#define PCI_EXT_CAP_ID_VNDR 11 |
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#define PCI_EXT_CAP_ID_ACS 13 |
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505 | 537 |
#define PCI_EXT_CAP_ID_ARI 14 |
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#define PCI_EXT_CAP_ID_ATS 15 |
507 | 539 |
#define PCI_EXT_CAP_ID_SRIOV 16 |
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#define PCI_EXT_CAP_ID_LTR 24 |
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508 | 541 |
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509 | 542 |
/* Advanced Error Reporting */ |
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#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ |
... | ... | |
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#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Fatal */ |
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#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ |
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#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ |
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#define PCI_ERR_ROOT_COR_SRC 52 |
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#define PCI_ERR_ROOT_SRC 54 |
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#define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ |
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561 | 593 |
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/* Virtual Channel */ |
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#define PCI_VC_PORT_REG1 4 |
... | ... | |
662 | 694 |
#define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */ |
663 | 695 |
#define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */ |
664 | 696 |
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#define PCI_LTR_MAX_SNOOP_LAT 0x4 |
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#define PCI_LTR_MAX_NOSNOOP_LAT 0x6 |
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#define PCI_LTR_VALUE_MASK 0x000003ff |
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#define PCI_LTR_SCALE_MASK 0x00001c00 |
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#define PCI_LTR_SCALE_SHIFT 10 |
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/* Access Control Service */ |
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#define PCI_ACS_CAP 0x04 /* ACS Capability Register */ |
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#define PCI_ACS_SV 0x01 /* Source Validation */ |
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#define PCI_ACS_TB 0x02 /* Translation Blocking */ |
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#define PCI_ACS_RR 0x04 /* P2P Request Redirect */ |
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#define PCI_ACS_CR 0x08 /* P2P Completion Redirect */ |
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#define PCI_ACS_UF 0x10 /* Upstream Forwarding */ |
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#define PCI_ACS_EC 0x20 /* P2P Egress Control */ |
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#define PCI_ACS_DT 0x40 /* Direct Translated P2P */ |
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#define PCI_ACS_CTRL 0x06 /* ACS Control Register */ |
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#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ |
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665 | 715 |
#endif /* LINUX_PCI_REGS_H */ |
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