Revision 81762d6d target-ppc/cpu.h
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# define TARGET_VIRT_ADDR_SPACE_BITS 64 |
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#endif |
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#define TARGET_PAGE_BITS_16M 24 |
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#else /* defined (TARGET_PPC64) */ |
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/* PowerPC 32 definitions */ |
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#define TARGET_LONG_BITS 32 |
| ... | ... | |
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typedef struct ppc_slb_t ppc_slb_t; |
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struct ppc_slb_t {
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uint64_t tmp64;
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uint32_t tmp;
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uint64_t esid;
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uint64_t vsid;
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}; |
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/* Bits in the SLB ESID word */ |
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#define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL |
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#define SLB_ESID_V 0x0000000008000000ULL /* valid */ |
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/* Bits in the SLB VSID word */ |
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#define SLB_VSID_SHIFT 12 |
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#define SLB_VSID_SSIZE_SHIFT 62 |
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#define SLB_VSID_B 0xc000000000000000ULL |
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#define SLB_VSID_B_256M 0x0000000000000000ULL |
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#define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL |
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#define SLB_VSID_KS 0x0000000000000800ULL |
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#define SLB_VSID_KP 0x0000000000000400ULL |
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#define SLB_VSID_N 0x0000000000000200ULL /* no-execute */ |
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#define SLB_VSID_L 0x0000000000000100ULL |
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#define SLB_VSID_C 0x0000000000000080ULL /* class */ |
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#define SLB_VSID_LP 0x0000000000000030ULL |
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#define SLB_VSID_ATTR 0x0000000000000FFFULL |
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#define SEGMENT_SHIFT_256M 28 |
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#define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1)) |
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/*****************************************************************************/ |
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/* Machine state register bits definition */ |
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#define MSR_SF 63 /* Sixty-four-bit mode hflags */ |
| ... | ... | |
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void ppc_store_asr (CPUPPCState *env, target_ulong value); |
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target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr); |
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target_ulong ppc_load_sr (CPUPPCState *env, int sr_nr); |
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void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
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int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
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#endif /* defined(TARGET_PPC64) */ |
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void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value); |
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#endif /* !defined(CONFIG_USER_ONLY) */ |
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