Revision 819385c5
| b/Makefile.target | ||
|---|---|---|
| 305 | 305 |
VL_OBJS+= cirrus_vga.o parallel.o |
| 306 | 306 |
VL_OBJS+= magic-load.o |
| 307 | 307 |
else |
| 308 |
VL_OBJS+= sun4m.o tcx.o lance.o iommu.o m48t08.o magic-load.o slavio_intctl.o slavio_timer.o slavio_serial.o slavio_misc.o fdc.o esp.o |
|
| 308 |
VL_OBJS+= sun4m.o tcx.o lance.o iommu.o m48t59.o magic-load.o slavio_intctl.o |
|
| 309 |
VL_OBJS+= slavio_timer.o slavio_serial.o slavio_misc.o fdc.o esp.o |
|
| 309 | 310 |
endif |
| 310 | 311 |
endif |
| 311 | 312 |
ifdef CONFIG_GDBSTUB |
| /dev/null | ||
|---|---|---|
| 1 |
/* |
|
| 2 |
* QEMU M48T08 NVRAM emulation for Sparc platform |
|
| 3 |
* |
|
| 4 |
* Copyright (c) 2003-2004 Jocelyn Mayer |
|
| 5 |
* |
|
| 6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
|
| 7 |
* of this software and associated documentation files (the "Software"), to deal |
|
| 8 |
* in the Software without restriction, including without limitation the rights |
|
| 9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
|
| 10 |
* copies of the Software, and to permit persons to whom the Software is |
|
| 11 |
* furnished to do so, subject to the following conditions: |
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| 12 |
* |
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| 13 |
* The above copyright notice and this permission notice shall be included in |
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| 14 |
* all copies or substantial portions of the Software. |
|
| 15 |
* |
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| 16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
|
| 20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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| 21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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| 22 |
* THE SOFTWARE. |
|
| 23 |
*/ |
|
| 24 |
#include "vl.h" |
|
| 25 |
#include "m48t08.h" |
|
| 26 |
|
|
| 27 |
//#define DEBUG_NVRAM |
|
| 28 |
|
|
| 29 |
#if defined(DEBUG_NVRAM) |
|
| 30 |
#define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
|
|
| 31 |
#else |
|
| 32 |
#define NVRAM_PRINTF(fmt, args...) do { } while (0)
|
|
| 33 |
#endif |
|
| 34 |
|
|
| 35 |
#define NVRAM_MAX_MEM 0x1ff0 |
|
| 36 |
#define NVRAM_MAXADDR 0x1fff |
|
| 37 |
|
|
| 38 |
struct m48t08_t {
|
|
| 39 |
/* RTC management */ |
|
| 40 |
time_t time_offset; |
|
| 41 |
time_t stop_time; |
|
| 42 |
/* NVRAM storage */ |
|
| 43 |
uint8_t *buffer; |
|
| 44 |
}; |
|
| 45 |
|
|
| 46 |
/* Fake timer functions */ |
|
| 47 |
/* Generic helpers for BCD */ |
|
| 48 |
static inline uint8_t toBCD (uint8_t value) |
|
| 49 |
{
|
|
| 50 |
return (((value / 10) % 10) << 4) | (value % 10); |
|
| 51 |
} |
|
| 52 |
|
|
| 53 |
static inline uint8_t fromBCD (uint8_t BCD) |
|
| 54 |
{
|
|
| 55 |
return ((BCD >> 4) * 10) + (BCD & 0x0F); |
|
| 56 |
} |
|
| 57 |
|
|
| 58 |
/* RTC management helpers */ |
|
| 59 |
static void get_time (m48t08_t *NVRAM, struct tm *tm) |
|
| 60 |
{
|
|
| 61 |
time_t t; |
|
| 62 |
|
|
| 63 |
t = time(NULL) + NVRAM->time_offset; |
|
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#ifdef _WIN32 |
|
| 65 |
memcpy(tm,localtime(&t),sizeof(*tm)); |
|
| 66 |
#else |
|
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localtime_r (&t, tm) ; |
|
| 68 |
#endif |
|
| 69 |
} |
|
| 70 |
|
|
| 71 |
static void set_time (m48t08_t *NVRAM, struct tm *tm) |
|
| 72 |
{
|
|
| 73 |
time_t now, new_time; |
|
| 74 |
|
|
| 75 |
new_time = mktime(tm); |
|
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now = time(NULL); |
|
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NVRAM->time_offset = new_time - now; |
|
| 78 |
} |
|
| 79 |
|
|
| 80 |
/* Direct access to NVRAM */ |
|
| 81 |
void m48t08_write (m48t08_t *NVRAM, uint32_t addr, uint8_t val) |
|
| 82 |
{
|
|
| 83 |
struct tm tm; |
|
| 84 |
int tmp; |
|
| 85 |
|
|
| 86 |
addr &= NVRAM_MAXADDR; |
|
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switch (addr) {
|
|
| 88 |
case 0x1FF8: |
|
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/* control */ |
|
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NVRAM->buffer[0x1FF8] = (val & ~0xA0) | 0x90; |
|
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break; |
|
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case 0x1FF9: |
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/* seconds (BCD) */ |
|
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tmp = fromBCD(val & 0x7F); |
|
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if (tmp >= 0 && tmp <= 59) {
|
|
| 96 |
get_time(NVRAM, &tm); |
|
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tm.tm_sec = tmp; |
|
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set_time(NVRAM, &tm); |
|
| 99 |
} |
|
| 100 |
if ((val & 0x80) ^ (NVRAM->buffer[0x1FF9] & 0x80)) {
|
|
| 101 |
if (val & 0x80) {
|
|
| 102 |
NVRAM->stop_time = time(NULL); |
|
| 103 |
} else {
|
|
| 104 |
NVRAM->time_offset += NVRAM->stop_time - time(NULL); |
|
| 105 |
NVRAM->stop_time = 0; |
|
| 106 |
} |
|
| 107 |
} |
|
| 108 |
NVRAM->buffer[0x1FF9] = val & 0x80; |
|
| 109 |
break; |
|
| 110 |
case 0x1FFA: |
|
| 111 |
/* minutes (BCD) */ |
|
| 112 |
tmp = fromBCD(val & 0x7F); |
|
| 113 |
if (tmp >= 0 && tmp <= 59) {
|
|
| 114 |
get_time(NVRAM, &tm); |
|
| 115 |
tm.tm_min = tmp; |
|
| 116 |
set_time(NVRAM, &tm); |
|
| 117 |
} |
|
| 118 |
break; |
|
| 119 |
case 0x1FFB: |
|
| 120 |
/* hours (BCD) */ |
|
| 121 |
tmp = fromBCD(val & 0x3F); |
|
| 122 |
if (tmp >= 0 && tmp <= 23) {
|
|
| 123 |
get_time(NVRAM, &tm); |
|
| 124 |
tm.tm_hour = tmp; |
|
| 125 |
set_time(NVRAM, &tm); |
|
| 126 |
} |
|
| 127 |
break; |
|
| 128 |
case 0x1FFC: |
|
| 129 |
/* day of the week / century */ |
|
| 130 |
tmp = fromBCD(val & 0x07); |
|
| 131 |
get_time(NVRAM, &tm); |
|
| 132 |
tm.tm_wday = tmp; |
|
| 133 |
set_time(NVRAM, &tm); |
|
| 134 |
NVRAM->buffer[0x1FFC] = val & 0x40; |
|
| 135 |
break; |
|
| 136 |
case 0x1FFD: |
|
| 137 |
/* date */ |
|
| 138 |
tmp = fromBCD(val & 0x1F); |
|
| 139 |
if (tmp != 0) {
|
|
| 140 |
get_time(NVRAM, &tm); |
|
| 141 |
tm.tm_mday = tmp; |
|
| 142 |
set_time(NVRAM, &tm); |
|
| 143 |
} |
|
| 144 |
break; |
|
| 145 |
case 0x1FFE: |
|
| 146 |
/* month */ |
|
| 147 |
tmp = fromBCD(val & 0x1F); |
|
| 148 |
if (tmp >= 1 && tmp <= 12) {
|
|
| 149 |
get_time(NVRAM, &tm); |
|
| 150 |
tm.tm_mon = tmp - 1; |
|
| 151 |
set_time(NVRAM, &tm); |
|
| 152 |
} |
|
| 153 |
break; |
|
| 154 |
case 0x1FFF: |
|
| 155 |
/* year */ |
|
| 156 |
tmp = fromBCD(val); |
|
| 157 |
if (tmp >= 0 && tmp <= 99) {
|
|
| 158 |
get_time(NVRAM, &tm); |
|
| 159 |
tm.tm_year = fromBCD(val); |
|
| 160 |
set_time(NVRAM, &tm); |
|
| 161 |
} |
|
| 162 |
break; |
|
| 163 |
default: |
|
| 164 |
NVRAM->buffer[addr] = val & 0xFF; |
|
| 165 |
break; |
|
| 166 |
} |
|
| 167 |
} |
|
| 168 |
|
|
| 169 |
uint8_t m48t08_read (m48t08_t *NVRAM, uint32_t addr) |
|
| 170 |
{
|
|
| 171 |
struct tm tm; |
|
| 172 |
uint8_t retval = 0xFF; |
|
| 173 |
|
|
| 174 |
addr &= NVRAM_MAXADDR; |
|
| 175 |
switch (addr) {
|
|
| 176 |
case 0x1FF8: |
|
| 177 |
/* control */ |
|
| 178 |
goto do_read; |
|
| 179 |
case 0x1FF9: |
|
| 180 |
/* seconds (BCD) */ |
|
| 181 |
get_time(NVRAM, &tm); |
|
| 182 |
retval = (NVRAM->buffer[0x1FF9] & 0x80) | toBCD(tm.tm_sec); |
|
| 183 |
break; |
|
| 184 |
case 0x1FFA: |
|
| 185 |
/* minutes (BCD) */ |
|
| 186 |
get_time(NVRAM, &tm); |
|
| 187 |
retval = toBCD(tm.tm_min); |
|
| 188 |
break; |
|
| 189 |
case 0x1FFB: |
|
| 190 |
/* hours (BCD) */ |
|
| 191 |
get_time(NVRAM, &tm); |
|
| 192 |
retval = toBCD(tm.tm_hour); |
|
| 193 |
break; |
|
| 194 |
case 0x1FFC: |
|
| 195 |
/* day of the week / century */ |
|
| 196 |
get_time(NVRAM, &tm); |
|
| 197 |
retval = NVRAM->buffer[0x1FFC] | tm.tm_wday; |
|
| 198 |
break; |
|
| 199 |
case 0x1FFD: |
|
| 200 |
/* date */ |
|
| 201 |
get_time(NVRAM, &tm); |
|
| 202 |
retval = toBCD(tm.tm_mday); |
|
| 203 |
break; |
|
| 204 |
case 0x1FFE: |
|
| 205 |
/* month */ |
|
| 206 |
get_time(NVRAM, &tm); |
|
| 207 |
retval = toBCD(tm.tm_mon + 1); |
|
| 208 |
break; |
|
| 209 |
case 0x1FFF: |
|
| 210 |
/* year */ |
|
| 211 |
get_time(NVRAM, &tm); |
|
| 212 |
retval = toBCD(tm.tm_year); |
|
| 213 |
break; |
|
| 214 |
default: |
|
| 215 |
do_read: |
|
| 216 |
retval = NVRAM->buffer[addr]; |
|
| 217 |
break; |
|
| 218 |
} |
|
| 219 |
return retval; |
|
| 220 |
} |
|
| 221 |
|
|
| 222 |
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
|
| 223 |
{
|
|
| 224 |
m48t08_t *NVRAM = opaque; |
|
| 225 |
|
|
| 226 |
m48t08_write(NVRAM, addr, value); |
|
| 227 |
} |
|
| 228 |
|
|
| 229 |
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
|
| 230 |
{
|
|
| 231 |
m48t08_t *NVRAM = opaque; |
|
| 232 |
|
|
| 233 |
m48t08_write(NVRAM, addr, value); |
|
| 234 |
m48t08_write(NVRAM, addr + 1, value >> 8); |
|
| 235 |
} |
|
| 236 |
|
|
| 237 |
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
|
| 238 |
{
|
|
| 239 |
m48t08_t *NVRAM = opaque; |
|
| 240 |
|
|
| 241 |
m48t08_write(NVRAM, addr, value); |
|
| 242 |
m48t08_write(NVRAM, addr + 1, value >> 8); |
|
| 243 |
m48t08_write(NVRAM, addr + 2, value >> 16); |
|
| 244 |
m48t08_write(NVRAM, addr + 3, value >> 24); |
|
| 245 |
} |
|
| 246 |
|
|
| 247 |
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) |
|
| 248 |
{
|
|
| 249 |
m48t08_t *NVRAM = opaque; |
|
| 250 |
uint32_t retval = 0; |
|
| 251 |
|
|
| 252 |
retval = m48t08_read(NVRAM, addr); |
|
| 253 |
return retval; |
|
| 254 |
} |
|
| 255 |
|
|
| 256 |
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) |
|
| 257 |
{
|
|
| 258 |
m48t08_t *NVRAM = opaque; |
|
| 259 |
uint32_t retval = 0; |
|
| 260 |
|
|
| 261 |
retval = m48t08_read(NVRAM, addr) << 8; |
|
| 262 |
retval |= m48t08_read(NVRAM, addr + 1); |
|
| 263 |
return retval; |
|
| 264 |
} |
|
| 265 |
|
|
| 266 |
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) |
|
| 267 |
{
|
|
| 268 |
m48t08_t *NVRAM = opaque; |
|
| 269 |
uint32_t retval = 0; |
|
| 270 |
|
|
| 271 |
retval = m48t08_read(NVRAM, addr) << 24; |
|
| 272 |
retval |= m48t08_read(NVRAM, addr + 1) << 16; |
|
| 273 |
retval |= m48t08_read(NVRAM, addr + 2) << 8; |
|
| 274 |
retval |= m48t08_read(NVRAM, addr + 3); |
|
| 275 |
return retval; |
|
| 276 |
} |
|
| 277 |
|
|
| 278 |
static CPUWriteMemoryFunc *nvram_write[] = {
|
|
| 279 |
&nvram_writeb, |
|
| 280 |
&nvram_writew, |
|
| 281 |
&nvram_writel, |
|
| 282 |
}; |
|
| 283 |
|
|
| 284 |
static CPUReadMemoryFunc *nvram_read[] = {
|
|
| 285 |
&nvram_readb, |
|
| 286 |
&nvram_readw, |
|
| 287 |
&nvram_readl, |
|
| 288 |
}; |
|
| 289 |
|
|
| 290 |
static void nvram_save(QEMUFile *f, void *opaque) |
|
| 291 |
{
|
|
| 292 |
m48t08_t *s = opaque; |
|
| 293 |
|
|
| 294 |
qemu_put_be32s(f, (uint32_t *)&s->time_offset); |
|
| 295 |
qemu_put_be32s(f, (uint32_t *)&s->stop_time); |
|
| 296 |
qemu_put_buffer(f, s->buffer, 0x2000); |
|
| 297 |
} |
|
| 298 |
|
|
| 299 |
static int nvram_load(QEMUFile *f, void *opaque, int version_id) |
|
| 300 |
{
|
|
| 301 |
m48t08_t *s = opaque; |
|
| 302 |
|
|
| 303 |
if (version_id != 1) |
|
| 304 |
return -EINVAL; |
|
| 305 |
|
|
| 306 |
qemu_get_be32s(f, (uint32_t *)&s->time_offset); |
|
| 307 |
qemu_get_be32s(f, (uint32_t *)&s->stop_time); |
|
| 308 |
qemu_get_buffer(f, s->buffer, 0x2000); |
|
| 309 |
return 0; |
|
| 310 |
} |
|
| 311 |
|
|
| 312 |
static void m48t08_reset(void *opaque) |
|
| 313 |
{
|
|
| 314 |
m48t08_t *s = opaque; |
|
| 315 |
|
|
| 316 |
s->time_offset = 0; |
|
| 317 |
s->stop_time = 0; |
|
| 318 |
} |
|
| 319 |
|
|
| 320 |
|
|
| 321 |
/* Initialisation routine */ |
|
| 322 |
m48t08_t *m48t08_init(uint32_t mem_base, uint16_t size) |
|
| 323 |
{
|
|
| 324 |
m48t08_t *s; |
|
| 325 |
int mem_index; |
|
| 326 |
|
|
| 327 |
s = qemu_mallocz(sizeof(m48t08_t)); |
|
| 328 |
if (!s) |
|
| 329 |
return NULL; |
|
| 330 |
s->buffer = qemu_mallocz(size); |
|
| 331 |
if (!s->buffer) {
|
|
| 332 |
qemu_free(s); |
|
| 333 |
return NULL; |
|
| 334 |
} |
|
| 335 |
if (mem_base != 0) {
|
|
| 336 |
mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s); |
|
| 337 |
cpu_register_physical_memory(mem_base, 0x2000, mem_index); |
|
| 338 |
} |
|
| 339 |
|
|
| 340 |
register_savevm("nvram", mem_base, 1, nvram_save, nvram_load, s);
|
|
| 341 |
qemu_register_reset(m48t08_reset, s); |
|
| 342 |
return s; |
|
| 343 |
} |
|
| 344 |
|
|
| 345 |
#if 0 |
|
| 346 |
struct idprom |
|
| 347 |
{
|
|
| 348 |
unsigned char id_format; /* Format identifier (always 0x01) */ |
|
| 349 |
unsigned char id_machtype; /* Machine type */ |
|
| 350 |
unsigned char id_ethaddr[6]; /* Hardware ethernet address */ |
|
| 351 |
long id_date; /* Date of manufacture */ |
|
| 352 |
unsigned int id_sernum:24; /* Unique serial number */ |
|
| 353 |
unsigned char id_cksum; /* Checksum - xor of the data bytes */ |
|
| 354 |
unsigned char reserved[16]; |
|
| 355 |
}; |
|
| 356 |
#endif |
|
| /dev/null | ||
|---|---|---|
| 1 |
#if !defined (__M48T08_H__) |
|
| 2 |
#define __M48T08_H__ |
|
| 3 |
|
|
| 4 |
typedef struct m48t08_t m48t08_t; |
|
| 5 |
|
|
| 6 |
void m48t08_write (m48t08_t *NVRAM, uint32_t addr, uint8_t val); |
|
| 7 |
uint8_t m48t08_read (m48t08_t *NVRAM, uint32_t addr); |
|
| 8 |
m48t08_t *m48t08_init(uint32_t mem_base, uint16_t size); |
|
| 9 |
|
|
| 10 |
#endif /* !defined (__M48T08_H__) */ |
|
| b/hw/m48t59.c | ||
|---|---|---|
| 1 | 1 |
/* |
| 2 |
* QEMU M48T59 NVRAM emulation for PPC PREP platform
|
|
| 2 |
* QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
|
|
| 3 | 3 |
* |
| 4 |
* Copyright (c) 2003-2004 Jocelyn Mayer
|
|
| 4 |
* Copyright (c) 2003-2005 Jocelyn Mayer
|
|
| 5 | 5 |
* |
| 6 | 6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | 7 |
* of this software and associated documentation files (the "Software"), to deal |
| ... | ... | |
| 32 | 32 |
#define NVRAM_PRINTF(fmt, args...) do { } while (0)
|
| 33 | 33 |
#endif |
| 34 | 34 |
|
| 35 |
/* |
|
| 36 |
* The M48T08 and M48T59 chips are very similar. The newer '59 has |
|
| 37 |
* alarm and a watchdog timer and related control registers. In the |
|
| 38 |
* PPC platform there is also a nvram lock function. |
|
| 39 |
*/ |
|
| 35 | 40 |
struct m48t59_t {
|
| 41 |
/* Model parameters */ |
|
| 42 |
int type; // 8 = m48t08, 59 = m48t59 |
|
| 36 | 43 |
/* Hardware parameters */ |
| 37 | 44 |
int IRQ; |
| 38 | 45 |
int mem_index; |
| ... | ... | |
| 188 | 195 |
} |
| 189 | 196 |
|
| 190 | 197 |
/* Direct access to NVRAM */ |
| 191 |
void m48t59_write (m48t59_t *NVRAM, uint32_t val) |
|
| 198 |
void m48t59_write (m48t59_t *NVRAM, uint32_t addr, uint32_t val)
|
|
| 192 | 199 |
{
|
| 193 | 200 |
struct tm tm; |
| 194 | 201 |
int tmp; |
| 195 | 202 |
|
| 196 |
if (NVRAM->addr > 0x1FF8 && NVRAM->addr < 0x2000) |
|
| 197 |
NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, NVRAM->addr, val);
|
|
| 198 |
switch (NVRAM->addr) {
|
|
| 203 |
if (addr > 0x1FF8 && addr < 0x2000) |
|
| 204 |
NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
|
|
| 205 |
if (NVRAM->type == 8 && |
|
| 206 |
(addr >= 0x1ff0 && addr <= 0x1ff7)) |
|
| 207 |
goto do_write; |
|
| 208 |
switch (addr) {
|
|
| 199 | 209 |
case 0x1FF0: |
| 200 | 210 |
/* flags register : read-only */ |
| 201 | 211 |
break; |
| ... | ... | |
| 204 | 214 |
break; |
| 205 | 215 |
case 0x1FF2: |
| 206 | 216 |
/* alarm seconds */ |
| 207 |
tmp = fromBCD(val & 0x7F);
|
|
| 208 |
if (tmp >= 0 && tmp <= 59) {
|
|
| 209 |
get_alarm(NVRAM, &tm);
|
|
| 210 |
tm.tm_sec = tmp;
|
|
| 211 |
NVRAM->buffer[0x1FF2] = val;
|
|
| 212 |
set_alarm(NVRAM, &tm);
|
|
| 213 |
}
|
|
| 217 |
tmp = fromBCD(val & 0x7F);
|
|
| 218 |
if (tmp >= 0 && tmp <= 59) {
|
|
| 219 |
get_alarm(NVRAM, &tm);
|
|
| 220 |
tm.tm_sec = tmp;
|
|
| 221 |
NVRAM->buffer[0x1FF2] = val;
|
|
| 222 |
set_alarm(NVRAM, &tm);
|
|
| 223 |
}
|
|
| 214 | 224 |
break; |
| 215 | 225 |
case 0x1FF3: |
| 216 | 226 |
/* alarm minutes */ |
| 217 |
tmp = fromBCD(val & 0x7F);
|
|
| 218 |
if (tmp >= 0 && tmp <= 59) {
|
|
| 219 |
get_alarm(NVRAM, &tm);
|
|
| 220 |
tm.tm_min = tmp;
|
|
| 221 |
NVRAM->buffer[0x1FF3] = val;
|
|
| 222 |
set_alarm(NVRAM, &tm);
|
|
| 223 |
}
|
|
| 227 |
tmp = fromBCD(val & 0x7F);
|
|
| 228 |
if (tmp >= 0 && tmp <= 59) {
|
|
| 229 |
get_alarm(NVRAM, &tm);
|
|
| 230 |
tm.tm_min = tmp;
|
|
| 231 |
NVRAM->buffer[0x1FF3] = val;
|
|
| 232 |
set_alarm(NVRAM, &tm);
|
|
| 233 |
}
|
|
| 224 | 234 |
break; |
| 225 | 235 |
case 0x1FF4: |
| 226 | 236 |
/* alarm hours */ |
| 227 |
tmp = fromBCD(val & 0x3F);
|
|
| 228 |
if (tmp >= 0 && tmp <= 23) {
|
|
| 229 |
get_alarm(NVRAM, &tm);
|
|
| 230 |
tm.tm_hour = tmp;
|
|
| 231 |
NVRAM->buffer[0x1FF4] = val;
|
|
| 232 |
set_alarm(NVRAM, &tm);
|
|
| 233 |
}
|
|
| 237 |
tmp = fromBCD(val & 0x3F);
|
|
| 238 |
if (tmp >= 0 && tmp <= 23) {
|
|
| 239 |
get_alarm(NVRAM, &tm);
|
|
| 240 |
tm.tm_hour = tmp;
|
|
| 241 |
NVRAM->buffer[0x1FF4] = val;
|
|
| 242 |
set_alarm(NVRAM, &tm);
|
|
| 243 |
}
|
|
| 234 | 244 |
break; |
| 235 | 245 |
case 0x1FF5: |
| 236 | 246 |
/* alarm date */ |
| 237 |
tmp = fromBCD(val & 0x1F);
|
|
| 238 |
if (tmp != 0) {
|
|
| 239 |
get_alarm(NVRAM, &tm);
|
|
| 240 |
tm.tm_mday = tmp;
|
|
| 241 |
NVRAM->buffer[0x1FF5] = val;
|
|
| 242 |
set_alarm(NVRAM, &tm);
|
|
| 243 |
}
|
|
| 247 |
tmp = fromBCD(val & 0x1F);
|
|
| 248 |
if (tmp != 0) {
|
|
| 249 |
get_alarm(NVRAM, &tm);
|
|
| 250 |
tm.tm_mday = tmp;
|
|
| 251 |
NVRAM->buffer[0x1FF5] = val;
|
|
| 252 |
set_alarm(NVRAM, &tm);
|
|
| 253 |
}
|
|
| 244 | 254 |
break; |
| 245 | 255 |
case 0x1FF6: |
| 246 | 256 |
/* interrupts */ |
| 247 |
NVRAM->buffer[0x1FF6] = val;
|
|
| 257 |
NVRAM->buffer[0x1FF6] = val;
|
|
| 248 | 258 |
break; |
| 249 | 259 |
case 0x1FF7: |
| 250 | 260 |
/* watchdog */ |
| 251 |
NVRAM->buffer[0x1FF7] = val;
|
|
| 252 |
set_up_watchdog(NVRAM, val);
|
|
| 261 |
NVRAM->buffer[0x1FF7] = val;
|
|
| 262 |
set_up_watchdog(NVRAM, val);
|
|
| 253 | 263 |
break; |
| 254 | 264 |
case 0x1FF8: |
| 255 | 265 |
/* control */ |
| ... | ... | |
| 328 | 338 |
break; |
| 329 | 339 |
default: |
| 330 | 340 |
/* Check lock registers state */ |
| 331 |
if (NVRAM->addr >= 0x20 && NVRAM->addr <= 0x2F && (NVRAM->lock & 1))
|
|
| 341 |
if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
|
|
| 332 | 342 |
break; |
| 333 |
if (NVRAM->addr >= 0x30 && NVRAM->addr <= 0x3F && (NVRAM->lock & 2))
|
|
| 343 |
if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
|
|
| 334 | 344 |
break; |
| 335 |
if (NVRAM->addr < 0x1FF0 ||
|
|
| 336 |
(NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
|
|
| 337 |
NVRAM->buffer[NVRAM->addr] = val & 0xFF;
|
|
| 345 |
do_write:
|
|
| 346 |
if (addr < NVRAM->size) {
|
|
| 347 |
NVRAM->buffer[addr] = val & 0xFF; |
|
| 338 | 348 |
} |
| 339 | 349 |
break; |
| 340 | 350 |
} |
| 341 | 351 |
} |
| 342 | 352 |
|
| 343 |
uint32_t m48t59_read (m48t59_t *NVRAM) |
|
| 353 |
uint32_t m48t59_read (m48t59_t *NVRAM, uint32_t addr)
|
|
| 344 | 354 |
{
|
| 345 | 355 |
struct tm tm; |
| 346 | 356 |
uint32_t retval = 0xFF; |
| 347 | 357 |
|
| 348 |
switch (NVRAM->addr) {
|
|
| 358 |
if (NVRAM->type == 8 && |
|
| 359 |
(addr >= 0x1ff0 && addr <= 0x1ff7)) |
|
| 360 |
goto do_read; |
|
| 361 |
switch (addr) {
|
|
| 349 | 362 |
case 0x1FF0: |
| 350 | 363 |
/* flags register */ |
| 351 | 364 |
goto do_read; |
| ... | ... | |
| 412 | 425 |
break; |
| 413 | 426 |
default: |
| 414 | 427 |
/* Check lock registers state */ |
| 415 |
if (NVRAM->addr >= 0x20 && NVRAM->addr <= 0x2F && (NVRAM->lock & 1))
|
|
| 428 |
if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
|
|
| 416 | 429 |
break; |
| 417 |
if (NVRAM->addr >= 0x30 && NVRAM->addr <= 0x3F && (NVRAM->lock & 2))
|
|
| 430 |
if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
|
|
| 418 | 431 |
break; |
| 419 |
if (NVRAM->addr < 0x1FF0 || |
|
| 420 |
(NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
|
|
| 421 |
do_read: |
|
| 422 |
retval = NVRAM->buffer[NVRAM->addr]; |
|
| 432 |
do_read: |
|
| 433 |
if (addr < NVRAM->size) {
|
|
| 434 |
retval = NVRAM->buffer[addr]; |
|
| 423 | 435 |
} |
| 424 | 436 |
break; |
| 425 | 437 |
} |
| 426 |
if (NVRAM->addr > 0x1FF9 && NVRAM->addr < 0x2000)
|
|
| 427 |
NVRAM_PRINTF("0x%08x <= 0x%08x\n", NVRAM->addr, retval);
|
|
| 438 |
if (addr > 0x1FF9 && addr < 0x2000)
|
|
| 439 |
NVRAM_PRINTF("0x%08x <= 0x%08x\n", addr, retval);
|
|
| 428 | 440 |
|
| 429 | 441 |
return retval; |
| 430 | 442 |
} |
| ... | ... | |
| 456 | 468 |
NVRAM->addr |= val << 8; |
| 457 | 469 |
break; |
| 458 | 470 |
case 3: |
| 459 |
m48t59_write(NVRAM, val); |
|
| 471 |
m48t59_write(NVRAM, val, NVRAM->addr);
|
|
| 460 | 472 |
NVRAM->addr = 0x0000; |
| 461 | 473 |
break; |
| 462 | 474 |
default: |
| ... | ... | |
| 472 | 484 |
addr -= NVRAM->io_base; |
| 473 | 485 |
switch (addr) {
|
| 474 | 486 |
case 3: |
| 475 |
retval = m48t59_read(NVRAM); |
|
| 487 |
retval = m48t59_read(NVRAM, NVRAM->addr);
|
|
| 476 | 488 |
break; |
| 477 | 489 |
default: |
| 478 | 490 |
retval = -1; |
| ... | ... | |
| 488 | 500 |
m48t59_t *NVRAM = opaque; |
| 489 | 501 |
|
| 490 | 502 |
addr -= NVRAM->mem_base; |
| 491 |
if (addr < 0x1FF0) |
|
| 492 |
NVRAM->buffer[addr] = value; |
|
| 503 |
m48t59_write(NVRAM, addr, value & 0xff); |
|
| 493 | 504 |
} |
| 494 | 505 |
|
| 495 | 506 |
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
| ... | ... | |
| 497 | 508 |
m48t59_t *NVRAM = opaque; |
| 498 | 509 |
|
| 499 | 510 |
addr -= NVRAM->mem_base; |
| 500 |
if (addr < 0x1FF0) {
|
|
| 501 |
NVRAM->buffer[addr] = value >> 8; |
|
| 502 |
NVRAM->buffer[addr + 1] = value; |
|
| 503 |
} |
|
| 511 |
m48t59_write(NVRAM, addr, (value >> 8) & 0xff); |
|
| 512 |
m48t59_write(NVRAM, addr + 1, value & 0xff); |
|
| 504 | 513 |
} |
| 505 | 514 |
|
| 506 | 515 |
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
| ... | ... | |
| 508 | 517 |
m48t59_t *NVRAM = opaque; |
| 509 | 518 |
|
| 510 | 519 |
addr -= NVRAM->mem_base; |
| 511 |
if (addr < 0x1FF0) {
|
|
| 512 |
NVRAM->buffer[addr] = value >> 24; |
|
| 513 |
NVRAM->buffer[addr + 1] = value >> 16; |
|
| 514 |
NVRAM->buffer[addr + 2] = value >> 8; |
|
| 515 |
NVRAM->buffer[addr + 3] = value; |
|
| 516 |
} |
|
| 520 |
m48t59_write(NVRAM, addr, (value >> 24) & 0xff); |
|
| 521 |
m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); |
|
| 522 |
m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); |
|
| 523 |
m48t59_write(NVRAM, addr + 3, value & 0xff); |
|
| 517 | 524 |
} |
| 518 | 525 |
|
| 519 | 526 |
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) |
| 520 | 527 |
{
|
| 521 | 528 |
m48t59_t *NVRAM = opaque; |
| 522 |
uint32_t retval = 0;
|
|
| 529 |
uint32_t retval; |
|
| 523 | 530 |
|
| 524 | 531 |
addr -= NVRAM->mem_base; |
| 525 |
if (addr < 0x1FF0) |
|
| 526 |
retval = NVRAM->buffer[addr]; |
|
| 527 |
|
|
| 532 |
retval = m48t59_read(NVRAM, addr); |
|
| 528 | 533 |
return retval; |
| 529 | 534 |
} |
| 530 | 535 |
|
| 531 | 536 |
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) |
| 532 | 537 |
{
|
| 533 | 538 |
m48t59_t *NVRAM = opaque; |
| 534 |
uint32_t retval = 0;
|
|
| 539 |
uint32_t retval; |
|
| 535 | 540 |
|
| 536 | 541 |
addr -= NVRAM->mem_base; |
| 537 |
if (addr < 0x1FF0) {
|
|
| 538 |
retval = NVRAM->buffer[addr] << 8; |
|
| 539 |
retval |= NVRAM->buffer[addr + 1]; |
|
| 540 |
} |
|
| 541 |
|
|
| 542 |
retval = m48t59_read(NVRAM, addr) << 8; |
|
| 543 |
retval |= m48t59_read(NVRAM, addr + 1); |
|
| 542 | 544 |
return retval; |
| 543 | 545 |
} |
| 544 | 546 |
|
| 545 | 547 |
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) |
| 546 | 548 |
{
|
| 547 | 549 |
m48t59_t *NVRAM = opaque; |
| 548 |
uint32_t retval = 0; |
|
| 549 |
|
|
| 550 |
addr -= NVRAM->mem_base; |
|
| 551 |
if (addr < 0x1FF0) {
|
|
| 552 |
retval = NVRAM->buffer[addr] << 24; |
|
| 553 |
retval |= NVRAM->buffer[addr + 1] << 16; |
|
| 554 |
retval |= NVRAM->buffer[addr + 2] << 8; |
|
| 555 |
retval |= NVRAM->buffer[addr + 3]; |
|
| 556 |
} |
|
| 550 |
uint32_t retval; |
|
| 557 | 551 |
|
| 552 |
addr -= NVRAM->mem_base; |
|
| 553 |
retval = m48t59_read(NVRAM, addr) << 24; |
|
| 554 |
retval |= m48t59_read(NVRAM, addr + 1) << 16; |
|
| 555 |
retval |= m48t59_read(NVRAM, addr + 2) << 8; |
|
| 556 |
retval |= m48t59_read(NVRAM, addr + 3); |
|
| 558 | 557 |
return retval; |
| 559 | 558 |
} |
| 560 | 559 |
|
| ... | ... | |
| 569 | 568 |
&nvram_readw, |
| 570 | 569 |
&nvram_readl, |
| 571 | 570 |
}; |
| 571 |
|
|
| 572 | 572 |
/* Initialisation routine */ |
| 573 |
m48t59_t *m48t59_init (int IRQ, uint32_t mem_base, |
|
| 574 |
uint32_t io_base, uint16_t size) |
|
| 573 |
m48t59_t *m48t59_init (int IRQ, target_ulong mem_base, |
|
| 574 |
uint32_t io_base, uint16_t size, |
|
| 575 |
int type) |
|
| 575 | 576 |
{
|
| 576 | 577 |
m48t59_t *s; |
| 577 | 578 |
|
| ... | ... | |
| 588 | 589 |
s->mem_base = mem_base; |
| 589 | 590 |
s->io_base = io_base; |
| 590 | 591 |
s->addr = 0; |
| 591 |
register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s); |
|
| 592 |
register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s); |
|
| 592 |
s->type = type; |
|
| 593 |
if (io_base != 0) {
|
|
| 594 |
register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s); |
|
| 595 |
register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s); |
|
| 596 |
} |
|
| 593 | 597 |
if (mem_base != 0) {
|
| 594 | 598 |
s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s); |
| 595 | 599 |
cpu_register_physical_memory(mem_base, 0x4000, s->mem_index); |
| 596 | 600 |
} |
| 597 |
s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s); |
|
| 598 |
s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s); |
|
| 601 |
if (type == 59) {
|
|
| 602 |
s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s); |
|
| 603 |
s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s); |
|
| 604 |
} |
|
| 599 | 605 |
s->lock = 0; |
| 600 | 606 |
|
| 601 | 607 |
return s; |
| b/hw/m48t59.h | ||
|---|---|---|
| 3 | 3 |
|
| 4 | 4 |
typedef struct m48t59_t m48t59_t; |
| 5 | 5 |
|
| 6 |
void m48t59_write (m48t59_t *NVRAM, uint32_t val); |
|
| 7 |
uint32_t m48t59_read (m48t59_t *NVRAM); |
|
| 8 |
void m48t59_set_addr (m48t59_t *NVRAM, uint32_t addr); |
|
| 6 |
void m48t59_write (m48t59_t *NVRAM, uint32_t addr, uint32_t val); |
|
| 7 |
uint32_t m48t59_read (m48t59_t *NVRAM, uint32_t addr); |
|
| 9 | 8 |
void m48t59_toggle_lock (m48t59_t *NVRAM, int lock); |
| 10 |
m48t59_t *m48t59_init (int IRQ, uint32_t io_base, |
|
| 11 |
uint32_t mem_base, uint16_t size); |
|
| 9 |
m48t59_t *m48t59_init (int IRQ, target_ulong mem_base, |
|
| 10 |
uint32_t io_base, uint16_t size, |
|
| 11 |
int type); |
|
| 12 | 12 |
|
| 13 | 13 |
#endif /* !defined (__M48T59_H__) */ |
| b/hw/ppc.c | ||
|---|---|---|
| 283 | 283 |
/* NVRAM helpers */ |
| 284 | 284 |
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value) |
| 285 | 285 |
{
|
| 286 |
m48t59_set_addr(nvram, addr); |
|
| 287 |
m48t59_write(nvram, value); |
|
| 286 |
m48t59_write(nvram, addr, value); |
|
| 288 | 287 |
} |
| 289 | 288 |
|
| 290 | 289 |
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr) |
| 291 | 290 |
{
|
| 292 |
m48t59_set_addr(nvram, addr); |
|
| 293 |
return m48t59_read(nvram); |
|
| 291 |
return m48t59_read(nvram, addr); |
|
| 294 | 292 |
} |
| 295 | 293 |
|
| 296 | 294 |
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value) |
| 297 | 295 |
{
|
| 298 |
m48t59_set_addr(nvram, addr); |
|
| 299 |
m48t59_write(nvram, value >> 8); |
|
| 300 |
m48t59_set_addr(nvram, addr + 1); |
|
| 301 |
m48t59_write(nvram, value & 0xFF); |
|
| 296 |
m48t59_write(nvram, addr, value >> 8); |
|
| 297 |
m48t59_write(nvram, addr + 1, value & 0xFF); |
|
| 302 | 298 |
} |
| 303 | 299 |
|
| 304 | 300 |
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr) |
| 305 | 301 |
{
|
| 306 | 302 |
uint16_t tmp; |
| 307 | 303 |
|
| 308 |
m48t59_set_addr(nvram, addr); |
|
| 309 |
tmp = m48t59_read(nvram) << 8; |
|
| 310 |
m48t59_set_addr(nvram, addr + 1); |
|
| 311 |
tmp |= m48t59_read(nvram); |
|
| 312 |
|
|
| 304 |
tmp = m48t59_read(nvram, addr) << 8; |
|
| 305 |
tmp |= m48t59_read(nvram, addr + 1); |
|
| 313 | 306 |
return tmp; |
| 314 | 307 |
} |
| 315 | 308 |
|
| 316 | 309 |
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value) |
| 317 | 310 |
{
|
| 318 |
m48t59_set_addr(nvram, addr); |
|
| 319 |
m48t59_write(nvram, value >> 24); |
|
| 320 |
m48t59_set_addr(nvram, addr + 1); |
|
| 321 |
m48t59_write(nvram, (value >> 16) & 0xFF); |
|
| 322 |
m48t59_set_addr(nvram, addr + 2); |
|
| 323 |
m48t59_write(nvram, (value >> 8) & 0xFF); |
|
| 324 |
m48t59_set_addr(nvram, addr + 3); |
|
| 325 |
m48t59_write(nvram, value & 0xFF); |
|
| 311 |
m48t59_write(nvram, addr, value >> 24); |
|
| 312 |
m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF); |
|
| 313 |
m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF); |
|
| 314 |
m48t59_write(nvram, addr + 3, value & 0xFF); |
|
| 326 | 315 |
} |
| 327 | 316 |
|
| 328 | 317 |
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr) |
| 329 | 318 |
{
|
| 330 | 319 |
uint32_t tmp; |
| 331 | 320 |
|
| 332 |
m48t59_set_addr(nvram, addr); |
|
| 333 |
tmp = m48t59_read(nvram) << 24; |
|
| 334 |
m48t59_set_addr(nvram, addr + 1); |
|
| 335 |
tmp |= m48t59_read(nvram) << 16; |
|
| 336 |
m48t59_set_addr(nvram, addr + 2); |
|
| 337 |
tmp |= m48t59_read(nvram) << 8; |
|
| 338 |
m48t59_set_addr(nvram, addr + 3); |
|
| 339 |
tmp |= m48t59_read(nvram); |
|
| 340 |
|
|
| 321 |
tmp = m48t59_read(nvram, addr) << 24; |
|
| 322 |
tmp |= m48t59_read(nvram, addr + 1) << 16; |
|
| 323 |
tmp |= m48t59_read(nvram, addr + 2) << 8; |
|
| 324 |
tmp |= m48t59_read(nvram, addr + 3); |
|
| 341 | 325 |
return tmp; |
| 342 | 326 |
} |
| 343 | 327 |
|
| ... | ... | |
| 347 | 331 |
int i; |
| 348 | 332 |
|
| 349 | 333 |
for (i = 0; i < max && str[i] != '\0'; i++) {
|
| 350 |
m48t59_set_addr(nvram, addr + i); |
|
| 351 |
m48t59_write(nvram, str[i]); |
|
| 334 |
m48t59_write(nvram, addr + i, str[i]); |
|
| 352 | 335 |
} |
| 353 |
m48t59_set_addr(nvram, addr + max - 1); |
|
| 354 |
m48t59_write(nvram, '\0'); |
|
| 336 |
m48t59_write(nvram, addr + max - 1, '\0'); |
|
| 355 | 337 |
} |
| 356 | 338 |
|
| 357 | 339 |
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max) |
| b/hw/ppc_chrp.c | ||
|---|---|---|
| 449 | 449 |
|
| 450 | 450 |
macio_init(pci_bus, 0x0017); |
| 451 | 451 |
|
| 452 |
nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE); |
|
| 452 |
nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
|
|
| 453 | 453 |
|
| 454 | 454 |
arch_name = "HEATHROW"; |
| 455 | 455 |
} else {
|
| ... | ... | |
| 496 | 496 |
|
| 497 | 497 |
macio_init(pci_bus, 0x0022); |
| 498 | 498 |
|
| 499 |
nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE); |
|
| 499 |
nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
|
|
| 500 | 500 |
|
| 501 | 501 |
arch_name = "MAC99"; |
| 502 | 502 |
} |
| b/hw/ppc_prep.c | ||
|---|---|---|
| 652 | 652 |
cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory); |
| 653 | 653 |
#endif |
| 654 | 654 |
|
| 655 |
nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE); |
|
| 655 |
nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE, 59);
|
|
| 656 | 656 |
if (nvram == NULL) |
| 657 | 657 |
return; |
| 658 | 658 |
sysctrl->nvram = nvram; |
| b/hw/sun4m.c | ||
|---|---|---|
| 22 | 22 |
* THE SOFTWARE. |
| 23 | 23 |
*/ |
| 24 | 24 |
#include "vl.h" |
| 25 |
#include "m48t08.h" |
|
| 26 | 25 |
|
| 27 | 26 |
#define KERNEL_LOAD_ADDR 0x00004000 |
| 28 | 27 |
#define CMDLINE_ADDR 0x007ff000 |
| ... | ... | |
| 88 | 87 |
{
|
| 89 | 88 |
} |
| 90 | 89 |
|
| 91 |
static void nvram_set_word (m48t08_t *nvram, uint32_t addr, uint16_t value)
|
|
| 90 |
static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
|
|
| 92 | 91 |
{
|
| 93 |
m48t08_write(nvram, addr++, (value >> 8) & 0xff);
|
|
| 94 |
m48t08_write(nvram, addr++, value & 0xff);
|
|
| 92 |
m48t59_write(nvram, addr++, (value >> 8) & 0xff);
|
|
| 93 |
m48t59_write(nvram, addr++, value & 0xff);
|
|
| 95 | 94 |
} |
| 96 | 95 |
|
| 97 |
static void nvram_set_lword (m48t08_t *nvram, uint32_t addr, uint32_t value)
|
|
| 96 |
static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
|
|
| 98 | 97 |
{
|
| 99 |
m48t08_write(nvram, addr++, value >> 24);
|
|
| 100 |
m48t08_write(nvram, addr++, (value >> 16) & 0xff);
|
|
| 101 |
m48t08_write(nvram, addr++, (value >> 8) & 0xff);
|
|
| 102 |
m48t08_write(nvram, addr++, value & 0xff);
|
|
| 98 |
m48t59_write(nvram, addr++, value >> 24);
|
|
| 99 |
m48t59_write(nvram, addr++, (value >> 16) & 0xff);
|
|
| 100 |
m48t59_write(nvram, addr++, (value >> 8) & 0xff);
|
|
| 101 |
m48t59_write(nvram, addr++, value & 0xff);
|
|
| 103 | 102 |
} |
| 104 | 103 |
|
| 105 |
static void nvram_set_string (m48t08_t *nvram, uint32_t addr,
|
|
| 104 |
static void nvram_set_string (m48t59_t *nvram, uint32_t addr,
|
|
| 106 | 105 |
const unsigned char *str, uint32_t max) |
| 107 | 106 |
{
|
| 108 | 107 |
unsigned int i; |
| 109 | 108 |
|
| 110 | 109 |
for (i = 0; i < max && str[i] != '\0'; i++) {
|
| 111 |
m48t08_write(nvram, addr + i, str[i]);
|
|
| 110 |
m48t59_write(nvram, addr + i, str[i]);
|
|
| 112 | 111 |
} |
| 113 |
m48t08_write(nvram, addr + max - 1, '\0');
|
|
| 112 |
m48t59_write(nvram, addr + max - 1, '\0');
|
|
| 114 | 113 |
} |
| 115 | 114 |
|
| 116 |
static m48t08_t *nvram;
|
|
| 115 |
static m48t59_t *nvram;
|
|
| 117 | 116 |
|
| 118 | 117 |
extern int nographic; |
| 119 | 118 |
|
| 120 |
static void nvram_init(m48t08_t *nvram, uint8_t *macaddr, const char *cmdline,
|
|
| 119 |
static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
|
|
| 121 | 120 |
int boot_device, uint32_t RAM_size, |
| 122 | 121 |
uint32_t kernel_size, |
| 123 | 122 |
int width, int height, int depth) |
| ... | ... | |
| 129 | 128 |
nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
| 130 | 129 |
nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */ |
| 131 | 130 |
// NVRAM_size, arch not applicable |
| 132 |
m48t08_write(nvram, 0x2F, nographic & 0xff);
|
|
| 131 |
m48t59_write(nvram, 0x2F, nographic & 0xff);
|
|
| 133 | 132 |
nvram_set_lword(nvram, 0x30, RAM_size); |
| 134 |
m48t08_write(nvram, 0x34, boot_device & 0xff);
|
|
| 133 |
m48t59_write(nvram, 0x34, boot_device & 0xff);
|
|
| 135 | 134 |
nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR); |
| 136 | 135 |
nvram_set_lword(nvram, 0x3C, kernel_size); |
| 137 | 136 |
if (cmdline) {
|
| ... | ... | |
| 146 | 145 |
|
| 147 | 146 |
// Sun4m specific use |
| 148 | 147 |
i = 0x1fd8; |
| 149 |
m48t08_write(nvram, i++, 0x01);
|
|
| 150 |
m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */
|
|
| 148 |
m48t59_write(nvram, i++, 0x01);
|
|
| 149 |
m48t59_write(nvram, i++, 0x80); /* Sun4m OBP */
|
|
| 151 | 150 |
j = 0; |
| 152 |
m48t08_write(nvram, i++, macaddr[j++]);
|
|
| 153 |
m48t08_write(nvram, i++, macaddr[j++]);
|
|
| 154 |
m48t08_write(nvram, i++, macaddr[j++]);
|
|
| 155 |
m48t08_write(nvram, i++, macaddr[j++]);
|
|
| 156 |
m48t08_write(nvram, i++, macaddr[j++]);
|
|
| 157 |
m48t08_write(nvram, i, macaddr[j]);
|
|
| 151 |
m48t59_write(nvram, i++, macaddr[j++]);
|
|
| 152 |
m48t59_write(nvram, i++, macaddr[j++]);
|
|
| 153 |
m48t59_write(nvram, i++, macaddr[j++]);
|
|
| 154 |
m48t59_write(nvram, i++, macaddr[j++]);
|
|
| 155 |
m48t59_write(nvram, i++, macaddr[j++]);
|
|
| 156 |
m48t59_write(nvram, i, macaddr[j]);
|
|
| 158 | 157 |
|
| 159 | 158 |
/* Calculate checksum */ |
| 160 | 159 |
for (i = 0x1fd8; i < 0x1fe7; i++) {
|
| 161 |
tmp ^= m48t08_read(nvram, i);
|
|
| 160 |
tmp ^= m48t59_read(nvram, i);
|
|
| 162 | 161 |
} |
| 163 |
m48t08_write(nvram, 0x1fe7, tmp);
|
|
| 162 |
m48t59_write(nvram, 0x1fe7, tmp);
|
|
| 164 | 163 |
} |
| 165 | 164 |
|
| 166 | 165 |
static void *slavio_intctl; |
| ... | ... | |
| 231 | 230 |
slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G); |
| 232 | 231 |
tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height); |
| 233 | 232 |
lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA); |
| 234 |
nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE);
|
|
| 233 |
nvram = m48t59_init(0, PHYS_JJ_EEPROM, 0, PHYS_JJ_EEPROM_SIZE, 8);
|
|
| 235 | 234 |
slavio_timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ, PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ); |
| 236 | 235 |
slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ); |
| 237 | 236 |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device |
| b/hw/sun4u.c | ||
|---|---|---|
| 68 | 68 |
/* NVRAM helpers */ |
| 69 | 69 |
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value) |
| 70 | 70 |
{
|
| 71 |
m48t59_set_addr(nvram, addr); |
|
| 72 |
m48t59_write(nvram, value); |
|
| 71 |
m48t59_write(nvram, addr, value); |
|
| 73 | 72 |
} |
| 74 | 73 |
|
| 75 | 74 |
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr) |
| 76 | 75 |
{
|
| 77 |
m48t59_set_addr(nvram, addr); |
|
| 78 |
return m48t59_read(nvram); |
|
| 76 |
return m48t59_read(nvram, addr); |
|
| 79 | 77 |
} |
| 80 | 78 |
|
| 81 | 79 |
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value) |
| 82 | 80 |
{
|
| 83 |
m48t59_set_addr(nvram, addr); |
|
| 84 |
m48t59_write(nvram, value >> 8); |
|
| 85 |
m48t59_set_addr(nvram, addr + 1); |
|
| 86 |
m48t59_write(nvram, value & 0xFF); |
|
| 81 |
m48t59_write(nvram, addr, value >> 8); |
|
| 82 |
m48t59_write(nvram, addr + 1, value & 0xFF); |
|
| 87 | 83 |
} |
| 88 | 84 |
|
| 89 | 85 |
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr) |
| 90 | 86 |
{
|
| 91 | 87 |
uint16_t tmp; |
| 92 | 88 |
|
| 93 |
m48t59_set_addr(nvram, addr); |
|
| 94 |
tmp = m48t59_read(nvram) << 8; |
|
| 95 |
m48t59_set_addr(nvram, addr + 1); |
|
| 96 |
tmp |= m48t59_read(nvram); |
|
| 89 |
tmp = m48t59_read(nvram, addr) << 8; |
|
| 90 |
tmp |= m48t59_read(nvram, addr + 1); |
|
| 97 | 91 |
|
| 98 | 92 |
return tmp; |
| 99 | 93 |
} |
| 100 | 94 |
|
| 101 | 95 |
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value) |
| 102 | 96 |
{
|
| 103 |
m48t59_set_addr(nvram, addr); |
|
| 104 |
m48t59_write(nvram, value >> 24); |
|
| 105 |
m48t59_set_addr(nvram, addr + 1); |
|
| 106 |
m48t59_write(nvram, (value >> 16) & 0xFF); |
|
| 107 |
m48t59_set_addr(nvram, addr + 2); |
|
| 108 |
m48t59_write(nvram, (value >> 8) & 0xFF); |
|
| 109 |
m48t59_set_addr(nvram, addr + 3); |
|
| 110 |
m48t59_write(nvram, value & 0xFF); |
|
| 97 |
m48t59_write(nvram, addr, value >> 24); |
|
| 98 |
m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF); |
|
| 99 |
m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF); |
|
| 100 |
m48t59_write(nvram, addr + 3, value & 0xFF); |
|
| 111 | 101 |
} |
| 112 | 102 |
|
| 113 | 103 |
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr) |
| 114 | 104 |
{
|
| 115 | 105 |
uint32_t tmp; |
| 116 | 106 |
|
| 117 |
m48t59_set_addr(nvram, addr); |
|
| 118 |
tmp = m48t59_read(nvram) << 24; |
|
| 119 |
m48t59_set_addr(nvram, addr + 1); |
|
| 120 |
tmp |= m48t59_read(nvram) << 16; |
|
| 121 |
m48t59_set_addr(nvram, addr + 2); |
|
| 122 |
tmp |= m48t59_read(nvram) << 8; |
|
| 123 |
m48t59_set_addr(nvram, addr + 3); |
|
| 124 |
tmp |= m48t59_read(nvram); |
|
| 107 |
tmp = m48t59_read(nvram, addr) << 24; |
|
| 108 |
tmp |= m48t59_read(nvram, addr + 1) << 16; |
|
| 109 |
tmp |= m48t59_read(nvram, addr + 2) << 8; |
|
| 110 |
tmp |= m48t59_read(nvram, addr + 3); |
|
| 125 | 111 |
|
| 126 | 112 |
return tmp; |
| 127 | 113 |
} |
| ... | ... | |
| 132 | 118 |
int i; |
| 133 | 119 |
|
| 134 | 120 |
for (i = 0; i < max && str[i] != '\0'; i++) {
|
| 135 |
m48t59_set_addr(nvram, addr + i); |
|
| 136 |
m48t59_write(nvram, str[i]); |
|
| 121 |
m48t59_write(nvram, addr + i, str[i]); |
|
| 137 | 122 |
} |
| 138 |
m48t59_set_addr(nvram, addr + max - 1); |
|
| 139 |
m48t59_write(nvram, '\0'); |
|
| 123 |
m48t59_write(nvram, addr + max - 1, '\0'); |
|
| 140 | 124 |
} |
| 141 | 125 |
|
| 142 | 126 |
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max) |
| ... | ... | |
| 357 | 341 |
pci_cmd646_ide_init(pci_bus, bs_table, 1); |
| 358 | 342 |
kbd_init(); |
| 359 | 343 |
floppy_controller = fdctrl_init(6, 2, 0, 0x3f0, fd_table); |
| 360 |
nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE); |
|
| 344 |
nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE, 59);
|
|
| 361 | 345 |
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device, |
| 362 | 346 |
KERNEL_LOAD_ADDR, kernel_size, |
| 363 | 347 |
kernel_cmdline, |
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