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target-arm: Fix compilation failure for 64 bit hosts
Use the correct _ptr aliases for manipulating the pointer tothe fp_status; this fixes a compilation failure on 64 bit hosts.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Acked-by: Stefan Weil <weil@mail.berlios.de>...
target-arm: Use correct float status for Neon int-float conversions
The Neon versions of int-float conversions must use the "standard FPSCR" rather than the default FPSCR. Implement this by having the helperfunctions take a pointer to the appropriate float_status value rather...
target-arm: Fix VMLA, VMLS, VNMLS, VNMLA handling of NaNs
Correct handling of NaNs for VFP VMLA, VMLS, VNMLS and VNMLA requires thatwe implement the set of negations and additions specified by the ARM ARM;plausible looking simplifications like turning (-A + B) into (B - A) or...
Fix typos in comments (neccessary -> necessary)
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
Fix typos in comments and code (occured -> occurred and related)
The code changed here is an unused data type name (evt_flush_occurred).
target-arm: Don't update base register on abort in Thumb T1 LDM
Make sure the base register isn't updated if it is in the load listfor a Thumb LDM (T1 encoding) which aborts partway through the load.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: fix LDMIA bug on page boundarytarget-arm: fix LDMIA bug on page boundary
When consecutive memory locations are on page boundary, a base register may beloaded before page fault occurs. After page fault handling, it losts the memorylocation information. To solve this problem, loading a base register has to put back....
target-arm: Handle UNDEF cases for Neon VLD/VST multiple-structures
Correctly UNDEF for Neon VLD/VST "multiple structures" forms where thealign field is not valid.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Handle UNDEFs for Neon single element load/stores
Handle the UNDEF and UNPREDICTABLE cases for Neon "single element toone lane" VLD and "single element from one lane" VST.
Remove unused function parameters from gen_pc_load and rename the function
Function gen_pc_load was introduced in commitd2856f1ad4c259e5766847c49acbb4e390731bd4.The only reason for parameter searched_pc wasa debug statement in target-i386/translate.c....
move helpers.h to helper.h
This provides a consistent naming scheme across all targets.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Handle UNDEF cases for Neon invalid modified-immediates
For Neon "one register and a modified immediate value" forms, thecombination op=1 cmode=1111 is unallocated and should UNDEF.All instructions of this form also UNDEF if Q 1 and Vd<0> 1....
target-arm: Handle UNDEF cases for Neon 3-regs-different-widths
Add missing UNDEF checks for instructions in the Neon "3 registers ofdifferent widths" data processing space.
target-arm: Handle UNDEF cases for Neon 2 regs + scalar forms
Add missing checks for cases which must UNDEF in the Neon "2 registers anda scalar" data processing instruction space.
target-arm: Handle UNDEF cases for VEXT
VEXT must UNDEF if Q 1 && (Vd<0> 1 || Vr<0> 1 || Vm<0> 1)
target-arm: Simplify checking of size field in Neon 2reg-misc forms
Many of the Neon "2 register misc" instruction forms require invalidsize fields to cause the instruction to UNDEF. Pull this informationout into an array; this simplifies the code and also means we can do...
target-arm: Handle UNDEF cases for Neon 2 register misc forms
Add missing UNDEF checks for Neon "two register miscellaneous" forms: * all instructions except VMOVN,VQMOVN must UNDEF if Q==1 && (Vd<0> 1 || Vm<0> 1) * VMOVN,VQMOVN,VCVT.F16.F32 UNDEF if Q 1 || Vm<0> 1...
target-arm: Treat UNPREDICTABLE VTBL, VTBX case as UNDEF
Catch the UNPREDICTABLE case for Neon VTBL,VTBX, and UNDEF itrather than allowing the helper function to index off the endof the register file.
target-arm: Handle UNDEF cases for VDUP (scalar)
Handle the UNDEF cases for VDUP: imm4 x000 Q 1 && Vd<0> == 1
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Collapse VSRI case into VSHL, VSLI
Collapse some switch cases for VSRI into those for VSHL, VSLI,since the bodies are the same. (This is not completely obviousfor the size < 3 case, but since for VSRI we know U=1 theGEN_NEON_INTEGER_OP() expansion is equivalent to the open-coded...
target-arm: Use lookup table for size check on Neon 3-reg-same insns
Simplify the checks for invalid size values for the Neon "three registersof the same size" instruction forms (and add them where they were missing)by using a lookup table.
This includes adding symbolic constants for the op values in this space,...
target-arm: Handle UNDEF cases for Neon 3-regs-same insns
Correct the handling of UNDEF cases for the NEON "3 registers samesize" forms, by adding missing checks and rationalising some othersso they are done early enough to avoid leaking TCG temporaries....
target-arm: Simplify three-register pairwise code
Since we know that the case of (pairwise && q) has been caughtearlier, we can simplify the register setup code for each passin the three-register-same-size Neon loop.
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>...
target-arm: Handle UNDEF cases for Neon "2 regs and shift" insns
Correctly handle all the UNDEF cases for Neon instructions of the"2 registers and shift" form, and make sure that we check for thesecases early enough not to leak TCG temporaries.
arm: basic support for ARMv4/ARMv4T emulation
Currently target-arm/ assumes at least ARMv5 core. Add support forhandling also ARMv4/ARMv4T. This changes the following instructions:
BX
BKPT, BLX, CDP2, CLZ, LDC2, LDRD, MCRR, MCRR2, MRRC, MCRR, MRC2, MRRC,...
Fix conversions from pointer to tcg_target_long
tcg_gen_exit_tb takes a parameter of type tcg_target_long,so the type casts of pointer to long should be replaced bytype casts of pointer to tcg_target_long (suggested by Blue Swirl).
These changes are needed for build environments where...
target-arm: Use global env in iwmmxt_helper.c helpers
Use the global 'env' variable in the helper functions in iwmmxt_helper.c.This means we don't need to pass env as an argument to them any more.
target-arm: Use global env in neon_helper.c helpers
Use the global 'env' variable in the helper functions in neon_helper.c.This means we don't need to pass env as an argument to them any more.
target-arm: Fix VCLE.F32 #0, VCLT.F32 #0 NaN handling
Implementing the floating-point versions of VCLE #0 and VCLT #0 bydoing a GT comparison and inverting the result gives the wrongresult if the input is a NaN. Implement as a GT comparison with theoperands swapped instead....
target-arm: Fix VLD of single element to all lanes
Fix several bugs in VLD of single element to all lanes:
The "single element to all lanes" form of VLD1 differs from those forVLD2, VLD3 and VLD4 in that bit 5 indicates whether the loaded elementshould be written to one or two Dregs (rather than being a register...
target-arm: Don't leak TCG temp for UNDEFs in Neon load/store space
Move the allocation and freeing of the TCG temp used for the address forNeon load/store instructions so that we don't allocate the temporaryuntil we've done enough decoding to know that the instruction is not...
target-arm: Fix TCG temporary leaks for scalar VMULL
Fix a TCG temporary leak when translating 32-bit scalar VMULL.
target-arm: Set Q bit for overflow in SMUAD and SMLAD
SMUAD and SMLAD are supposed to set the Q bit if the addition ofthe two 16x16 multiply products and optional accumulator overflowsconsidered as a signed value. However we were only doing this checkfor the addition of the accumulator, not when adding the products,...
target-arm: Fix UNDEF cases in Thumb load/store
Decode of Thumb load/store was merging together the cases of 'bit 11==0'(reg+reg LSL imm) and 'bit 11==1' (reg+imm). This happens to work forvalid instruction patterns but meant that we would not UNDEF for the...
target-arm: Implement a minimal set of cp14 debug registers
Newer ARM kernels try to probe for whether the CPU has hardware breakpointsupport. For this to work QEMU has to implement a minimal set of the cp14debug registers. The architecture requires v7 cores to implement debug...
target-arm: Use TCG temporary leak debugging facilities
Use the new TCG temporary leak debugging facilities tocheck that each ARM instruction does not leak temporaries.
target-arm: Remove ad-hoc leak checking code
This commit removes the ad-hoc resource leak checking code fromtarget-arm. This includes replacing all uses of new_tmp() withtcg_temp_new_i32() and all uses of dead_tmp() withtcg_temp_free_i32().
target-arm: Set carry flag correctly for Thumb2 ORNS
The code for Thumb2 ORNS (or negated and set flags) was trashinga TCG input register which was needed later for use in calculatingflags, with the effect that the carry flag was always set withthe wrong sense. Fix this by using the TCG orc op instead of...
target-arm: Handle VMOV between two core and VFP single regs
Fix two bugs in the translation of the instructions VMOV sa,sb,rx,ry andVMOV rx,ry,sa,sb (which copy between a pair of ARM core registers and apair of VFP single precision registers):
target-arm: Don't decode old cp15 WFI instructions on v7 cores
In v7 of the ARM architecture, WFI (wait for interrupt) is a first-classinstruction, but in previous versions this functionality was providedvia a cp15 coprocessor register. Add correct feature checks to the...
target-arm: Fix shift by immediate and narrow where src, dest overlap
For Neon shifts by immediate and narrow, correctly handle the casewhere the source registers and the destination registers overlap(the second pass should use the original register contents, not the...
target-arm: Refactor to pull narrowing decode into separate function
Pull the code which decodes narrowing operations as being eithersigned/unsigned saturate or plain out into its own function.
target-arm: fix Neon VQSHRN and VSHRN.
Call the normal shift helpers instead of the rounding ones.
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: fix decoding of Neon 64 bit shifts.
Fix decoding of 64 bits variants of VSHRN, VRSHRN, VQSHRN, VQSHRUN,VQRSHRN, VQRSHRUN, taking into account whether inputs are unsignedor not.
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Move Neon VZIP to helper functions
Move the implementation of the Neon VUZP unzip instruction from inlinecode to helper functions. (At 50+ TCG ops it was well over therecommended limit for coding inline.) The helper implementations alsogive the correct answers where the inline implementation did not....
target-arm: Move Neon VUZP to helper functions
Move the implementation of the Neon VUZP unzip instruction from inlinecode to helper functions. (At 50+ TCG ops it was well over therecommended limit for coding inline.) The helper implementations alsofix the handling of the quadword version of the instruction....
target-arm: Correct conversion of Thumb Neon dp encodings into ARM
We handle Thumb Neon data processing instructions by converting theminto the equivalent ARM encoding, as the two are very close. Howeverthe ARM encoding should have bit 28 set, not clear. This wasn't causing...
target-arm: Fix Neon VQDMLSL instruction
For VQDMLSL, negation has to occur after saturation, not before.
target-arm: Refactor handling of VQDMULL
Refactor the handling of VQDMULL so that it is dealt with inits own if() case rather than together with the accumulatinginstructions.
target-arm: Implement VMULL.P8
Implement VMULL.P8 (the 32x32->64 version of the polynomial multiplyinstruction).
target-arm: Use standard FPSCR for Neon half-precision operations
The Neon half-precision conversion operations (VCVT.F16.F32 andVCVT.F32.F16) use ARM standard floating-point arithmetic, unlikethe VFP versions (VCVTB and VCVTT).
target-arm: implement vsli.64, vsri.64
target-arm: fix VSHLL Neon instruction.
Fix bit mask used when widening the result of shift on narrow input.
target-arm: Fix VQMOVUN Neon instruction.
VQMOVUN does a signed-to-unsigned saturating conversion. This isdifferent from both the signed-to-signed and unsigned-to-unsignedconversions already implemented, so we need a new set of helperfunctions (neon_unarrow_sat*)....
target-arm: Fix decoding of preload and memory hint space
Correct the decoding of the ARM preload and memory hint space,by adding decoding of PLI, PLDW and the v7MP unallocated hintspace. This commit also corrects a slightly overexuberantdecoding of PLD which was not checking that bit 4...
target-arm: Fix decoding of Thumb preload and hint space
Refine the decoding of the Thumb preload and hint space, so weUNDEF on the patterns that are supposed to UNDEF rather than NOP.We also move the tests for this space earlier, so we don't emitharmless but unnecessary address generation code for preload...
Set the right overflow bit for neon 32 and 64 bit saturating add/sub.
target-arm: Fix Neon vsra instructions.
This patch fixes the errors reported by my tests in VSRA.
Support saturation with shift=0.
This patch fixes corner-case saturations, when the target range iszero. It merely removes the guard against (sh == 0), and makes:_ssat(0x87654321, 1) return 0xffffffff and set the saturation flag_usat(0x87654321, 0) return 0 and set the saturation flag...
target-arm: Fix garbage collection of temporaries in Neon emulation.
Fix garbage collection of temporaries in Neon emulation.
target-arm: Fix loading of scalar value for Neon multiply-by-scalar
Fix the register and part of register we get the scalar from inthe various "multiply vector by scalar" ops (VMUL by scalarand friends).
target-arm: Log instruction start in TCG code
Add support for logging the start of instructions in TCGcode debug dumps for ARM targets.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
target-arm: Translate with VFP-enabled from TB flags, not CPUState
When translating code, whether the VFP unit is enabled for this TBis stored in a bit in the TB flags. Use this rather than incorrectlyreading the FPEXC from the CPUState passed to translation....
target-arm: Translate with VFP len/stride from TB flags, not CPUState
When translating, the VFP vector length and stride for this TB are encodedin the TB flags; the CPUState copies may be different and must not be used.
target-arm: Translate with Thumb state from TB flags, not CPUState
The Thumb/ARM state for the TB being translated should come fromthe TB flags, not the CPUState.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>...
target-arm: Translate with condexec bits from TB flags, not CPUState
When translating, the condexec bits for the TB are in the TB flags;the CPUState condexec bits may be different.
This patch fixes https://bugs.launchpad.net/bugs/604872 where we mightsegfault if we took an exception in the middle of a TB with an IT...
target-arm: Translate with user-state from TB flags, not CPUState
When translating, get the user/priv state from the TB flags, notthe CPUState.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Remove redundant setting of IT bits before Thumb SWI
Remove a redundant call to gen_set_condexec() in the translation of Thumbmode SWI. (SWI and WFI generate "exceptions" which happen after theexecution of the instruction, ie when PC and IT bits have updated....
target-arm: Refactor translation of exception generating instructions
Create a new function which does the common sequence of gen_set_condexec,gen_set_pc_im, gen_exception, set is_jmp to DISAS_JUMP.
target-arm: Restore IT bits when resuming after an exception
We were not correctly restoring the IT bits when resuming executionafter taking an unexpected exception in the middle of an IT block.Fix this by tracking them along with PC changes and restoring in...
target-arm: Don't generate code specific to current CPU mode for SRS
When translating the SRS instruction, handle the "store registersto stack of current mode" case in the helper function rather thaninline. This means the generated code does not make assumptions...
ARM: Fix decoding of VQSHL/VQSHLU immediate forms
Fix errors in the decoding of ARM VQSHL/VQSHLU immediate forms,including using the new VQSHLU helper functions where appropriate.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: fix SMMLA/SMMLS instructions
SMMLA and SMMLS are broken on both in normal and thumb mode, that isboth (different) implementations are wrong. They try to avoid a 64-bitadd for the rounding, which is not trivial if you want to support bothSMMLA and SMMLS with the same code....
target-arm: fix UMAAL instruction
UMAAL should use unsigned multiply instead of signed.
This patch fixes this issue by handling UMAAL separately fromUMULL/UMLAL/SMULL/SMLAL as these instructions are differentenough. It also explicitly list instructions in case and catch...
target-arm: Fix arguments passed to VQSHL helpers
Correct the arguments passed when generating neon qshl_{u,s}64()helpers so that we use the correct registers.
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: fix bug in translation of REVSH
The translation of REVSH shifted the low byte 8 steps left before performingan 8-bit sign extend, causing this part of the expression to alwas be 0.
Reported-by: Johan Bengtsson <teofrastius@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
ARM: fix ldrexd/strexd
Correct ldrexd and strexd code to always read and write thehigh word of the 64-bit value from addr+4.Also make ldrexd and strexd agree that for a 64 bit value theaddress in env->exclusive_addr is that of the low word.
This fixes the issues reported in...
ARM: Fix decoding of VFP forms of VCVT between float and int/fixed
Correct the decoding of source and destination registersfor the VFP forms of the VCVT instructions which convertbetween floating point and integer or fixed-point.
ARM: Fix decoding of Neon forms of VCVT between float and fixed point
Fix errors in the decoding of the Neon forms of fixed-point VCVT: * fixed-point VCVT is op 14 and 15, not 15 and 16 * the fbits immediate field was being misinterpreted * the sense of the to_fixed bit was inverted...
ARM: Fix sense of to_integer bit in Neon VCVT float/int conversion
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
target-arm: Add support for PKHxx in thumb2
The PKHxx instructions were not recognized by the thumb2 decoder. Thesolution provided in this changeset is identical to the arm-modeimplementation.
Signed-off-by: Johan Bengtsson <teofrastius@gmail.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Fix mixup in decoding of saturating add and sub
The thumb2 decoder contained a mixup between the bit controllingdoubling and the bit controlling if the operation was an add or a sub.
target-arm: Handle 'smc' as an undefined instruction
Refine check on bkpt so that smc and undefined instruction encodings arehandled as an undefined instruction and trap.
Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
target-arm : fix thumb2 parallel add/sub opcode decoding
Signed-off-by: Chih-Min Chao <cmchao@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
NEON vldN optimization
When combining multiple values as part of a NEON array load, do explcitshift/or rather than using gen_bfi. This voids redundant maskoperations.
Signed-off-by: Paul Brook <paul@codesourcery.com>
arm: remove dead assignments, spotted by clang analyzer
Value stored is never read.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: fix neon vmon/vmvn with modified immediate
Signed-Off-By: Riku Voipio <riku.voipio@nokia.com>Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: resource leak fixes for iwmmxt disassemble
This patch fixes few resource leaks in the iwmmxt disassemble.
Signed-off-by: Lars Munch <lars@segv.dk>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Fix handling of AL condition in IT instruction
Do not try to insert a conditional jump over next instruction when thecondition code is AL as this will trigger an internal error.
Signed-off-by: Johan Bengtsson <teofrastius@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: make RFE usable with any register
The rfe instruction can be used with any register, not just sp. Adjust thecondition check accordingly.
Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Fix missing 'return' in SRS handling.
There's a return missing in the srs handling which leads to srs always beingtreated an an invalid op.
target-arm: neon vshll instruction fix
implementation only widened the 32bit source vector elements into a64bit destination vector but forgot to perform the actual shiftingoperation.
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Signed-off-by: Riku Voipio <riku.voipio@nokia.com>...
target-arm: neon - fix VRADDHN/VRSUBHN vs VADDHN/VSUBHN
The rounding/truncating options were inverted. truncatingwas done when rounding was meant and vice verse.
Signed-off-by: Riku Voipio <riku.voipio@nokia.com>Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>...
ARM CP15 tls fix
Fix temporary handling in cp15 tls register load/store.
target-arm: implement Thumb-2 exception return
Support the "subs pc, lr" Thumb-2 exception return instruction.
Signed-off-by: Rabin Vincent <rabin@rab.in>Signed-off-by: Paul Brook <paul@codesourcery.com>
target-arm: fix thumb CPS
The Thumb CPS currently does not work correctly: CPSID touches more bitsthan the instruction wants to, and CPSIE does nothing. Fix it bypassing the correct mask (the "affect" bits) and value.
Signed-off-by: Rabin Vincent <rabin@rab.in>
target-arm: refactor cp15.c13 register access
Access the cp15.c13 TLS registers directly with TCG ops instead of witha slow helper. If the the cp15 read/write was not TLS register access,fall back to the cp15 helper.
This makes accessing __thread variables in linux-user when apps are compiled...
target-arm: fix strexd
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
ARM atomic ops rewrite
Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC.