Revision 81ea0e13
b/Makefile.target | ||
---|---|---|
247 | 247 |
obj-ppc-y += xilinx_uartlite.o |
248 | 248 |
obj-ppc-y += xilinx_ethlite.o |
249 | 249 |
|
250 |
# LM32 peripherals |
|
251 |
|
|
250 | 252 |
obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o |
251 | 253 |
obj-mips-y += mips_addr.o mips_timer.o mips_int.o |
252 | 254 |
obj-mips-y += vga.o i8259.o |
b/arch_init.c | ||
---|---|---|
64 | 64 |
#define QEMU_ARCH QEMU_ARCH_I386 |
65 | 65 |
#elif defined(TARGET_M68K) |
66 | 66 |
#define QEMU_ARCH QEMU_ARCH_M68K |
67 |
#elif defined(TARGET_LM32) |
|
68 |
#define QEMU_ARCH QEMU_ARCH_LM32 |
|
67 | 69 |
#elif defined(TARGET_MICROBLAZE) |
68 | 70 |
#define QEMU_ARCH QEMU_ARCH_MICROBLAZE |
69 | 71 |
#elif defined(TARGET_MIPS) |
b/arch_init.h | ||
---|---|---|
10 | 10 |
QEMU_ARCH_CRIS = 4, |
11 | 11 |
QEMU_ARCH_I386 = 8, |
12 | 12 |
QEMU_ARCH_M68K = 16, |
13 |
QEMU_ARCH_MICROBLAZE = 32, |
|
14 |
QEMU_ARCH_MIPS = 64, |
|
15 |
QEMU_ARCH_PPC = 128, |
|
16 |
QEMU_ARCH_S390X = 256, |
|
17 |
QEMU_ARCH_SH4 = 512, |
|
18 |
QEMU_ARCH_SPARC = 1024, |
|
13 |
QEMU_ARCH_LM32 = 32, |
|
14 |
QEMU_ARCH_MICROBLAZE = 64, |
|
15 |
QEMU_ARCH_MIPS = 128, |
|
16 |
QEMU_ARCH_PPC = 256, |
|
17 |
QEMU_ARCH_S390X = 512, |
|
18 |
QEMU_ARCH_SH4 = 1024, |
|
19 |
QEMU_ARCH_SPARC = 2048, |
|
19 | 20 |
}; |
20 | 21 |
|
21 | 22 |
extern const uint32_t arch_type; |
b/cpu-exec.c | ||
---|---|---|
239 | 239 |
#elif defined(TARGET_ALPHA) |
240 | 240 |
#elif defined(TARGET_ARM) |
241 | 241 |
#elif defined(TARGET_PPC) |
242 |
#elif defined(TARGET_LM32) |
|
242 | 243 |
#elif defined(TARGET_MICROBLAZE) |
243 | 244 |
#elif defined(TARGET_MIPS) |
244 | 245 |
#elif defined(TARGET_SH4) |
... | ... | |
292 | 293 |
env->old_exception = -1; |
293 | 294 |
#elif defined(TARGET_PPC) |
294 | 295 |
do_interrupt(env); |
296 |
#elif defined(TARGET_LM32) |
|
297 |
do_interrupt(env); |
|
295 | 298 |
#elif defined(TARGET_MICROBLAZE) |
296 | 299 |
do_interrupt(env); |
297 | 300 |
#elif defined(TARGET_MIPS) |
... | ... | |
332 | 335 |
} |
333 | 336 |
#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \ |
334 | 337 |
defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \ |
335 |
defined(TARGET_MICROBLAZE) |
|
338 |
defined(TARGET_MICROBLAZE) || defined(TARGET_LM32)
|
|
336 | 339 |
if (interrupt_request & CPU_INTERRUPT_HALT) { |
337 | 340 |
env->interrupt_request &= ~CPU_INTERRUPT_HALT; |
338 | 341 |
env->halted = 1; |
... | ... | |
412 | 415 |
env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
413 | 416 |
next_tb = 0; |
414 | 417 |
} |
418 |
#elif defined(TARGET_LM32) |
|
419 |
if ((interrupt_request & CPU_INTERRUPT_HARD) |
|
420 |
&& (env->ie & IE_IE)) { |
|
421 |
env->exception_index = EXCP_IRQ; |
|
422 |
do_interrupt(env); |
|
423 |
next_tb = 0; |
|
424 |
} |
|
415 | 425 |
#elif defined(TARGET_MICROBLAZE) |
416 | 426 |
if ((interrupt_request & CPU_INTERRUPT_HARD) |
417 | 427 |
&& (env->sregs[SR_MSR] & MSR_IE) |
... | ... | |
624 | 634 |
/* XXX: Save/restore host fpu exception state?. */ |
625 | 635 |
#elif defined(TARGET_SPARC) |
626 | 636 |
#elif defined(TARGET_PPC) |
637 |
#elif defined(TARGET_LM32) |
|
627 | 638 |
#elif defined(TARGET_M68K) |
628 | 639 |
cpu_m68k_flush_flags(env, env->cc_op); |
629 | 640 |
env->cc_op = CC_OP_FLAGS; |
b/elf.h | ||
---|---|---|
104 | 104 |
|
105 | 105 |
#define EM_H8_300H 47 /* Hitachi H8/300H */ |
106 | 106 |
#define EM_H8S 48 /* Hitachi H8S */ |
107 |
#define EM_LATTICEMICO32 138 /* LatticeMico32 */ |
|
107 | 108 |
|
108 | 109 |
/* |
109 | 110 |
* This is an interim value that we will use until the committee comes |
b/poison.h | ||
---|---|---|
10 | 10 |
#pragma GCC poison TARGET_ALPHA |
11 | 11 |
#pragma GCC poison TARGET_ARM |
12 | 12 |
#pragma GCC poison TARGET_CRIS |
13 |
#pragma GCC poison TARGET_LM32 |
|
13 | 14 |
#pragma GCC poison TARGET_M68K |
14 | 15 |
#pragma GCC poison TARGET_MIPS |
15 | 16 |
#pragma GCC poison TARGET_MIPS64 |
b/target-lm32/cpu.h | ||
---|---|---|
1 |
/* |
|
2 |
* LatticeMico32 virtual CPU header. |
|
3 |
* |
|
4 |
* Copyright (c) 2010 Michael Walle <michael@walle.cc> |
|
5 |
* |
|
6 |
* This library is free software; you can redistribute it and/or |
|
7 |
* modify it under the terms of the GNU Lesser General Public |
|
8 |
* License as published by the Free Software Foundation; either |
|
9 |
* version 2 of the License, or (at your option) any later version. |
|
10 |
* |
|
11 |
* This library is distributed in the hope that it will be useful, |
|
12 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
13 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
|
14 |
* Lesser General Public License for more details. |
|
15 |
* |
|
16 |
* You should have received a copy of the GNU Lesser General Public |
|
17 |
* License along with this library; if not, see <http://www.gnu.org/licenses/>. |
|
18 |
*/ |
|
19 |
|
|
20 |
#ifndef CPU_LM32_H |
|
21 |
#define CPU_LM32_H |
|
22 |
|
|
23 |
#define TARGET_LONG_BITS 32 |
|
24 |
|
|
25 |
#define CPUState struct CPULM32State |
|
26 |
|
|
27 |
#include "qemu-common.h" |
|
28 |
#include "cpu-defs.h" |
|
29 |
struct CPULM32State; |
|
30 |
|
|
31 |
#define TARGET_HAS_ICE 1 |
|
32 |
|
|
33 |
#define ELF_MACHINE EM_LATTICEMICO32 |
|
34 |
|
|
35 |
#define NB_MMU_MODES 1 |
|
36 |
#define TARGET_PAGE_BITS 12 |
|
37 |
static inline int cpu_mmu_index(CPUState *env) |
|
38 |
{ |
|
39 |
return 0; |
|
40 |
} |
|
41 |
|
|
42 |
#define TARGET_PHYS_ADDR_SPACE_BITS 32 |
|
43 |
#define TARGET_VIRT_ADDR_SPACE_BITS 32 |
|
44 |
|
|
45 |
/* Exceptions indices */ |
|
46 |
enum { |
|
47 |
EXCP_RESET = 0, |
|
48 |
EXCP_BREAKPOINT, |
|
49 |
EXCP_INSN_BUS_ERROR, |
|
50 |
EXCP_WATCHPOINT, |
|
51 |
EXCP_DATA_BUS_ERROR, |
|
52 |
EXCP_DIVIDE_BY_ZERO, |
|
53 |
EXCP_IRQ, |
|
54 |
EXCP_SYSTEMCALL |
|
55 |
}; |
|
56 |
|
|
57 |
/* Registers */ |
|
58 |
enum { |
|
59 |
R_R0 = 0, R_R1, R_R2, R_R3, R_R4, R_R5, R_R6, R_R7, R_R8, R_R9, R_R10, |
|
60 |
R_R11, R_R12, R_R13, R_R14, R_R15, R_R16, R_R17, R_R18, R_R19, R_R20, |
|
61 |
R_R21, R_R22, R_R23, R_R24, R_R25, R_R26, R_R27, R_R28, R_R29, R_R30, |
|
62 |
R_R31 |
|
63 |
}; |
|
64 |
|
|
65 |
/* Register aliases */ |
|
66 |
enum { |
|
67 |
R_GP = R_R26, |
|
68 |
R_FP = R_R27, |
|
69 |
R_SP = R_R28, |
|
70 |
R_RA = R_R29, |
|
71 |
R_EA = R_R30, |
|
72 |
R_BA = R_R31 |
|
73 |
}; |
|
74 |
|
|
75 |
/* IE flags */ |
|
76 |
enum { |
|
77 |
IE_IE = (1<<0), |
|
78 |
IE_EIE = (1<<1), |
|
79 |
IE_BIE = (1<<2), |
|
80 |
}; |
|
81 |
|
|
82 |
/* DC flags */ |
|
83 |
enum { |
|
84 |
DC_SS = (1<<0), |
|
85 |
DC_RE = (1<<1), |
|
86 |
DC_C0 = (1<<2), |
|
87 |
DC_C1 = (1<<3), |
|
88 |
DC_C2 = (1<<4), |
|
89 |
DC_C3 = (1<<5), |
|
90 |
}; |
|
91 |
|
|
92 |
/* CFG mask */ |
|
93 |
enum { |
|
94 |
CFG_M = (1<<0), |
|
95 |
CFG_D = (1<<1), |
|
96 |
CFG_S = (1<<2), |
|
97 |
CFG_U = (1<<3), |
|
98 |
CFG_X = (1<<4), |
|
99 |
CFG_CC = (1<<5), |
|
100 |
CFG_IC = (1<<6), |
|
101 |
CFG_DC = (1<<7), |
|
102 |
CFG_G = (1<<8), |
|
103 |
CFG_H = (1<<9), |
|
104 |
CFG_R = (1<<10), |
|
105 |
CFG_J = (1<<11), |
|
106 |
CFG_INT_SHIFT = 12, |
|
107 |
CFG_BP_SHIFT = 18, |
|
108 |
CFG_WP_SHIFT = 22, |
|
109 |
CFG_REV_SHIFT = 26, |
|
110 |
}; |
|
111 |
|
|
112 |
/* CSRs */ |
|
113 |
enum { |
|
114 |
CSR_IE = 0x00, |
|
115 |
CSR_IM = 0x01, |
|
116 |
CSR_IP = 0x02, |
|
117 |
CSR_ICC = 0x03, |
|
118 |
CSR_DCC = 0x04, |
|
119 |
CSR_CC = 0x05, |
|
120 |
CSR_CFG = 0x06, |
|
121 |
CSR_EBA = 0x07, |
|
122 |
CSR_DC = 0x08, |
|
123 |
CSR_DEBA = 0x09, |
|
124 |
CSR_JTX = 0x0e, |
|
125 |
CSR_JRX = 0x0f, |
|
126 |
CSR_BP0 = 0x10, |
|
127 |
CSR_BP1 = 0x11, |
|
128 |
CSR_BP2 = 0x12, |
|
129 |
CSR_BP3 = 0x13, |
|
130 |
CSR_WP0 = 0x18, |
|
131 |
CSR_WP1 = 0x19, |
|
132 |
CSR_WP2 = 0x1a, |
|
133 |
CSR_WP3 = 0x1b, |
|
134 |
}; |
|
135 |
|
|
136 |
enum { |
|
137 |
LM32_FEATURE_MULTIPLY = 1, |
|
138 |
LM32_FEATURE_DIVIDE = 2, |
|
139 |
LM32_FEATURE_SHIFT = 4, |
|
140 |
LM32_FEATURE_SIGN_EXTEND = 8, |
|
141 |
LM32_FEATURE_I_CACHE = 16, |
|
142 |
LM32_FEATURE_D_CACHE = 32, |
|
143 |
LM32_FEATURE_CYCLE_COUNT = 64, |
|
144 |
}; |
|
145 |
|
|
146 |
enum { |
|
147 |
LM32_FLAG_IGNORE_MSB = 1, |
|
148 |
}; |
|
149 |
|
|
150 |
typedef struct CPULM32State { |
|
151 |
/* general registers */ |
|
152 |
uint32_t regs[32]; |
|
153 |
|
|
154 |
/* special registers */ |
|
155 |
uint32_t pc; /* program counter */ |
|
156 |
uint32_t ie; /* interrupt enable */ |
|
157 |
uint32_t icc; /* instruction cache control */ |
|
158 |
uint32_t dcc; /* data cache control */ |
|
159 |
uint32_t cc; /* cycle counter */ |
|
160 |
uint32_t cfg; /* configuration */ |
|
161 |
|
|
162 |
/* debug registers */ |
|
163 |
uint32_t dc; /* debug control */ |
|
164 |
uint32_t bp[4]; /* breakpoint addresses */ |
|
165 |
uint32_t wp[4]; /* watchpoint addresses */ |
|
166 |
|
|
167 |
CPU_COMMON |
|
168 |
|
|
169 |
uint32_t eba; /* exception base address */ |
|
170 |
uint32_t deba; /* debug exception base address */ |
|
171 |
|
|
172 |
/* interrupt controller handle for callbacks */ |
|
173 |
DeviceState *pic_state; |
|
174 |
/* JTAG UART handle for callbacks */ |
|
175 |
DeviceState *juart_state; |
|
176 |
|
|
177 |
/* processor core features */ |
|
178 |
uint32_t features; |
|
179 |
uint32_t flags; |
|
180 |
uint8_t num_bps; |
|
181 |
uint8_t num_wps; |
|
182 |
|
|
183 |
} CPULM32State; |
|
184 |
|
|
185 |
|
|
186 |
CPUState *cpu_lm32_init(const char *cpu_model); |
|
187 |
void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf); |
|
188 |
int cpu_lm32_exec(CPUState *s); |
|
189 |
void cpu_lm32_close(CPUState *s); |
|
190 |
void do_interrupt(CPUState *env); |
|
191 |
/* you can call this signal handler from your SIGBUS and SIGSEGV |
|
192 |
signal handlers to inform the virtual CPU of exceptions. non zero |
|
193 |
is returned if the signal was handled by the virtual CPU. */ |
|
194 |
int cpu_lm32_signal_handler(int host_signum, void *pinfo, |
|
195 |
void *puc); |
|
196 |
void lm32_translate_init(void); |
|
197 |
void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value); |
|
198 |
|
|
199 |
#define cpu_list cpu_lm32_list |
|
200 |
#define cpu_init cpu_lm32_init |
|
201 |
#define cpu_exec cpu_lm32_exec |
|
202 |
#define cpu_gen_code cpu_lm32_gen_code |
|
203 |
#define cpu_signal_handler cpu_lm32_signal_handler |
|
204 |
|
|
205 |
#define CPU_SAVE_VERSION 1 |
|
206 |
|
|
207 |
int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw, |
|
208 |
int mmu_idx, int is_softmmu); |
|
209 |
#define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault |
|
210 |
|
|
211 |
#if defined(CONFIG_USER_ONLY) |
|
212 |
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
|
213 |
{ |
|
214 |
if (newsp) { |
|
215 |
env->regs[R_SP] = newsp; |
|
216 |
} |
|
217 |
env->regs[R_R1] = 0; |
|
218 |
} |
|
219 |
#endif |
|
220 |
|
|
221 |
static inline void cpu_set_tls(CPUState *env, target_ulong newtls) |
|
222 |
{ |
|
223 |
} |
|
224 |
|
|
225 |
static inline int cpu_interrupts_enabled(CPUState *env) |
|
226 |
{ |
|
227 |
return env->ie & IE_IE; |
|
228 |
} |
|
229 |
|
|
230 |
#include "cpu-all.h" |
|
231 |
|
|
232 |
static inline target_ulong cpu_get_pc(CPUState *env) |
|
233 |
{ |
|
234 |
return env->pc; |
|
235 |
} |
|
236 |
|
|
237 |
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
|
238 |
target_ulong *cs_base, int *flags) |
|
239 |
{ |
|
240 |
*pc = env->pc; |
|
241 |
*cs_base = 0; |
|
242 |
*flags = 0; |
|
243 |
} |
|
244 |
#endif |
b/target-lm32/exec.h | ||
---|---|---|
1 |
/* |
|
2 |
* LatticeMico32 execution defines. |
|
3 |
* |
|
4 |
* Copyright (c) 2010 Michael Walle <michael@walle.cc> |
|
5 |
* |
|
6 |
* This library is free software; you can redistribute it and/or |
|
7 |
* modify it under the terms of the GNU Lesser General Public |
|
8 |
* License as published by the Free Software Foundation; either |
|
9 |
* version 2 of the License, or (at your option) any later version. |
|
10 |
* |
|
11 |
* This library is distributed in the hope that it will be useful, |
|
12 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
13 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
|
14 |
* Lesser General Public License for more details. |
|
15 |
* |
|
16 |
* You should have received a copy of the GNU Lesser General Public |
|
17 |
* License along with this library; if not, see <http://www.gnu.org/licenses/>. |
|
18 |
*/ |
|
19 |
|
|
20 |
#include "dyngen-exec.h" |
|
21 |
|
|
22 |
register struct CPULM32State *env asm(AREG0); |
|
23 |
|
|
24 |
#include "cpu.h" |
|
25 |
#include "exec-all.h" |
|
26 |
|
|
27 |
static inline int cpu_has_work(CPUState *env) |
|
28 |
{ |
|
29 |
return env->interrupt_request & CPU_INTERRUPT_HARD; |
|
30 |
} |
|
31 |
|
|
32 |
static inline int cpu_halted(CPUState *env) |
|
33 |
{ |
|
34 |
if (!env->halted) { |
|
35 |
return 0; |
|
36 |
} |
|
37 |
|
|
38 |
/* IRQ execeptions wakes us up. */ |
|
39 |
if (cpu_has_work(env)) { |
|
40 |
env->halted = 0; |
|
41 |
return 0; |
|
42 |
} |
|
43 |
return EXCP_HALTED; |
|
44 |
} |
|
45 |
|
|
46 |
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
|
47 |
{ |
|
48 |
env->pc = tb->pc; |
|
49 |
} |
|
50 |
|
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