Revision 8217606e hw/ppc405_uc.c
| b/hw/ppc405_uc.c | ||
|---|---|---|
| 173 | 173 |
ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); |
| 174 | 174 |
ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); |
| 175 | 175 |
ppc4xx_plb_reset(plb); |
| 176 |
qemu_register_reset(ppc4xx_plb_reset, plb); |
|
| 176 |
qemu_register_reset(ppc4xx_plb_reset, 0, plb);
|
|
| 177 | 177 |
} |
| 178 | 178 |
|
| 179 | 179 |
/*****************************************************************************/ |
| ... | ... | |
| 249 | 249 |
ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); |
| 250 | 250 |
ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); |
| 251 | 251 |
ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); |
| 252 |
qemu_register_reset(ppc4xx_pob_reset, pob); |
|
| 252 |
qemu_register_reset(ppc4xx_pob_reset, 0, pob);
|
|
| 253 | 253 |
ppc4xx_pob_reset(env); |
| 254 | 254 |
} |
| 255 | 255 |
|
| ... | ... | |
| 386 | 386 |
#endif |
| 387 | 387 |
ppc4xx_mmio_register(env, mmio, offset, 0x002, |
| 388 | 388 |
opba_read, opba_write, opba); |
| 389 |
qemu_register_reset(ppc4xx_opba_reset, opba); |
|
| 389 |
qemu_register_reset(ppc4xx_opba_reset, 0, opba);
|
|
| 390 | 390 |
ppc4xx_opba_reset(opba); |
| 391 | 391 |
} |
| 392 | 392 |
|
| ... | ... | |
| 580 | 580 |
|
| 581 | 581 |
ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t)); |
| 582 | 582 |
ebc_reset(ebc); |
| 583 |
qemu_register_reset(&ebc_reset, ebc); |
|
| 583 |
qemu_register_reset(&ebc_reset, 0, ebc);
|
|
| 584 | 584 |
ppc_dcr_register(env, EBC0_CFGADDR, |
| 585 | 585 |
ebc, &dcr_read_ebc, &dcr_write_ebc); |
| 586 | 586 |
ppc_dcr_register(env, EBC0_CFGDATA, |
| ... | ... | |
| 672 | 672 |
dma = qemu_mallocz(sizeof(ppc405_dma_t)); |
| 673 | 673 |
memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); |
| 674 | 674 |
ppc405_dma_reset(dma); |
| 675 |
qemu_register_reset(&ppc405_dma_reset, dma); |
|
| 675 |
qemu_register_reset(&ppc405_dma_reset, 0, dma);
|
|
| 676 | 676 |
ppc_dcr_register(env, DMA0_CR0, |
| 677 | 677 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 678 | 678 |
ppc_dcr_register(env, DMA0_CT0, |
| ... | ... | |
| 837 | 837 |
gpio = qemu_mallocz(sizeof(ppc405_gpio_t)); |
| 838 | 838 |
gpio->base = offset; |
| 839 | 839 |
ppc405_gpio_reset(gpio); |
| 840 |
qemu_register_reset(&ppc405_gpio_reset, gpio); |
|
| 840 |
qemu_register_reset(&ppc405_gpio_reset, 0, gpio);
|
|
| 841 | 841 |
#ifdef DEBUG_GPIO |
| 842 | 842 |
printf("%s: offset " PADDRX "\n", __func__, offset);
|
| 843 | 843 |
#endif |
| ... | ... | |
| 1028 | 1028 |
ocm = qemu_mallocz(sizeof(ppc405_ocm_t)); |
| 1029 | 1029 |
ocm->offset = qemu_ram_alloc(4096); |
| 1030 | 1030 |
ocm_reset(ocm); |
| 1031 |
qemu_register_reset(&ocm_reset, ocm); |
|
| 1031 |
qemu_register_reset(&ocm_reset, 0, ocm);
|
|
| 1032 | 1032 |
ppc_dcr_register(env, OCM0_ISARC, |
| 1033 | 1033 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
| 1034 | 1034 |
ppc_dcr_register(env, OCM0_ISACNTL, |
| ... | ... | |
| 1280 | 1280 |
#endif |
| 1281 | 1281 |
ppc4xx_mmio_register(env, mmio, offset, 0x011, |
| 1282 | 1282 |
i2c_read, i2c_write, i2c); |
| 1283 |
qemu_register_reset(ppc4xx_i2c_reset, i2c); |
|
| 1283 |
qemu_register_reset(ppc4xx_i2c_reset, 0, i2c);
|
|
| 1284 | 1284 |
} |
| 1285 | 1285 |
|
| 1286 | 1286 |
/*****************************************************************************/ |
| ... | ... | |
| 1562 | 1562 |
#endif |
| 1563 | 1563 |
ppc4xx_mmio_register(env, mmio, offset, 0x0D4, |
| 1564 | 1564 |
gpt_read, gpt_write, gpt); |
| 1565 |
qemu_register_reset(ppc4xx_gpt_reset, gpt); |
|
| 1565 |
qemu_register_reset(ppc4xx_gpt_reset, 0, gpt);
|
|
| 1566 | 1566 |
} |
| 1567 | 1567 |
|
| 1568 | 1568 |
/*****************************************************************************/ |
| ... | ... | |
| 1787 | 1787 |
for (i = 0; i < 4; i++) |
| 1788 | 1788 |
mal->irqs[i] = irqs[i]; |
| 1789 | 1789 |
ppc40x_mal_reset(mal); |
| 1790 |
qemu_register_reset(&ppc40x_mal_reset, mal); |
|
| 1790 |
qemu_register_reset(&ppc40x_mal_reset, 0, mal);
|
|
| 1791 | 1791 |
ppc_dcr_register(env, MAL0_CFG, |
| 1792 | 1792 |
mal, &dcr_read_mal, &dcr_write_mal); |
| 1793 | 1793 |
ppc_dcr_register(env, MAL0_ESR, |
| ... | ... | |
| 2171 | 2171 |
ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc, |
| 2172 | 2172 |
&dcr_read_crcpc, &dcr_write_crcpc); |
| 2173 | 2173 |
ppc405cr_clk_init(cpc); |
| 2174 |
qemu_register_reset(ppc405cr_cpc_reset, cpc); |
|
| 2174 |
qemu_register_reset(ppc405cr_cpc_reset, 0, cpc);
|
|
| 2175 | 2175 |
ppc405cr_cpc_reset(cpc); |
| 2176 | 2176 |
} |
| 2177 | 2177 |
|
| ... | ... | |
| 2493 | 2493 |
cpc->jtagid = 0x20267049; |
| 2494 | 2494 |
cpc->sysclk = sysclk; |
| 2495 | 2495 |
ppc405ep_cpc_reset(cpc); |
| 2496 |
qemu_register_reset(&ppc405ep_cpc_reset, cpc); |
|
| 2496 |
qemu_register_reset(&ppc405ep_cpc_reset, 0, cpc);
|
|
| 2497 | 2497 |
ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, |
| 2498 | 2498 |
&dcr_read_epcpc, &dcr_write_epcpc); |
| 2499 | 2499 |
ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, |
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