Revision 827df9f3 hw/omap.h
| b/hw/omap.h | ||
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| 5 | 5 |
* |
| 6 | 6 |
* This program is free software; you can redistribute it and/or |
| 7 | 7 |
* modify it under the terms of the GNU General Public License as |
| 8 |
* published by the Free Software Foundation; either version 2 of
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| 9 |
* the License, or (at your option) any later version.
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| 8 |
* published by the Free Software Foundation; either version 2 or
|
|
| 9 |
* (at your option) version 3 of the License.
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|
| 10 | 10 |
* |
| 11 | 11 |
* This program is distributed in the hope that it will be useful, |
| 12 | 12 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ... | ... | |
| 22 | 22 |
# define hw_omap_h "omap.h" |
| 23 | 23 |
|
| 24 | 24 |
# define OMAP_EMIFS_BASE 0x00000000 |
| 25 |
# define OMAP2_Q0_BASE 0x00000000 |
|
| 25 | 26 |
# define OMAP_CS0_BASE 0x00000000 |
| 26 | 27 |
# define OMAP_CS1_BASE 0x04000000 |
| 27 | 28 |
# define OMAP_CS2_BASE 0x08000000 |
| ... | ... | |
| 29 | 30 |
# define OMAP_EMIFF_BASE 0x10000000 |
| 30 | 31 |
# define OMAP_IMIF_BASE 0x20000000 |
| 31 | 32 |
# define OMAP_LOCALBUS_BASE 0x30000000 |
| 33 |
# define OMAP2_Q1_BASE 0x40000000 |
|
| 34 |
# define OMAP2_L4_BASE 0x48000000 |
|
| 35 |
# define OMAP2_SRAM_BASE 0x40200000 |
|
| 36 |
# define OMAP2_L3_BASE 0x68000000 |
|
| 37 |
# define OMAP2_Q2_BASE 0x80000000 |
|
| 38 |
# define OMAP2_Q3_BASE 0xc0000000 |
|
| 32 | 39 |
# define OMAP_MPUI_BASE 0xe1000000 |
| 33 | 40 |
|
| 34 | 41 |
# define OMAP730_SRAM_SIZE 0x00032000 |
| 35 | 42 |
# define OMAP15XX_SRAM_SIZE 0x00030000 |
| 36 | 43 |
# define OMAP16XX_SRAM_SIZE 0x00004000 |
| 37 | 44 |
# define OMAP1611_SRAM_SIZE 0x0003e800 |
| 45 |
# define OMAP242X_SRAM_SIZE 0x000a0000 |
|
| 46 |
# define OMAP243X_SRAM_SIZE 0x00010000 |
|
| 38 | 47 |
# define OMAP_CS0_SIZE 0x04000000 |
| 39 | 48 |
# define OMAP_CS1_SIZE 0x04000000 |
| 40 | 49 |
# define OMAP_CS2_SIZE 0x04000000 |
| 41 | 50 |
# define OMAP_CS3_SIZE 0x04000000 |
| 42 | 51 |
|
| 43 |
/* omap1_clk.c */
|
|
| 52 |
/* omap_clk.c */ |
|
| 44 | 53 |
struct omap_mpu_state_s; |
| 45 | 54 |
typedef struct clk *omap_clk; |
| 46 | 55 |
omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); |
| ... | ... | |
| 55 | 64 |
void omap_clk_reparent(omap_clk clk, omap_clk parent); |
| 56 | 65 |
|
| 57 | 66 |
/* omap[123].c */ |
| 67 |
struct omap_l4_s; |
|
| 68 |
struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num); |
|
| 69 |
|
|
| 70 |
struct omap_target_agent_s; |
|
| 71 |
struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs); |
|
| 72 |
target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region, |
|
| 73 |
int iotype); |
|
| 74 |
|
|
| 58 | 75 |
struct omap_intr_handler_s; |
| 59 | 76 |
struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base, |
| 60 |
unsigned long size, unsigned char nbanks, |
|
| 77 |
unsigned long size, unsigned char nbanks, qemu_irq **pins,
|
|
| 61 | 78 |
qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk); |
| 62 |
|
|
| 63 |
struct omap_target_agent_s; |
|
| 64 |
static inline target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, |
|
| 65 |
int region, int iotype) { return 0; }
|
|
| 79 |
struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base, |
|
| 80 |
int size, int nbanks, qemu_irq **pins, |
|
| 81 |
qemu_irq parent_irq, qemu_irq parent_fiq, |
|
| 82 |
omap_clk fclk, omap_clk iclk); |
|
| 83 |
void omap_inth_reset(struct omap_intr_handler_s *s); |
|
| 84 |
|
|
| 85 |
struct omap_prcm_s; |
|
| 86 |
struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta, |
|
| 87 |
qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int, |
|
| 88 |
struct omap_mpu_state_s *mpu); |
|
| 89 |
|
|
| 90 |
struct omap_sysctl_s; |
|
| 91 |
struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta, |
|
| 92 |
omap_clk iclk, struct omap_mpu_state_s *mpu); |
|
| 93 |
|
|
| 94 |
struct omap_sdrc_s; |
|
| 95 |
struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base); |
|
| 96 |
|
|
| 97 |
struct omap_gpmc_s; |
|
| 98 |
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq); |
|
| 99 |
void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype, |
|
| 100 |
void (*base_upd)(void *opaque, target_phys_addr_t new), |
|
| 101 |
void (*unmap)(void *opaque), void *opaque); |
|
| 66 | 102 |
|
| 67 | 103 |
/* |
| 68 | 104 |
* Common IRQ numbers for level 1 interrupt handler |
| ... | ... | |
| 295 | 331 |
* OMAP-24xx common IRQ numbers |
| 296 | 332 |
*/ |
| 297 | 333 |
# define OMAP_INT_24XX_SYS_NIRQ 7 |
| 334 |
# define OMAP_INT_24XX_L3_IRQ 10 |
|
| 335 |
# define OMAP_INT_24XX_PRCM_MPU_IRQ 11 |
|
| 298 | 336 |
# define OMAP_INT_24XX_SDMA_IRQ0 12 |
| 299 | 337 |
# define OMAP_INT_24XX_SDMA_IRQ1 13 |
| 300 | 338 |
# define OMAP_INT_24XX_SDMA_IRQ2 14 |
| 301 | 339 |
# define OMAP_INT_24XX_SDMA_IRQ3 15 |
| 340 |
# define OMAP_INT_243X_MCBSP2_IRQ 16 |
|
| 341 |
# define OMAP_INT_243X_MCBSP3_IRQ 17 |
|
| 342 |
# define OMAP_INT_243X_MCBSP4_IRQ 18 |
|
| 343 |
# define OMAP_INT_243X_MCBSP5_IRQ 19 |
|
| 344 |
# define OMAP_INT_24XX_GPMC_IRQ 20 |
|
| 345 |
# define OMAP_INT_24XX_GUFFAW_IRQ 21 |
|
| 346 |
# define OMAP_INT_24XX_IVA_IRQ 22 |
|
| 347 |
# define OMAP_INT_24XX_EAC_IRQ 23 |
|
| 302 | 348 |
# define OMAP_INT_24XX_CAM_IRQ 24 |
| 303 | 349 |
# define OMAP_INT_24XX_DSS_IRQ 25 |
| 304 | 350 |
# define OMAP_INT_24XX_MAIL_U0_MPU 26 |
| ... | ... | |
| 308 | 354 |
# define OMAP_INT_24XX_GPIO_BANK2 30 |
| 309 | 355 |
# define OMAP_INT_24XX_GPIO_BANK3 31 |
| 310 | 356 |
# define OMAP_INT_24XX_GPIO_BANK4 32 |
| 311 |
# define OMAP_INT_24XX_GPIO_BANK5 33
|
|
| 357 |
# define OMAP_INT_243X_GPIO_BANK5 33
|
|
| 312 | 358 |
# define OMAP_INT_24XX_MAIL_U3_MPU 34 |
| 359 |
# define OMAP_INT_24XX_WDT3 35 |
|
| 360 |
# define OMAP_INT_24XX_WDT4 36 |
|
| 313 | 361 |
# define OMAP_INT_24XX_GPTIMER1 37 |
| 314 | 362 |
# define OMAP_INT_24XX_GPTIMER2 38 |
| 315 | 363 |
# define OMAP_INT_24XX_GPTIMER3 39 |
| ... | ... | |
| 322 | 370 |
# define OMAP_INT_24XX_GPTIMER10 46 |
| 323 | 371 |
# define OMAP_INT_24XX_GPTIMER11 47 |
| 324 | 372 |
# define OMAP_INT_24XX_GPTIMER12 48 |
| 373 |
# define OMAP_INT_24XX_PKA_IRQ 50 |
|
| 374 |
# define OMAP_INT_24XX_SHA1MD5_IRQ 51 |
|
| 375 |
# define OMAP_INT_24XX_RNG_IRQ 52 |
|
| 376 |
# define OMAP_INT_24XX_MG_IRQ 53 |
|
| 377 |
# define OMAP_INT_24XX_I2C1_IRQ 56 |
|
| 378 |
# define OMAP_INT_24XX_I2C2_IRQ 57 |
|
| 325 | 379 |
# define OMAP_INT_24XX_MCBSP1_IRQ_TX 59 |
| 326 | 380 |
# define OMAP_INT_24XX_MCBSP1_IRQ_RX 60 |
| 327 | 381 |
# define OMAP_INT_24XX_MCBSP2_IRQ_TX 62 |
| 328 | 382 |
# define OMAP_INT_24XX_MCBSP2_IRQ_RX 63 |
| 383 |
# define OMAP_INT_243X_MCBSP1_IRQ 64 |
|
| 384 |
# define OMAP_INT_24XX_MCSPI1_IRQ 65 |
|
| 385 |
# define OMAP_INT_24XX_MCSPI2_IRQ 66 |
|
| 386 |
# define OMAP_INT_24XX_SSI1_IRQ0 67 |
|
| 387 |
# define OMAP_INT_24XX_SSI1_IRQ1 68 |
|
| 388 |
# define OMAP_INT_24XX_SSI2_IRQ0 69 |
|
| 389 |
# define OMAP_INT_24XX_SSI2_IRQ1 70 |
|
| 390 |
# define OMAP_INT_24XX_SSI_GDD_IRQ 71 |
|
| 329 | 391 |
# define OMAP_INT_24XX_UART1_IRQ 72 |
| 330 | 392 |
# define OMAP_INT_24XX_UART2_IRQ 73 |
| 331 | 393 |
# define OMAP_INT_24XX_UART3_IRQ 74 |
| ... | ... | |
| 335 | 397 |
# define OMAP_INT_24XX_USB_IRQ_HGEN 78 |
| 336 | 398 |
# define OMAP_INT_24XX_USB_IRQ_HSOF 79 |
| 337 | 399 |
# define OMAP_INT_24XX_USB_IRQ_OTG 80 |
| 400 |
# define OMAP_INT_24XX_VLYNQ_IRQ 81 |
|
| 338 | 401 |
# define OMAP_INT_24XX_MMC_IRQ 83 |
| 402 |
# define OMAP_INT_24XX_MS_IRQ 84 |
|
| 403 |
# define OMAP_INT_24XX_FAC_IRQ 85 |
|
| 404 |
# define OMAP_INT_24XX_MCSPI3_IRQ 91 |
|
| 339 | 405 |
# define OMAP_INT_243X_HS_USB_MC 92 |
| 340 | 406 |
# define OMAP_INT_243X_HS_USB_DMA 93 |
| 341 | 407 |
# define OMAP_INT_243X_CARKIT 94 |
| 408 |
# define OMAP_INT_34XX_GPTIMER12 95 |
|
| 342 | 409 |
|
| 343 | 410 |
/* omap_dma.c */ |
| 344 | 411 |
enum omap_dma_model {
|
| ... | ... | |
| 352 | 419 |
struct omap_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs, |
| 353 | 420 |
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, |
| 354 | 421 |
enum omap_dma_model model); |
| 422 |
struct omap_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs, |
|
| 423 |
struct omap_mpu_state_s *mpu, int fifo, |
|
| 424 |
int chans, omap_clk iclk, omap_clk fclk); |
|
| 355 | 425 |
void omap_dma_reset(struct omap_dma_s *s); |
| 356 | 426 |
|
| 357 | 427 |
struct dma_irq_map {
|
| ... | ... | |
| 367 | 437 |
tipb, |
| 368 | 438 |
local, /* omap16xx: ocp_t2 */ |
| 369 | 439 |
tipb_mpui, |
| 370 |
omap_dma_port_last, |
|
| 440 |
__omap_dma_port_last,
|
|
| 371 | 441 |
}; |
| 372 | 442 |
|
| 373 | 443 |
typedef enum {
|
| ... | ... | |
| 488 | 558 |
# define OMAP_DMA_MMC2_RX 55 |
| 489 | 559 |
# define OMAP_DMA_CRYPTO_DES_OUT 56 |
| 490 | 560 |
|
| 561 |
/* |
|
| 562 |
* DMA request numbers for the OMAP2 |
|
| 563 |
*/ |
|
| 564 |
# define OMAP24XX_DMA_NO_DEVICE 0 |
|
| 565 |
# define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */ |
|
| 566 |
# define OMAP24XX_DMA_EXT_DMAREQ0 2 |
|
| 567 |
# define OMAP24XX_DMA_EXT_DMAREQ1 3 |
|
| 568 |
# define OMAP24XX_DMA_GPMC 4 |
|
| 569 |
# define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */ |
|
| 570 |
# define OMAP24XX_DMA_DSS 6 |
|
| 571 |
# define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */ |
|
| 572 |
# define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */ |
|
| 573 |
# define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */ |
|
| 574 |
# define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */ |
|
| 575 |
# define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */ |
|
| 576 |
# define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */ |
|
| 577 |
# define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */ |
|
| 578 |
# define OMAP24XX_DMA_EXT_DMAREQ2 14 |
|
| 579 |
# define OMAP24XX_DMA_EXT_DMAREQ3 15 |
|
| 580 |
# define OMAP24XX_DMA_EXT_DMAREQ4 16 |
|
| 581 |
# define OMAP24XX_DMA_EAC_AC_RD 17 |
|
| 582 |
# define OMAP24XX_DMA_EAC_AC_WR 18 |
|
| 583 |
# define OMAP24XX_DMA_EAC_MD_UL_RD 19 |
|
| 584 |
# define OMAP24XX_DMA_EAC_MD_UL_WR 20 |
|
| 585 |
# define OMAP24XX_DMA_EAC_MD_DL_RD 21 |
|
| 586 |
# define OMAP24XX_DMA_EAC_MD_DL_WR 22 |
|
| 587 |
# define OMAP24XX_DMA_EAC_BT_UL_RD 23 |
|
| 588 |
# define OMAP24XX_DMA_EAC_BT_UL_WR 24 |
|
| 589 |
# define OMAP24XX_DMA_EAC_BT_DL_RD 25 |
|
| 590 |
# define OMAP24XX_DMA_EAC_BT_DL_WR 26 |
|
| 591 |
# define OMAP24XX_DMA_I2C1_TX 27 |
|
| 592 |
# define OMAP24XX_DMA_I2C1_RX 28 |
|
| 593 |
# define OMAP24XX_DMA_I2C2_TX 29 |
|
| 594 |
# define OMAP24XX_DMA_I2C2_RX 30 |
|
| 595 |
# define OMAP24XX_DMA_MCBSP1_TX 31 |
|
| 596 |
# define OMAP24XX_DMA_MCBSP1_RX 32 |
|
| 597 |
# define OMAP24XX_DMA_MCBSP2_TX 33 |
|
| 598 |
# define OMAP24XX_DMA_MCBSP2_RX 34 |
|
| 599 |
# define OMAP24XX_DMA_SPI1_TX0 35 |
|
| 600 |
# define OMAP24XX_DMA_SPI1_RX0 36 |
|
| 601 |
# define OMAP24XX_DMA_SPI1_TX1 37 |
|
| 602 |
# define OMAP24XX_DMA_SPI1_RX1 38 |
|
| 603 |
# define OMAP24XX_DMA_SPI1_TX2 39 |
|
| 604 |
# define OMAP24XX_DMA_SPI1_RX2 40 |
|
| 605 |
# define OMAP24XX_DMA_SPI1_TX3 41 |
|
| 606 |
# define OMAP24XX_DMA_SPI1_RX3 42 |
|
| 607 |
# define OMAP24XX_DMA_SPI2_TX0 43 |
|
| 608 |
# define OMAP24XX_DMA_SPI2_RX0 44 |
|
| 609 |
# define OMAP24XX_DMA_SPI2_TX1 45 |
|
| 610 |
# define OMAP24XX_DMA_SPI2_RX1 46 |
|
| 611 |
|
|
| 612 |
# define OMAP24XX_DMA_UART1_TX 49 |
|
| 613 |
# define OMAP24XX_DMA_UART1_RX 50 |
|
| 614 |
# define OMAP24XX_DMA_UART2_TX 51 |
|
| 615 |
# define OMAP24XX_DMA_UART2_RX 52 |
|
| 616 |
# define OMAP24XX_DMA_UART3_TX 53 |
|
| 617 |
# define OMAP24XX_DMA_UART3_RX 54 |
|
| 618 |
# define OMAP24XX_DMA_USB_W2FC_TX0 55 |
|
| 619 |
# define OMAP24XX_DMA_USB_W2FC_RX0 56 |
|
| 620 |
# define OMAP24XX_DMA_USB_W2FC_TX1 57 |
|
| 621 |
# define OMAP24XX_DMA_USB_W2FC_RX1 58 |
|
| 622 |
# define OMAP24XX_DMA_USB_W2FC_TX2 59 |
|
| 623 |
# define OMAP24XX_DMA_USB_W2FC_RX2 60 |
|
| 624 |
# define OMAP24XX_DMA_MMC1_TX 61 |
|
| 625 |
# define OMAP24XX_DMA_MMC1_RX 62 |
|
| 626 |
# define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */ |
|
| 627 |
# define OMAP24XX_DMA_EXT_DMAREQ5 64 |
|
| 628 |
|
|
| 491 | 629 |
/* omap[123].c */ |
| 492 | 630 |
struct omap_mpu_timer_s; |
| 493 | 631 |
struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base, |
| 494 | 632 |
qemu_irq irq, omap_clk clk); |
| 495 | 633 |
|
| 634 |
struct omap_gp_timer_s; |
|
| 635 |
struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, |
|
| 636 |
qemu_irq irq, omap_clk fclk, omap_clk iclk); |
|
| 637 |
|
|
| 496 | 638 |
struct omap_watchdog_timer_s; |
| 497 | 639 |
struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base, |
| 498 | 640 |
qemu_irq irq, omap_clk clk); |
| ... | ... | |
| 501 | 643 |
struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base, |
| 502 | 644 |
qemu_irq irq, omap_clk clk); |
| 503 | 645 |
|
| 646 |
void omap_synctimer_init(struct omap_target_agent_s *ta, |
|
| 647 |
struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk); |
|
| 648 |
|
|
| 504 | 649 |
struct omap_tipb_bridge_s; |
| 505 | 650 |
struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base, |
| 506 | 651 |
qemu_irq abort_irq, omap_clk clk); |
| 507 | 652 |
|
| 508 | 653 |
struct omap_uart_s; |
| 509 | 654 |
struct omap_uart_s *omap_uart_init(target_phys_addr_t base, |
| 510 |
qemu_irq irq, omap_clk clk, CharDriverState *chr); |
|
| 655 |
qemu_irq irq, omap_clk fclk, omap_clk iclk, |
|
| 656 |
qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr); |
|
| 657 |
struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta, |
|
| 658 |
qemu_irq irq, omap_clk fclk, omap_clk iclk, |
|
| 659 |
qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr); |
|
| 660 |
void omap_uart_reset(struct omap_uart_s *s); |
|
| 511 | 661 |
|
| 512 | 662 |
struct omap_mpuio_s; |
| 513 | 663 |
struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base, |
| ... | ... | |
| 523 | 673 |
qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s); |
| 524 | 674 |
void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler); |
| 525 | 675 |
|
| 676 |
struct omap_gpif_s; |
|
| 677 |
struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta, |
|
| 678 |
qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules); |
|
| 679 |
qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start); |
|
| 680 |
void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler); |
|
| 681 |
|
|
| 526 | 682 |
struct uwire_slave_s {
|
| 527 | 683 |
uint16_t (*receive)(void *opaque); |
| 528 | 684 |
void (*send)(void *opaque, uint16_t data); |
| ... | ... | |
| 534 | 690 |
void omap_uwire_attach(struct omap_uwire_s *s, |
| 535 | 691 |
struct uwire_slave_s *slave, int chipselect); |
| 536 | 692 |
|
| 693 |
struct omap_mcspi_s; |
|
| 694 |
struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, |
|
| 695 |
qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk); |
|
| 696 |
void omap_mcspi_attach(struct omap_mcspi_s *s, |
|
| 697 |
uint32_t (*txrx)(void *opaque, uint32_t), void *opaque, |
|
| 698 |
int chipselect); |
|
| 699 |
|
|
| 537 | 700 |
struct omap_rtc_s; |
| 538 | 701 |
struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base, |
| 539 | 702 |
qemu_irq *irq, omap_clk clk); |
| ... | ... | |
| 570 | 733 |
struct omap_lpg_s; |
| 571 | 734 |
struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk); |
| 572 | 735 |
|
| 736 |
void omap_tap_init(struct omap_target_agent_s *ta, |
|
| 737 |
struct omap_mpu_state_s *mpu); |
|
| 738 |
|
|
| 573 | 739 |
/* omap_lcdc.c */ |
| 574 | 740 |
struct omap_lcd_panel_s; |
| 575 | 741 |
void omap_lcdc_reset(struct omap_lcd_panel_s *s); |
| ... | ... | |
| 577 | 743 |
struct omap_dma_lcd_channel_s *dma, DisplayState *ds, |
| 578 | 744 |
ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk); |
| 579 | 745 |
|
| 746 |
/* omap_dss.c */ |
|
| 747 |
struct rfbi_chip_s {
|
|
| 748 |
void *opaque; |
|
| 749 |
void (*write)(void *opaque, int dc, uint16_t value); |
|
| 750 |
void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch); |
|
| 751 |
uint16_t (*read)(void *opaque, int dc); |
|
| 752 |
}; |
|
| 753 |
struct omap_dss_s; |
|
| 754 |
void omap_dss_reset(struct omap_dss_s *s); |
|
| 755 |
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, |
|
| 756 |
target_phys_addr_t l3_base, DisplayState *ds, |
|
| 757 |
qemu_irq irq, qemu_irq drq, |
|
| 758 |
omap_clk fck1, omap_clk fck2, omap_clk ck54m, |
|
| 759 |
omap_clk ick1, omap_clk ick2); |
|
| 760 |
void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip); |
|
| 761 |
|
|
| 580 | 762 |
/* omap_mmc.c */ |
| 581 | 763 |
struct omap_mmc_s; |
| 582 | 764 |
struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base, |
| 583 | 765 |
BlockDriverState *bd, |
| 584 | 766 |
qemu_irq irq, qemu_irq dma[], omap_clk clk); |
| 767 |
struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, |
|
| 768 |
BlockDriverState *bd, qemu_irq irq, qemu_irq dma[], |
|
| 769 |
omap_clk fclk, omap_clk iclk); |
|
| 585 | 770 |
void omap_mmc_reset(struct omap_mmc_s *s); |
| 586 | 771 |
void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); |
| 772 |
void omap_mmc_enable(struct omap_mmc_s *s, int enable); |
|
| 587 | 773 |
|
| 588 | 774 |
/* omap_i2c.c */ |
| 589 | 775 |
struct omap_i2c_s; |
| ... | ... | |
| 596 | 782 |
|
| 597 | 783 |
# define cpu_is_omap310(cpu) (cpu->mpu_model == omap310) |
| 598 | 784 |
# define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510) |
| 785 |
# define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610) |
|
| 786 |
# define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710) |
|
| 787 |
# define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410) |
|
| 788 |
# define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420) |
|
| 789 |
# define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430) |
|
| 790 |
# define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430) |
|
| 791 |
|
|
| 599 | 792 |
# define cpu_is_omap15xx(cpu) \ |
| 600 | 793 |
(cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) |
| 601 |
# define cpu_class_omap1(cpu) 1 |
|
| 794 |
# define cpu_is_omap16xx(cpu) \ |
|
| 795 |
(cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) |
|
| 796 |
# define cpu_is_omap24xx(cpu) \ |
|
| 797 |
(cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu)) |
|
| 798 |
|
|
| 799 |
# define cpu_class_omap1(cpu) \ |
|
| 800 |
(cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu)) |
|
| 801 |
# define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu) |
|
| 802 |
# define cpu_class_omap3(cpu) cpu_is_omap3430(cpu) |
|
| 602 | 803 |
|
| 603 | 804 |
struct omap_mpu_state_s {
|
| 604 |
enum omap1_mpu_model {
|
|
| 805 |
enum omap_mpu_model {
|
|
| 605 | 806 |
omap310, |
| 606 | 807 |
omap1510, |
| 808 |
omap1610, |
|
| 809 |
omap1710, |
|
| 810 |
omap2410, |
|
| 811 |
omap2420, |
|
| 812 |
omap2422, |
|
| 813 |
omap2423, |
|
| 814 |
omap2430, |
|
| 815 |
omap3430, |
|
| 607 | 816 |
} mpu_model; |
| 608 | 817 |
|
| 609 | 818 |
CPUState *env; |
| ... | ... | |
| 620 | 829 |
target_phys_addr_t offset, uint32_t value); |
| 621 | 830 |
int (*addr_valid)(struct omap_mpu_state_s *s, |
| 622 | 831 |
target_phys_addr_t addr); |
| 623 |
} port[omap_dma_port_last]; |
|
| 832 |
} port[__omap_dma_port_last];
|
|
| 624 | 833 |
|
| 625 | 834 |
unsigned long sdram_size; |
| 626 | 835 |
unsigned long sram_size; |
| ... | ... | |
| 656 | 865 |
omap_clk clk; |
| 657 | 866 |
} pwt; |
| 658 | 867 |
|
| 659 |
struct omap_i2c_s *i2c; |
|
| 868 |
struct omap_i2c_s *i2c[2];
|
|
| 660 | 869 |
|
| 661 | 870 |
struct omap_rtc_s *rtc; |
| 662 | 871 |
|
| ... | ... | |
| 722 | 931 |
uint16_t dsp_idlect2; |
| 723 | 932 |
uint16_t dsp_rstct2; |
| 724 | 933 |
} clkm; |
| 725 |
} *omap310_mpu_init(unsigned long sdram_size, |
|
| 934 |
|
|
| 935 |
/* OMAP2-only peripherals */ |
|
| 936 |
struct omap_l4_s *l4; |
|
| 937 |
|
|
| 938 |
struct omap_gp_timer_s *gptimer[12]; |
|
| 939 |
|
|
| 940 |
target_phys_addr_t tap_base; |
|
| 941 |
|
|
| 942 |
struct omap_synctimer_s {
|
|
| 943 |
target_phys_addr_t base; |
|
| 944 |
uint32_t val; |
|
| 945 |
uint16_t readh; |
|
| 946 |
} synctimer; |
|
| 947 |
|
|
| 948 |
struct omap_prcm_s *prcm; |
|
| 949 |
struct omap_sdrc_s *sdrc; |
|
| 950 |
struct omap_gpmc_s *gpmc; |
|
| 951 |
struct omap_sysctl_s *sysc; |
|
| 952 |
|
|
| 953 |
struct omap_gpif_s *gpif; |
|
| 954 |
|
|
| 955 |
struct omap_mcspi_s *mcspi[2]; |
|
| 956 |
|
|
| 957 |
struct omap_dss_s *dss; |
|
| 958 |
}; |
|
| 959 |
|
|
| 960 |
/* omap1.c */ |
|
| 961 |
struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size, |
|
| 962 |
DisplayState *ds, const char *core); |
|
| 963 |
|
|
| 964 |
/* omap2.c */ |
|
| 965 |
struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size, |
|
| 726 | 966 |
DisplayState *ds, const char *core); |
| 727 | 967 |
|
| 728 | 968 |
# if TARGET_PHYS_ADDR_BITS == 32 |
| ... | ... | |
| 743 | 983 |
void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, |
| 744 | 984 |
uint32_t value); |
| 745 | 985 |
|
| 986 |
void omap_mpu_wakeup(void *opaque, int irq, int req); |
|
| 987 |
|
|
| 746 | 988 |
# define OMAP_BAD_REG(paddr) \ |
| 747 |
printf("%s: Bad register " OMAP_FMT_plx "\n", __FUNCTION__, paddr)
|
|
| 989 |
fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \ |
|
| 990 |
__FUNCTION__, paddr) |
|
| 748 | 991 |
# define OMAP_RO_REG(paddr) \ |
| 749 |
printf("%s: Read-only register " OMAP_FMT_plx "\n", \
|
|
| 992 |
fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \
|
|
| 750 | 993 |
__FUNCTION__, paddr) |
| 751 | 994 |
|
| 995 |
/* OMAP-specific Linux bootloader tags for the ATAG_BOARD area |
|
| 996 |
(Board-specifc tags are not here) */ |
|
| 997 |
#define OMAP_TAG_CLOCK 0x4f01 |
|
| 998 |
#define OMAP_TAG_MMC 0x4f02 |
|
| 999 |
#define OMAP_TAG_SERIAL_CONSOLE 0x4f03 |
|
| 1000 |
#define OMAP_TAG_USB 0x4f04 |
|
| 1001 |
#define OMAP_TAG_LCD 0x4f05 |
|
| 1002 |
#define OMAP_TAG_GPIO_SWITCH 0x4f06 |
|
| 1003 |
#define OMAP_TAG_UART 0x4f07 |
|
| 1004 |
#define OMAP_TAG_FBMEM 0x4f08 |
|
| 1005 |
#define OMAP_TAG_STI_CONSOLE 0x4f09 |
|
| 1006 |
#define OMAP_TAG_CAMERA_SENSOR 0x4f0a |
|
| 1007 |
#define OMAP_TAG_PARTITION 0x4f0b |
|
| 1008 |
#define OMAP_TAG_TEA5761 0x4f10 |
|
| 1009 |
#define OMAP_TAG_TMP105 0x4f11 |
|
| 1010 |
#define OMAP_TAG_BOOT_REASON 0x4f80 |
|
| 1011 |
#define OMAP_TAG_FLASH_PART_STR 0x4f81 |
|
| 1012 |
#define OMAP_TAG_VERSION_STR 0x4f82 |
|
| 1013 |
|
|
| 752 | 1014 |
# define TCMI_VERBOSE 1 |
| 753 | 1015 |
//# define MEM_VERBOSE 1 |
| 754 | 1016 |
|
| 755 | 1017 |
# ifdef TCMI_VERBOSE |
| 756 | 1018 |
# define OMAP_8B_REG(paddr) \ |
| 757 |
printf("%s: 8-bit register " OMAP_FMT_plx "\n", \
|
|
| 1019 |
fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \
|
|
| 758 | 1020 |
__FUNCTION__, paddr) |
| 759 | 1021 |
# define OMAP_16B_REG(paddr) \ |
| 760 |
printf("%s: 16-bit register " OMAP_FMT_plx "\n", \
|
|
| 1022 |
fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \
|
|
| 761 | 1023 |
__FUNCTION__, paddr) |
| 762 | 1024 |
# define OMAP_32B_REG(paddr) \ |
| 763 |
printf("%s: 32-bit register " OMAP_FMT_plx "\n", \
|
|
| 1025 |
fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \
|
|
| 764 | 1026 |
__FUNCTION__, paddr) |
| 765 | 1027 |
# else |
| 766 | 1028 |
# define OMAP_8B_REG(paddr) |
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