Revision 827df9f3 hw/omap_clk.c
b/hw/omap_clk.c | ||
---|---|---|
1 | 1 |
/* |
2 | 2 |
* OMAP clocks. |
3 | 3 |
* |
4 |
* Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
|
|
4 |
* Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
|
|
5 | 5 |
* |
6 | 6 |
* Clocks data comes in part from arch/arm/mach-omap1/clock.h in Linux. |
7 | 7 |
* |
... | ... | |
34 | 34 |
#define CLOCK_IN_OMAP730 (1 << 11) |
35 | 35 |
#define CLOCK_IN_OMAP1510 (1 << 12) |
36 | 36 |
#define CLOCK_IN_OMAP16XX (1 << 13) |
37 |
#define CLOCK_IN_OMAP242X (1 << 14) |
|
38 |
#define CLOCK_IN_OMAP243X (1 << 15) |
|
39 |
#define CLOCK_IN_OMAP343X (1 << 16) |
|
37 | 40 |
uint32_t flags; |
38 | 41 |
int id; |
39 | 42 |
|
... | ... | |
55 | 58 |
static struct clk xtal_osc32k = { |
56 | 59 |
.name = "xtal_osc_32k", |
57 | 60 |
.rate = 32768, |
58 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
|
61 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
|
62 |
CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
59 | 63 |
}; |
60 | 64 |
|
61 | 65 |
static struct clk ck_ref = { |
... | ... | |
502 | 506 |
static struct clk clk32k = { |
503 | 507 |
.name = "clk32-kHz", |
504 | 508 |
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
505 |
ALWAYS_ENABLED, |
|
506 |
.parent = &xtal_osc32k, |
|
509 |
CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
|
510 |
.parent = &xtal_osc32k, |
|
511 |
}; |
|
512 |
|
|
513 |
static struct clk apll_96m = { |
|
514 |
.name = "apll_96m", |
|
515 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
|
516 |
.rate = 96000000, |
|
517 |
/*.parent = sys.xtalin */ |
|
518 |
}; |
|
519 |
|
|
520 |
static struct clk apll_54m = { |
|
521 |
.name = "apll_54m", |
|
522 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
|
523 |
.rate = 54000000, |
|
524 |
/*.parent = sys.xtalin */ |
|
525 |
}; |
|
526 |
|
|
527 |
static struct clk sys_clk = { |
|
528 |
.name = "sys_clk", |
|
529 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
|
530 |
.rate = 32768, |
|
531 |
/*.parent = sys.xtalin */ |
|
532 |
}; |
|
533 |
|
|
534 |
static struct clk sleep_clk = { |
|
535 |
.name = "sleep_clk", |
|
536 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
|
537 |
.rate = 32768, |
|
538 |
/*.parent = sys.xtalin */ |
|
539 |
}; |
|
540 |
|
|
541 |
static struct clk dpll_ck = { |
|
542 |
.name = "dpll", |
|
543 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
|
544 |
/*.parent = sys.xtalin */ |
|
545 |
}; |
|
546 |
|
|
547 |
static struct clk dpll_x2_ck = { |
|
548 |
.name = "dpll_x2", |
|
549 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
|
550 |
/*.parent = sys.xtalin */ |
|
551 |
}; |
|
552 |
|
|
553 |
static struct clk wdt1_sys_clk = { |
|
554 |
.name = "wdt1_sys_clk", |
|
555 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
|
556 |
.rate = 32768, |
|
557 |
/*.parent = sys.xtalin */ |
|
558 |
}; |
|
559 |
|
|
560 |
static struct clk func_96m_clk = { |
|
561 |
.name = "func_96m_clk", |
|
562 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
563 |
.divisor = 1, |
|
564 |
.parent = &apll_96m, |
|
565 |
}; |
|
566 |
|
|
567 |
static struct clk func_48m_clk = { |
|
568 |
.name = "func_48m_clk", |
|
569 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
570 |
.divisor = 2, |
|
571 |
.parent = &apll_96m, |
|
572 |
}; |
|
573 |
|
|
574 |
static struct clk func_12m_clk = { |
|
575 |
.name = "func_12m_clk", |
|
576 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
577 |
.divisor = 8, |
|
578 |
.parent = &apll_96m, |
|
579 |
}; |
|
580 |
|
|
581 |
static struct clk func_54m_clk = { |
|
582 |
.name = "func_54m_clk", |
|
583 |
.flags = CLOCK_IN_OMAP242X, |
|
584 |
.divisor = 1, |
|
585 |
.parent = &apll_54m, |
|
586 |
}; |
|
587 |
|
|
588 |
static struct clk sys_clkout = { |
|
589 |
.name = "clkout", |
|
590 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
591 |
.parent = &sys_clk, |
|
592 |
}; |
|
593 |
|
|
594 |
static struct clk sys_clkout2 = { |
|
595 |
.name = "clkout2", |
|
596 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
597 |
.parent = &sys_clk, |
|
598 |
}; |
|
599 |
|
|
600 |
static struct clk core_clk = { |
|
601 |
.name = "core_clk", |
|
602 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
603 |
.parent = &dpll_ck, |
|
604 |
}; |
|
605 |
|
|
606 |
static struct clk l3_clk = { |
|
607 |
.name = "l3_clk", |
|
608 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
609 |
.parent = &core_clk, |
|
610 |
}; |
|
611 |
|
|
612 |
static struct clk core_l4_iclk = { |
|
613 |
.name = "core_l4_iclk", |
|
614 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
615 |
.parent = &l3_clk, |
|
616 |
}; |
|
617 |
|
|
618 |
static struct clk wu_l4_iclk = { |
|
619 |
.name = "wu_l4_iclk", |
|
620 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
621 |
.parent = &l3_clk, |
|
622 |
}; |
|
623 |
|
|
624 |
static struct clk core_l3_iclk = { |
|
625 |
.name = "core_l3_iclk", |
|
626 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
627 |
.parent = &core_clk, |
|
628 |
}; |
|
629 |
|
|
630 |
static struct clk core_l4_usb_clk = { |
|
631 |
.name = "core_l4_usb_clk", |
|
632 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
633 |
.parent = &l3_clk, |
|
634 |
}; |
|
635 |
|
|
636 |
static struct clk wu_gpt1_clk = { |
|
637 |
.name = "wu_gpt1_clk", |
|
638 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
639 |
.parent = &sys_clk, |
|
640 |
}; |
|
641 |
|
|
642 |
static struct clk wu_32k_clk = { |
|
643 |
.name = "wu_32k_clk", |
|
644 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
645 |
.parent = &sys_clk, |
|
646 |
}; |
|
647 |
|
|
648 |
static struct clk uart1_fclk = { |
|
649 |
.name = "uart1_fclk", |
|
650 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
651 |
.parent = &func_48m_clk, |
|
652 |
}; |
|
653 |
|
|
654 |
static struct clk uart1_iclk = { |
|
655 |
.name = "uart1_iclk", |
|
656 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
657 |
.parent = &core_l4_iclk, |
|
658 |
}; |
|
659 |
|
|
660 |
static struct clk uart2_fclk = { |
|
661 |
.name = "uart2_fclk", |
|
662 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
663 |
.parent = &func_48m_clk, |
|
664 |
}; |
|
665 |
|
|
666 |
static struct clk uart2_iclk = { |
|
667 |
.name = "uart2_iclk", |
|
668 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
669 |
.parent = &core_l4_iclk, |
|
670 |
}; |
|
671 |
|
|
672 |
static struct clk uart3_fclk = { |
|
673 |
.name = "uart3_fclk", |
|
674 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
675 |
.parent = &func_48m_clk, |
|
676 |
}; |
|
677 |
|
|
678 |
static struct clk uart3_iclk = { |
|
679 |
.name = "uart3_iclk", |
|
680 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
681 |
.parent = &core_l4_iclk, |
|
682 |
}; |
|
683 |
|
|
684 |
static struct clk mpu_fclk = { |
|
685 |
.name = "mpu_fclk", |
|
686 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
687 |
.parent = &core_clk, |
|
688 |
}; |
|
689 |
|
|
690 |
static struct clk mpu_iclk = { |
|
691 |
.name = "mpu_iclk", |
|
692 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
693 |
.parent = &core_clk, |
|
694 |
}; |
|
695 |
|
|
696 |
static struct clk int_m_fclk = { |
|
697 |
.name = "int_m_fclk", |
|
698 |
.alias = "mpu_intc_fclk", |
|
699 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
700 |
.parent = &core_clk, |
|
701 |
}; |
|
702 |
|
|
703 |
static struct clk int_m_iclk = { |
|
704 |
.name = "int_m_iclk", |
|
705 |
.alias = "mpu_intc_iclk", |
|
706 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
707 |
.parent = &core_clk, |
|
708 |
}; |
|
709 |
|
|
710 |
static struct clk core_gpt2_clk = { |
|
711 |
.name = "core_gpt2_clk", |
|
712 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
713 |
.parent = &sys_clk, |
|
714 |
}; |
|
715 |
|
|
716 |
static struct clk core_gpt3_clk = { |
|
717 |
.name = "core_gpt3_clk", |
|
718 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
719 |
.parent = &sys_clk, |
|
720 |
}; |
|
721 |
|
|
722 |
static struct clk core_gpt4_clk = { |
|
723 |
.name = "core_gpt4_clk", |
|
724 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
725 |
.parent = &sys_clk, |
|
726 |
}; |
|
727 |
|
|
728 |
static struct clk core_gpt5_clk = { |
|
729 |
.name = "core_gpt5_clk", |
|
730 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
731 |
.parent = &sys_clk, |
|
732 |
}; |
|
733 |
|
|
734 |
static struct clk core_gpt6_clk = { |
|
735 |
.name = "core_gpt6_clk", |
|
736 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
737 |
.parent = &sys_clk, |
|
738 |
}; |
|
739 |
|
|
740 |
static struct clk core_gpt7_clk = { |
|
741 |
.name = "core_gpt7_clk", |
|
742 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
743 |
.parent = &sys_clk, |
|
744 |
}; |
|
745 |
|
|
746 |
static struct clk core_gpt8_clk = { |
|
747 |
.name = "core_gpt8_clk", |
|
748 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
749 |
.parent = &sys_clk, |
|
750 |
}; |
|
751 |
|
|
752 |
static struct clk core_gpt9_clk = { |
|
753 |
.name = "core_gpt9_clk", |
|
754 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
755 |
.parent = &sys_clk, |
|
756 |
}; |
|
757 |
|
|
758 |
static struct clk core_gpt10_clk = { |
|
759 |
.name = "core_gpt10_clk", |
|
760 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
761 |
.parent = &sys_clk, |
|
762 |
}; |
|
763 |
|
|
764 |
static struct clk core_gpt11_clk = { |
|
765 |
.name = "core_gpt11_clk", |
|
766 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
767 |
.parent = &sys_clk, |
|
768 |
}; |
|
769 |
|
|
770 |
static struct clk core_gpt12_clk = { |
|
771 |
.name = "core_gpt12_clk", |
|
772 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
773 |
.parent = &sys_clk, |
|
774 |
}; |
|
775 |
|
|
776 |
static struct clk mcbsp1_clk = { |
|
777 |
.name = "mcbsp1_cg", |
|
778 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
779 |
.divisor = 2, |
|
780 |
.parent = &func_96m_clk, |
|
781 |
}; |
|
782 |
|
|
783 |
static struct clk mcbsp2_clk = { |
|
784 |
.name = "mcbsp2_cg", |
|
785 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
786 |
.divisor = 2, |
|
787 |
.parent = &func_96m_clk, |
|
788 |
}; |
|
789 |
|
|
790 |
static struct clk emul_clk = { |
|
791 |
.name = "emul_ck", |
|
792 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
793 |
.parent = &func_54m_clk, |
|
794 |
}; |
|
795 |
|
|
796 |
static struct clk sdma_fclk = { |
|
797 |
.name = "sdma_fclk", |
|
798 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
799 |
.parent = &l3_clk, |
|
800 |
}; |
|
801 |
|
|
802 |
static struct clk sdma_iclk = { |
|
803 |
.name = "sdma_iclk", |
|
804 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
805 |
.parent = &core_l3_iclk, /* core_l4_iclk for the configuration port */ |
|
806 |
}; |
|
807 |
|
|
808 |
static struct clk i2c1_fclk = { |
|
809 |
.name = "i2c1.fclk", |
|
810 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
811 |
.parent = &func_12m_clk, |
|
812 |
.divisor = 1, |
|
813 |
}; |
|
814 |
|
|
815 |
static struct clk i2c1_iclk = { |
|
816 |
.name = "i2c1.iclk", |
|
817 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
818 |
.parent = &core_l4_iclk, |
|
819 |
}; |
|
820 |
|
|
821 |
static struct clk i2c2_fclk = { |
|
822 |
.name = "i2c2.fclk", |
|
823 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
824 |
.parent = &func_12m_clk, |
|
825 |
.divisor = 1, |
|
826 |
}; |
|
827 |
|
|
828 |
static struct clk i2c2_iclk = { |
|
829 |
.name = "i2c2.iclk", |
|
830 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
831 |
.parent = &core_l4_iclk, |
|
832 |
}; |
|
833 |
|
|
834 |
static struct clk gpio_dbclk[4] = { |
|
835 |
{ |
|
836 |
.name = "gpio1_dbclk", |
|
837 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
838 |
.parent = &wu_32k_clk, |
|
839 |
}, { |
|
840 |
.name = "gpio2_dbclk", |
|
841 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
842 |
.parent = &wu_32k_clk, |
|
843 |
}, { |
|
844 |
.name = "gpio3_dbclk", |
|
845 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
846 |
.parent = &wu_32k_clk, |
|
847 |
}, { |
|
848 |
.name = "gpio4_dbclk", |
|
849 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
850 |
.parent = &wu_32k_clk, |
|
851 |
}, |
|
852 |
}; |
|
853 |
|
|
854 |
static struct clk gpio_iclk = { |
|
855 |
.name = "gpio_iclk", |
|
856 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
857 |
.parent = &wu_l4_iclk, |
|
858 |
}; |
|
859 |
|
|
860 |
static struct clk mmc_fck = { |
|
861 |
.name = "mmc_fclk", |
|
862 |
.flags = CLOCK_IN_OMAP242X, |
|
863 |
.parent = &func_96m_clk, |
|
864 |
}; |
|
865 |
|
|
866 |
static struct clk mmc_ick = { |
|
867 |
.name = "mmc_iclk", |
|
868 |
.flags = CLOCK_IN_OMAP242X, |
|
869 |
.parent = &core_l4_iclk, |
|
870 |
}; |
|
871 |
|
|
872 |
static struct clk spi_fclk[3] = { |
|
873 |
{ |
|
874 |
.name = "spi1_fclk", |
|
875 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
876 |
.parent = &func_48m_clk, |
|
877 |
}, { |
|
878 |
.name = "spi2_fclk", |
|
879 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
880 |
.parent = &func_48m_clk, |
|
881 |
}, { |
|
882 |
.name = "spi3_fclk", |
|
883 |
.flags = CLOCK_IN_OMAP243X, |
|
884 |
.parent = &func_48m_clk, |
|
885 |
}, |
|
886 |
}; |
|
887 |
|
|
888 |
static struct clk dss_clk[2] = { |
|
889 |
{ |
|
890 |
.name = "dss_clk1", |
|
891 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
892 |
.parent = &core_clk, |
|
893 |
}, { |
|
894 |
.name = "dss_clk2", |
|
895 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
896 |
.parent = &sys_clk, |
|
897 |
}, |
|
898 |
}; |
|
899 |
|
|
900 |
static struct clk dss_54m_clk = { |
|
901 |
.name = "dss_54m_clk", |
|
902 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
903 |
.parent = &func_54m_clk, |
|
904 |
}; |
|
905 |
|
|
906 |
static struct clk dss_l3_iclk = { |
|
907 |
.name = "dss_l3_iclk", |
|
908 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
909 |
.parent = &core_l3_iclk, |
|
910 |
}; |
|
911 |
|
|
912 |
static struct clk dss_l4_iclk = { |
|
913 |
.name = "dss_l4_iclk", |
|
914 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
915 |
.parent = &core_l4_iclk, |
|
916 |
}; |
|
917 |
|
|
918 |
static struct clk spi_iclk[3] = { |
|
919 |
{ |
|
920 |
.name = "spi1_iclk", |
|
921 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
922 |
.parent = &core_l4_iclk, |
|
923 |
}, { |
|
924 |
.name = "spi2_iclk", |
|
925 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
926 |
.parent = &core_l4_iclk, |
|
927 |
}, { |
|
928 |
.name = "spi3_iclk", |
|
929 |
.flags = CLOCK_IN_OMAP243X, |
|
930 |
.parent = &core_l4_iclk, |
|
931 |
}, |
|
932 |
}; |
|
933 |
|
|
934 |
static struct clk omapctrl_clk = { |
|
935 |
.name = "omapctrl_iclk", |
|
936 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
|
937 |
/* XXX Should be in WKUP domain */ |
|
938 |
.parent = &core_l4_iclk, |
|
507 | 939 |
}; |
508 | 940 |
|
509 | 941 |
static struct clk *onchip_clks[] = { |
942 |
/* OMAP 1 */ |
|
943 |
|
|
510 | 944 |
/* non-ULPD clocks */ |
511 | 945 |
&xtal_osc12m, |
512 | 946 |
&xtal_osc32k, |
... | ... | |
572 | 1006 |
/* Virtual clocks */ |
573 | 1007 |
&i2c_fck, |
574 | 1008 |
&i2c_ick, |
1009 |
|
|
1010 |
/* OMAP 2 */ |
|
1011 |
|
|
1012 |
&apll_96m, |
|
1013 |
&apll_54m, |
|
1014 |
&sys_clk, |
|
1015 |
&sleep_clk, |
|
1016 |
&dpll_ck, |
|
1017 |
&dpll_x2_ck, |
|
1018 |
&wdt1_sys_clk, |
|
1019 |
&func_96m_clk, |
|
1020 |
&func_48m_clk, |
|
1021 |
&func_12m_clk, |
|
1022 |
&func_54m_clk, |
|
1023 |
&sys_clkout, |
|
1024 |
&sys_clkout2, |
|
1025 |
&core_clk, |
|
1026 |
&l3_clk, |
|
1027 |
&core_l4_iclk, |
|
1028 |
&wu_l4_iclk, |
|
1029 |
&core_l3_iclk, |
|
1030 |
&core_l4_usb_clk, |
|
1031 |
&wu_gpt1_clk, |
|
1032 |
&wu_32k_clk, |
|
1033 |
&uart1_fclk, |
|
1034 |
&uart1_iclk, |
|
1035 |
&uart2_fclk, |
|
1036 |
&uart2_iclk, |
|
1037 |
&uart3_fclk, |
|
1038 |
&uart3_iclk, |
|
1039 |
&mpu_fclk, |
|
1040 |
&mpu_iclk, |
|
1041 |
&int_m_fclk, |
|
1042 |
&int_m_iclk, |
|
1043 |
&core_gpt2_clk, |
|
1044 |
&core_gpt3_clk, |
|
1045 |
&core_gpt4_clk, |
|
1046 |
&core_gpt5_clk, |
|
1047 |
&core_gpt6_clk, |
|
1048 |
&core_gpt7_clk, |
|
1049 |
&core_gpt8_clk, |
|
1050 |
&core_gpt9_clk, |
|
1051 |
&core_gpt10_clk, |
|
1052 |
&core_gpt11_clk, |
|
1053 |
&core_gpt12_clk, |
|
1054 |
&mcbsp1_clk, |
|
1055 |
&mcbsp2_clk, |
|
1056 |
&emul_clk, |
|
1057 |
&sdma_fclk, |
|
1058 |
&sdma_iclk, |
|
1059 |
&i2c1_fclk, |
|
1060 |
&i2c1_iclk, |
|
1061 |
&i2c2_fclk, |
|
1062 |
&i2c2_iclk, |
|
1063 |
&gpio_dbclk[0], |
|
1064 |
&gpio_dbclk[1], |
|
1065 |
&gpio_dbclk[2], |
|
1066 |
&gpio_dbclk[3], |
|
1067 |
&gpio_iclk, |
|
1068 |
&mmc_fck, |
|
1069 |
&mmc_ick, |
|
1070 |
&spi_fclk[0], |
|
1071 |
&spi_iclk[0], |
|
1072 |
&spi_fclk[1], |
|
1073 |
&spi_iclk[1], |
|
1074 |
&spi_fclk[2], |
|
1075 |
&spi_iclk[2], |
|
1076 |
&dss_clk[0], |
|
1077 |
&dss_clk[1], |
|
1078 |
&dss_54m_clk, |
|
1079 |
&dss_l3_iclk, |
|
1080 |
&dss_l4_iclk, |
|
1081 |
&omapctrl_clk, |
|
1082 |
|
|
575 | 1083 |
0 |
576 | 1084 |
}; |
577 | 1085 |
|
... | ... | |
727 | 1235 |
flag = CLOCK_IN_OMAP310; |
728 | 1236 |
else if (cpu_is_omap1510(mpu)) |
729 | 1237 |
flag = CLOCK_IN_OMAP1510; |
1238 |
else if (cpu_is_omap2410(mpu) || cpu_is_omap2420(mpu)) |
|
1239 |
flag = CLOCK_IN_OMAP242X; |
|
1240 |
else if (cpu_is_omap2430(mpu)) |
|
1241 |
flag = CLOCK_IN_OMAP243X; |
|
1242 |
else if (cpu_is_omap3430(mpu)) |
|
1243 |
flag = CLOCK_IN_OMAP243X; |
|
730 | 1244 |
else |
731 | 1245 |
return; |
732 | 1246 |
|
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