Revision 827df9f3 target-arm/helper.c

b/target-arm/helper.c
55 55 
        env->cp15.c0_cachetype = 0x1dd20d2;
56 56 
        env->cp15.c1_sys = 0x00090078;
57 57 
        break;
58 
    case ARM_CPUID_ARM1136_R2:
58 59 
    case ARM_CPUID_ARM1136:
59 60 
        set_feature(env, ARM_FEATURE_V6);
60 61 
        set_feature(env, ARM_FEATURE_VFP);
......
206 207 
    { ARM_CPUID_ARM946, "arm946"},
207 208 
    { ARM_CPUID_ARM1026, "arm1026"},
208 209 
    { ARM_CPUID_ARM1136, "arm1136"},
210 
    { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
209 211 
    { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
210 212 
    { ARM_CPUID_CORTEXM3, "cortex-m3"},
211 213 
    { ARM_CPUID_CORTEXA8, "cortex-a8"},
......
1582 1584 
            case ARM_CPUID_ARM1026:
1583 1585 
                return 1;
1584 1586 
            case ARM_CPUID_ARM1136:
1587 
            case ARM_CPUID_ARM1136_R2:
1585 1588 
                return 7;
1586 1589 
            case ARM_CPUID_ARM11MPCORE:
1587 1590 
                return 1;
......
1762 1765 
            case 8: /* TI925T_status */
1763 1766 
                return 0;
1764 1767 
            }
1768 
            /* TODO: Peripheral port remap register:
1769 
             * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
1770 
             * controller base address at $rn & ~0xfff and map size of
1771 
             * 0x200 << ($rn & 0xfff), when MMU is off.  */
1765 1772 
            goto bad_reg;
1766 1773 
        }
1767 1774 
        return 0;

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