Revision 833ed386
| b/target-sh4/cpu.h | ||
|---|---|---|
| 117 | 117 |
CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */ |
| 118 | 118 |
tlb_t itlb[ITLB_SIZE]; /* instruction translation table */ |
| 119 | 119 |
void *intc_handle; |
| 120 |
int intr_at_halt; /* SR_BL ignored during sleep */ |
|
| 120 | 121 |
} CPUSH4State; |
| 121 | 122 |
|
| 122 | 123 |
CPUSH4State *cpu_sh4_init(const char *cpu_model); |
| b/target-sh4/exec.h | ||
|---|---|---|
| 41 | 41 |
return 0; |
| 42 | 42 |
if (env->interrupt_request & CPU_INTERRUPT_HARD) {
|
| 43 | 43 |
env->halted = 0; |
| 44 |
env->intr_at_halt = 1; |
|
| 44 | 45 |
return 0; |
| 45 | 46 |
} |
| 46 | 47 |
return EXCP_HALTED; |
| b/target-sh4/helper.c | ||
|---|---|---|
| 87 | 87 |
if (do_exp && env->exception_index != 0x1e0) {
|
| 88 | 88 |
env->exception_index = 0x000; /* masked exception -> reset */ |
| 89 | 89 |
} |
| 90 |
if (do_irq) {
|
|
| 90 |
if (do_irq && !env->intr_at_halt) {
|
|
| 91 | 91 |
return; /* masked */ |
| 92 | 92 |
} |
| 93 |
env->intr_at_halt = 0; |
|
| 93 | 94 |
} |
| 94 | 95 |
|
| 95 | 96 |
if (do_irq) {
|
| b/target-sh4/op.c | ||
|---|---|---|
| 1091 | 1091 |
cpu_loop_exit(); |
| 1092 | 1092 |
} |
| 1093 | 1093 |
|
| 1094 |
void OPPROTO op_sleep(void) |
|
| 1095 |
{
|
|
| 1096 |
env->halted = 1; |
|
| 1097 |
env->exception_index = EXCP_HLT; |
|
| 1098 |
cpu_loop_exit(); |
|
| 1099 |
} |
|
| 1100 |
|
|
| 1094 | 1101 |
/* Load and store */ |
| 1095 | 1102 |
#define MEMSUFFIX _raw |
| 1096 | 1103 |
#include "op_mem.c" |
| b/target-sh4/translate.c | ||
|---|---|---|
| 298 | 298 |
case 0x0009: /* nop */ |
| 299 | 299 |
return; |
| 300 | 300 |
case 0x001b: /* sleep */ |
| 301 |
assert(0); /* XXXXX */ |
|
| 301 |
if (ctx->memidx) {
|
|
| 302 |
gen_op_sleep(); |
|
| 303 |
} else {
|
|
| 304 |
gen_op_raise_illegal_instruction(); |
|
| 305 |
ctx->bstate = BS_EXCP; |
|
| 306 |
} |
|
| 302 | 307 |
return; |
| 303 | 308 |
} |
| 304 | 309 |
|
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