Revision 83469015 target-sparc/helper.c
| b/target-sparc/helper.c | ||
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| 1 | 1 |
/* |
| 2 | 2 |
* sparc helpers |
| 3 | 3 |
* |
| 4 |
* Copyright (c) 2003 Fabrice Bellard |
|
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* Copyright (c) 2003-2005 Fabrice Bellard
|
|
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* |
| 6 | 6 |
* This library is free software; you can redistribute it and/or |
| 7 | 7 |
* modify it under the terms of the GNU Lesser General Public |
| ... | ... | |
| 28 | 28 |
#include "cpu.h" |
| 29 | 29 |
#include "exec-all.h" |
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|
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//#define DEBUG_PCALL |
|
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//#define DEBUG_MMU |
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|
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/* Sparc MMU emulation */ |
| ... | ... | |
| 62 | 61 |
#else |
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|
| 64 | 63 |
#ifndef TARGET_SPARC64 |
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/* |
|
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* Sparc V8 Reference MMU (SRMMU) |
|
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*/ |
|
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static const int access_table[8][8] = {
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{ 0, 0, 0, 0, 2, 0, 3, 3 },
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{ 0, 0, 0, 0, 2, 0, 0, 0 },
|
| ... | ... | |
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} |
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} |
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#else |
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/* |
|
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* UltraSparc IIi I/DMMUs |
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*/ |
|
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static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot, |
| 233 | 238 |
int *access_index, target_ulong address, int rw, |
| 234 | 239 |
int is_user) |
| ... | ... | |
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unsigned int i; |
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|
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if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
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*physical = address & 0xffffffff;
|
|
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*physical = address; |
|
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*prot = PAGE_READ | PAGE_WRITE; |
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return 0; |
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} |
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|
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for (i = 0; i < 64; i++) {
|
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if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
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|
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switch (env->dtlb_tte[i] >> 60) {
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default: |
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case 0x4: // 8k |
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mask = 0xffffffffffffe000ULL; |
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break; |
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case 0x5: // 64k |
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mask = 0xffffffffffff0000ULL; |
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break; |
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case 0x6: // 512k |
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mask = 0xfffffffffff80000ULL; |
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break; |
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case 0x7: // 4M |
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mask = 0xffffffffffc00000ULL; |
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break; |
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} |
|
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// ctx match, vaddr match? |
|
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if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) && |
|
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(address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
|
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// access ok? |
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if (((env->dtlb_tte[i] & 0x4) && !(env->pstate & PS_PRIV)) || |
|
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(!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
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env->exception_index = TT_DFAULT; |
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return 1; |
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} |
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*physical = env->dtlb_tte[i] & 0xffffe000; |
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*prot = PAGE_READ; |
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if (env->dtlb_tte[i] & 0x2) |
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*prot |= PAGE_WRITE; |
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return 0; |
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switch ((env->dtlb_tte[i] >> 61) & 3) {
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default: |
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case 0x0: // 8k |
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mask = 0xffffffffffffe000ULL; |
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break; |
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case 0x1: // 64k |
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mask = 0xffffffffffff0000ULL; |
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break; |
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case 0x2: // 512k |
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mask = 0xfffffffffff80000ULL; |
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break; |
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case 0x3: // 4M |
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mask = 0xffffffffffc00000ULL; |
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break; |
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} |
|
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// ctx match, vaddr match? |
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if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) && |
|
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(address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
|
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// valid, access ok? |
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if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 || |
|
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((env->dtlb_tte[i] & 0x4) && is_user) || |
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(!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
|
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if (env->dmmuregs[3]) /* Fault status register */ |
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env->dmmuregs[3] = 2; /* overflow (not read before another fault) */ |
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env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1; |
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env->dmmuregs[4] = address; /* Fault address register */ |
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env->exception_index = TT_DFAULT; |
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#ifdef DEBUG_MMU |
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printf("DFAULT at 0x%llx\n", address);
|
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#endif |
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return 1; |
|
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} |
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*physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL); |
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*prot = PAGE_READ; |
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if (env->dtlb_tte[i] & 0x2) |
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*prot |= PAGE_WRITE; |
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return 0; |
|
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} |
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} |
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env->exception_index = TT_DFAULT; |
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#ifdef DEBUG_MMU |
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printf("DMISS at 0x%llx\n", address);
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#endif |
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env->exception_index = TT_DMISS; |
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return 1; |
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} |
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|
| ... | ... | |
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unsigned int i; |
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|
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if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
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*physical = address & 0xffffffff;
|
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*physical = address; |
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*prot = PAGE_READ; |
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return 0; |
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} |
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|
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for (i = 0; i < 64; i++) {
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if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
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switch (env->itlb_tte[i] >> 60) {
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default: |
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case 0x4: // 8k |
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mask = 0xffffffffffffe000ULL; |
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break; |
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case 0x5: // 64k |
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mask = 0xffffffffffff0000ULL; |
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break; |
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case 0x6: // 512k |
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mask = 0xfffffffffff80000ULL; |
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break; |
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case 0x7: // 4M |
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mask = 0xffffffffffc00000ULL; |
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switch ((env->itlb_tte[i] >> 61) & 3) {
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default: |
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case 0x0: // 8k |
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mask = 0xffffffffffffe000ULL; |
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break; |
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case 0x1: // 64k |
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mask = 0xffffffffffff0000ULL; |
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break; |
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case 0x2: // 512k |
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mask = 0xfffffffffff80000ULL; |
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break; |
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case 0x3: // 4M |
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mask = 0xffffffffffc00000ULL; |
|
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break; |
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} |
|
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// ctx match, vaddr match? |
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if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) && |
|
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(address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
|
|
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// valid, access ok? |
|
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if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 || |
|
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((env->itlb_tte[i] & 0x4) && is_user)) {
|
|
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if (env->immuregs[3]) /* Fault status register */ |
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env->immuregs[3] = 2; /* overflow (not read before another fault) */ |
|
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env->immuregs[3] |= (is_user << 3) | 1; |
|
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env->exception_index = TT_TFAULT; |
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#ifdef DEBUG_MMU |
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printf("TFAULT at 0x%llx\n", address);
|
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#endif |
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return 1; |
|
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} |
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// ctx match, vaddr match? |
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if (env->immuregs[1] == (env->itlb_tag[i] & 0x1fff) && |
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(address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
|
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// access ok? |
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if ((env->itlb_tte[i] & 0x4) && !(env->pstate & PS_PRIV)) {
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env->exception_index = TT_TFAULT; |
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return 1; |
|
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} |
|
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*physical = env->itlb_tte[i] & 0xffffe000; |
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*prot = PAGE_READ; |
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return 0; |
|
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} |
|
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*physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL); |
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*prot = PAGE_READ; |
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return 0; |
|
| 324 | 344 |
} |
| 325 | 345 |
} |
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env->exception_index = TT_TFAULT; |
|
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#ifdef DEBUG_MMU |
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printf("TMISS at 0x%llx\n", address);
|
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#endif |
|
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env->exception_index = TT_TMISS; |
|
| 327 | 350 |
return 1; |
| 328 | 351 |
} |
| 329 | 352 |
|
| ... | ... | |
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int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
| 342 | 365 |
int is_user, int is_softmmu) |
| 343 | 366 |
{
|
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target_ulong virt_addr; |
|
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target_ulong virt_addr, vaddr;
|
|
| 345 | 368 |
target_phys_addr_t paddr; |
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unsigned long vaddr; |
|
| 347 | 369 |
int error_code = 0, prot, ret = 0, access_index; |
| 348 | 370 |
|
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error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user); |
| 350 | 372 |
if (error_code == 0) {
|
| 351 | 373 |
virt_addr = address & TARGET_PAGE_MASK; |
| 352 | 374 |
vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1)); |
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#ifdef DEBUG_MMU |
|
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printf("Translate at 0x%llx -> 0x%llx, vaddr 0x%llx\n", address, paddr, vaddr);
|
|
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#endif |
|
| 353 | 378 |
ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu); |
| 354 | 379 |
return ret; |
| 355 | 380 |
} |
| ... | ... | |
| 471 | 496 |
printf("MMU dump ends\n");
|
| 472 | 497 |
} |
| 473 | 498 |
#endif |
| 499 |
#else |
|
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#ifdef DEBUG_MMU |
|
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void dump_mmu(CPUState *env) |
|
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{
|
|
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unsigned int i; |
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const char *mask; |
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|
|
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printf("MMU contexts: Primary: %lld, Secondary: %lld\n", env->dmmuregs[1], env->dmmuregs[2]);
|
|
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if ((env->lsu & DMMU_E) == 0) {
|
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printf("DMMU disabled\n");
|
|
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} else {
|
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printf("DMMU dump:\n");
|
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for (i = 0; i < 64; i++) {
|
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switch ((env->dtlb_tte[i] >> 61) & 3) {
|
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default: |
|
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case 0x0: |
|
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mask = " 8k"; |
|
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break; |
|
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case 0x1: |
|
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mask = " 64k"; |
|
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break; |
|
| 520 |
case 0x2: |
|
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mask = "512k"; |
|
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break; |
|
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case 0x3: |
|
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mask = " 4M"; |
|
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break; |
|
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} |
|
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if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
|
|
| 528 |
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %lld\n",
|
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env->dtlb_tag[i] & ~0x1fffULL, |
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env->dtlb_tte[i] & 0x1ffffffe000ULL, |
|
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mask, |
|
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env->dtlb_tte[i] & 0x4? "priv": "user", |
|
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env->dtlb_tte[i] & 0x2? "RW": "RO", |
|
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env->dtlb_tte[i] & 0x40? "locked": "unlocked", |
|
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env->dtlb_tag[i] & 0x1fffULL); |
|
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} |
|
| 537 |
} |
|
| 538 |
} |
|
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if ((env->lsu & IMMU_E) == 0) {
|
|
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printf("IMMU disabled\n");
|
|
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} else {
|
|
| 542 |
printf("IMMU dump:\n");
|
|
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for (i = 0; i < 64; i++) {
|
|
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switch ((env->itlb_tte[i] >> 61) & 3) {
|
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| 545 |
default: |
|
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case 0x0: |
|
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mask = " 8k"; |
|
| 548 |
break; |
|
| 549 |
case 0x1: |
|
| 550 |
mask = " 64k"; |
|
| 551 |
break; |
|
| 552 |
case 0x2: |
|
| 553 |
mask = "512k"; |
|
| 554 |
break; |
|
| 555 |
case 0x3: |
|
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mask = " 4M"; |
|
| 557 |
break; |
|
| 558 |
} |
|
| 559 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
|
|
| 560 |
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %lld\n",
|
|
| 561 |
env->itlb_tag[i] & ~0x1fffULL, |
|
| 562 |
env->itlb_tte[i] & 0x1ffffffe000ULL, |
|
| 563 |
mask, |
|
| 564 |
env->itlb_tte[i] & 0x4? "priv": "user", |
|
| 565 |
env->itlb_tte[i] & 0x40? "locked": "unlocked", |
|
| 566 |
env->itlb_tag[i] & 0x1fffULL); |
|
| 567 |
} |
|
| 568 |
} |
|
| 569 |
} |
|
| 570 |
} |
|
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#endif |
|
| 474 | 572 |
#endif |
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