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1
/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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25
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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    "%g0",
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    "%g1",
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    "%g2",
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    "%g3",
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    "%g4",
31
    "%g5",
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    "%g6",
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    "%g7",
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    "%o0",
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    "%o1",
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    "%o2",
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    "%o3",
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    "%o4",
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    "%o5",
40
    "%o6",
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    "%o7",
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    "%l0",
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    "%l1",
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    "%l2",
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    "%l3",
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    "%l4",
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    "%l5",
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    "%l6",
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    "%l7",
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    "%i0",
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    "%i1",
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    "%i2",
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    "%i3",
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    "%i4",
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    "%i5",
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    "%i6",
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    "%i7",
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};
59

    
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static const int tcg_target_reg_alloc_order[] = {
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    TCG_REG_L0,
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    TCG_REG_L1,
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    TCG_REG_L2,
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    TCG_REG_L3,
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    TCG_REG_L4,
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    TCG_REG_L5,
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    TCG_REG_L6,
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    TCG_REG_L7,
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    TCG_REG_I0,
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    TCG_REG_I1,
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    TCG_REG_I2,
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    TCG_REG_I3,
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    TCG_REG_I4,
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};
75

    
76
static const int tcg_target_call_iarg_regs[6] = {
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    TCG_REG_O0,
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    TCG_REG_O1,
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    TCG_REG_O2,
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    TCG_REG_O3,
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    TCG_REG_O4,
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    TCG_REG_O5,
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};
84

    
85
static const int tcg_target_call_oarg_regs[2] = {
86
    TCG_REG_O0,
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    TCG_REG_O1,
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};
89

    
90
static inline int check_fit_tl(tcg_target_long val, unsigned int bits)
91
{
92
    return (val << ((sizeof(tcg_target_long) * 8 - bits))
93
            >> (sizeof(tcg_target_long) * 8 - bits)) == val;
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}
95

    
96
static inline int check_fit_i32(uint32_t val, unsigned int bits)
97
{
98
    return ((val << (32 - bits)) >> (32 - bits)) == val;
99
}
100

    
101
static void patch_reloc(uint8_t *code_ptr, int type,
102
                        tcg_target_long value, tcg_target_long addend)
103
{
104
    value += addend;
105
    switch (type) {
106
    case R_SPARC_32:
107
        if (value != (uint32_t)value)
108
            tcg_abort();
109
        *(uint32_t *)code_ptr = value;
110
        break;
111
    case R_SPARC_WDISP22:
112
        value -= (long)code_ptr;
113
        value >>= 2;
114
        if (!check_fit_tl(value, 22))
115
            tcg_abort();
116
        *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x3fffff) | value;
117
        break;
118
    default:
119
        tcg_abort();
120
    }
121
}
122

    
123
/* maximum number of register used for input function arguments */
124
static inline int tcg_target_get_call_iarg_regs_count(int flags)
125
{
126
    return 6;
127
}
128

    
129
/* parse target specific constraints */
130
static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
131
{
132
    const char *ct_str;
133

    
134
    ct_str = *pct_str;
135
    switch (ct_str[0]) {
136
    case 'r':
137
    case 'L': /* qemu_ld/st constraint */
138
        ct->ct |= TCG_CT_REG;
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        tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
140
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_I0);
141
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_I1);
142
        break;
143
    case 'I':
144
        ct->ct |= TCG_CT_CONST_S11;
145
        break;
146
    case 'J':
147
        ct->ct |= TCG_CT_CONST_S13;
148
        break;
149
    default:
150
        return -1;
151
    }
152
    ct_str++;
153
    *pct_str = ct_str;
154
    return 0;
155
}
156

    
157
/* test if a constant matches the constraint */
158
static inline int tcg_target_const_match(tcg_target_long val,
159
                                         const TCGArgConstraint *arg_ct)
160
{
161
    int ct;
162

    
163
    ct = arg_ct->ct;
164
    if (ct & TCG_CT_CONST)
165
        return 1;
166
    else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11))
167
        return 1;
168
    else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13))
169
        return 1;
170
    else
171
        return 0;
172
}
173

    
174
#define INSN_OP(x)  ((x) << 30)
175
#define INSN_OP2(x) ((x) << 22)
176
#define INSN_OP3(x) ((x) << 19)
177
#define INSN_OPF(x) ((x) << 5)
178
#define INSN_RD(x)  ((x) << 25)
179
#define INSN_RS1(x) ((x) << 14)
180
#define INSN_RS2(x) (x)
181
#define INSN_ASI(x) ((x) << 5)
182

    
183
#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
184
#define INSN_OFF22(x) (((x) >> 2) & 0x3fffff)
185

    
186
#define INSN_COND(x, a) (((x) << 25) | ((a) << 29))
187
#define COND_N     0x0
188
#define COND_E     0x1
189
#define COND_LE    0x2
190
#define COND_L     0x3
191
#define COND_LEU   0x4
192
#define COND_CS    0x5
193
#define COND_NEG   0x6
194
#define COND_VS    0x7
195
#define COND_A     0x8
196
#define COND_NE    0x9
197
#define COND_G     0xa
198
#define COND_GE    0xb
199
#define COND_GU    0xc
200
#define COND_CC    0xd
201
#define COND_POS   0xe
202
#define COND_VC    0xf
203
#define BA         (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
204

    
205
#define ARITH_ADD  (INSN_OP(2) | INSN_OP3(0x00))
206
#define ARITH_AND  (INSN_OP(2) | INSN_OP3(0x01))
207
#define ARITH_OR   (INSN_OP(2) | INSN_OP3(0x02))
208
#define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
209
#define ARITH_XOR  (INSN_OP(2) | INSN_OP3(0x03))
210
#define ARITH_SUB  (INSN_OP(2) | INSN_OP3(0x04))
211
#define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
212
#define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10))
213
#define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
214
#define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
215
#define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
216
#define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
217
#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
218
#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
219
#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
220

    
221
#define SHIFT_SLL  (INSN_OP(2) | INSN_OP3(0x25))
222
#define SHIFT_SRL  (INSN_OP(2) | INSN_OP3(0x26))
223
#define SHIFT_SRA  (INSN_OP(2) | INSN_OP3(0x27))
224

    
225
#define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
226
#define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
227
#define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
228

    
229
#define WRY        (INSN_OP(2) | INSN_OP3(0x30))
230
#define JMPL       (INSN_OP(2) | INSN_OP3(0x38))
231
#define SAVE       (INSN_OP(2) | INSN_OP3(0x3c))
232
#define RESTORE    (INSN_OP(2) | INSN_OP3(0x3d))
233
#define SETHI      (INSN_OP(0) | INSN_OP2(0x4))
234
#define CALL       INSN_OP(1)
235
#define LDUB       (INSN_OP(3) | INSN_OP3(0x01))
236
#define LDSB       (INSN_OP(3) | INSN_OP3(0x09))
237
#define LDUH       (INSN_OP(3) | INSN_OP3(0x02))
238
#define LDSH       (INSN_OP(3) | INSN_OP3(0x0a))
239
#define LDUW       (INSN_OP(3) | INSN_OP3(0x00))
240
#define LDSW       (INSN_OP(3) | INSN_OP3(0x08))
241
#define LDX        (INSN_OP(3) | INSN_OP3(0x0b))
242
#define STB        (INSN_OP(3) | INSN_OP3(0x05))
243
#define STH        (INSN_OP(3) | INSN_OP3(0x06))
244
#define STW        (INSN_OP(3) | INSN_OP3(0x04))
245
#define STX        (INSN_OP(3) | INSN_OP3(0x0e))
246
#define LDUBA      (INSN_OP(3) | INSN_OP3(0x11))
247
#define LDSBA      (INSN_OP(3) | INSN_OP3(0x19))
248
#define LDUHA      (INSN_OP(3) | INSN_OP3(0x12))
249
#define LDSHA      (INSN_OP(3) | INSN_OP3(0x1a))
250
#define LDUWA      (INSN_OP(3) | INSN_OP3(0x10))
251
#define LDSWA      (INSN_OP(3) | INSN_OP3(0x18))
252
#define LDXA       (INSN_OP(3) | INSN_OP3(0x1b))
253
#define STBA       (INSN_OP(3) | INSN_OP3(0x15))
254
#define STHA       (INSN_OP(3) | INSN_OP3(0x16))
255
#define STWA       (INSN_OP(3) | INSN_OP3(0x14))
256
#define STXA       (INSN_OP(3) | INSN_OP3(0x1e))
257

    
258
#ifndef ASI_PRIMARY_LITTLE
259
#define ASI_PRIMARY_LITTLE 0x88
260
#endif
261

    
262
static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2,
263
                                 int op)
264
{
265
    tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
266
              INSN_RS2(rs2));
267
}
268

    
269
static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1, int offset,
270
                                  int op)
271
{
272
    tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
273
              INSN_IMM13(offset));
274
}
275

    
276
static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
277
{
278
    tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
279
}
280

    
281
static inline void tcg_out_sethi(TCGContext *s, int ret, uint32_t arg)
282
{
283
    tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
284
}
285

    
286
static inline void tcg_out_movi_imm13(TCGContext *s, int ret, uint32_t arg)
287
{
288
    tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR);
289
}
290

    
291
static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg)
292
{
293
    if (check_fit_i32(arg, 13))
294
        tcg_out_movi_imm13(s, ret, arg);
295
    else {
296
        tcg_out_sethi(s, ret, arg);
297
        if (arg & 0x3ff)
298
            tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
299
    }
300
}
301

    
302
static inline void tcg_out_movi(TCGContext *s, TCGType type,
303
                                int ret, tcg_target_long arg)
304
{
305
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
306
    if (!check_fit_tl(arg, 32) && (arg & ~0xffffffffULL) != 0) {
307
        // XXX ret may be I5, need another temp
308
        tcg_out_movi_imm32(s, TCG_REG_I5, arg >> 32);
309
        tcg_out_arithi(s, TCG_REG_I5, TCG_REG_I5, 32, SHIFT_SLLX);
310
        tcg_out_movi_imm32(s, ret, arg);
311
        tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_OR);
312
    } else
313
#endif
314
        tcg_out_movi_imm32(s, ret, arg);
315
}
316

    
317
static inline void tcg_out_ld_raw(TCGContext *s, int ret,
318
                                  tcg_target_long arg)
319
{
320
    tcg_out_sethi(s, ret, arg);
321
    tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
322
              INSN_IMM13(arg & 0x3ff));
323
}
324

    
325
static inline void tcg_out_ld_ptr(TCGContext *s, int ret,
326
                                  tcg_target_long arg)
327
{
328
    if (!check_fit_tl(arg, 10))
329
        tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
330
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
331
    tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |
332
              INSN_IMM13(arg & 0x3ff));
333
#else
334
    tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
335
              INSN_IMM13(arg & 0x3ff));
336
#endif
337
}
338

    
339
static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op)
340
{
341
    if (check_fit_tl(offset, 13))
342
        tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
343
                  INSN_IMM13(offset));
344
    else {
345
        tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
346
        tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
347
                  INSN_RS2(addr));
348
    }
349
}
350

    
351
static inline void tcg_out_ldst_asi(TCGContext *s, int ret, int addr,
352
                                    int offset, int op, int asi)
353
{
354
    tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
355
    tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
356
              INSN_ASI(asi) | INSN_RS2(addr));
357
}
358

    
359
static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
360
                              int arg1, tcg_target_long arg2)
361
{
362
    if (type == TCG_TYPE_I32)
363
        tcg_out_ldst(s, ret, arg1, arg2, LDUW);
364
    else
365
        tcg_out_ldst(s, ret, arg1, arg2, LDX);
366
}
367

    
368
static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
369
                              int arg1, tcg_target_long arg2)
370
{
371
    if (type == TCG_TYPE_I32)
372
        tcg_out_ldst(s, arg, arg1, arg2, STW);
373
    else
374
        tcg_out_ldst(s, arg, arg1, arg2, STX);
375
}
376

    
377
static inline void tcg_out_sety(TCGContext *s, tcg_target_long val)
378
{
379
    if (val == 0 || val == -1)
380
        tcg_out32(s, WRY | INSN_IMM13(val));
381
    else
382
        fprintf(stderr, "unimplemented sety %ld\n", (long)val);
383
}
384

    
385
static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
386
{
387
    if (val != 0) {
388
        if (check_fit_tl(val, 13))
389
            tcg_out_arithi(s, reg, reg, val, ARITH_ADD);
390
        else {
391
            tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, val);
392
            tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_ADD);
393
        }
394
    }
395
}
396

    
397
static inline void tcg_out_nop(TCGContext *s)
398
{
399
    tcg_out_sethi(s, TCG_REG_G0, 0);
400
}
401

    
402
static void tcg_out_branch(TCGContext *s, int opc, int label_index)
403
{
404
    int32_t val;
405
    TCGLabel *l = &s->labels[label_index];
406

    
407
    if (l->has_value) {
408
        val = l->u.value - (tcg_target_long)s->code_ptr;
409
        tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2)
410
                      | INSN_OFF22(l->u.value - (unsigned long)s->code_ptr)));
411
    } else {
412
        tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP22, label_index, 0);
413
        tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0));
414
    }
415
}
416

    
417
static const uint8_t tcg_cond_to_bcond[10] = {
418
    [TCG_COND_EQ] = COND_E,
419
    [TCG_COND_NE] = COND_NE,
420
    [TCG_COND_LT] = COND_L,
421
    [TCG_COND_GE] = COND_GE,
422
    [TCG_COND_LE] = COND_LE,
423
    [TCG_COND_GT] = COND_G,
424
    [TCG_COND_LTU] = COND_CS,
425
    [TCG_COND_GEU] = COND_CC,
426
    [TCG_COND_LEU] = COND_LEU,
427
    [TCG_COND_GTU] = COND_GU,
428
};
429

    
430
static void tcg_out_brcond(TCGContext *s, int cond,
431
                           TCGArg arg1, TCGArg arg2, int const_arg2,
432
                           int label_index)
433
{
434
    if (const_arg2 && arg2 == 0)
435
        /* orcc %g0, r, %g0 */
436
        tcg_out_arith(s, TCG_REG_G0, TCG_REG_G0, arg1, ARITH_ORCC);
437
    else
438
        /* subcc r1, r2, %g0 */
439
        tcg_out_arith(s, TCG_REG_G0, arg1, arg2, ARITH_SUBCC);
440
    tcg_out_branch(s, tcg_cond_to_bcond[cond], label_index);
441
    tcg_out_nop(s);
442
}
443

    
444
/* Generate global QEMU prologue and epilogue code */
445
void tcg_target_qemu_prologue(TCGContext *s)
446
{
447
    tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
448
              INSN_IMM13(-TCG_TARGET_STACK_MINFRAME));
449
    tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I0) |
450
              INSN_RS2(TCG_REG_G0));
451
    tcg_out_nop(s);
452
}
453

    
454
#if defined(CONFIG_SOFTMMU)
455
extern void __ldb_mmu(void);
456
extern void __ldw_mmu(void);
457
extern void __ldl_mmu(void);
458
extern void __ldq_mmu(void);
459

    
460
extern void __stb_mmu(void);
461
extern void __stw_mmu(void);
462
extern void __stl_mmu(void);
463
extern void __stq_mmu(void);
464

    
465

    
466
static const void * const qemu_ld_helpers[4] = {
467
    __ldb_mmu,
468
    __ldw_mmu,
469
    __ldl_mmu,
470
    __ldq_mmu,
471
};
472

    
473
static const void * const qemu_st_helpers[4] = {
474
    __stb_mmu,
475
    __stw_mmu,
476
    __stl_mmu,
477
    __stq_mmu,
478
};
479
#endif
480

    
481
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
482
                            int opc)
483
{
484
    int addr_reg, data_reg, r0, r1, mem_index, s_bits, ld_op;
485
#if defined(CONFIG_SOFTMMU)
486
    uint8_t *label1_ptr, *label2_ptr;
487
#endif
488

    
489
    data_reg = *args++;
490
    addr_reg = *args++;
491
    mem_index = *args;
492
    s_bits = opc & 3;
493

    
494
    r0 = TCG_REG_I0;
495
    r1 = TCG_REG_I1;
496

    
497
#if TARGET_LONG_BITS == 32
498
    ld_op = LDUW;
499
#else
500
    ld_op = LDX;
501
#endif
502

    
503
#if defined(CONFIG_SOFTMMU)
504
    /* srl addr_reg, x, r1 */
505
    tcg_out_arithi(s, r1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
506
                   SHIFT_SRL);
507
    /* and addr_reg, x, r0 */
508
    tcg_out_arithi(s, r0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
509
                   ARITH_AND);
510

    
511
    /* and r1, x, r1 */
512
    tcg_out_arithi(s, r1, r1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS,
513
                   ARITH_AND);
514

    
515
    /* add r1, x, r1 */
516
    tcg_out_arithi(s, r1, r1, offsetof(CPUState, tlb_table[mem_index][0].addr_read),
517
                   ARITH_ADD);
518

    
519
    /* ld [env + r1], r1 */
520
    tcg_out_ldst(s, r1, TCG_AREG0, r1, ld_op);
521

    
522
    /* subcc r0, r1, %g0 */
523
    tcg_out_arith(s, TCG_REG_G0, r0, r1, ARITH_SUBCC);
524

    
525
    /* will become:
526
       be label1 */
527
    label1_ptr = s->code_ptr;
528
    tcg_out32(s, 0);
529

    
530
    /* mov (delay slot)*/
531
    tcg_out_mov(s, r0, addr_reg);
532

    
533
    /* XXX: move that code at the end of the TB */
534
    tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits]
535
                           - (tcg_target_ulong)s->code_ptr) >> 2)
536
                         & 0x3fffffff));
537
    /* mov (delay slot)*/
538
    tcg_out_movi(s, TCG_TYPE_I32, r1, mem_index);
539

    
540
    switch(opc) {
541
    case 0 | 4:
542
        /* sll i0, 24/56, i0 */
543
        tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0,
544
                       sizeof(tcg_target_long) * 8 - 8, SHIFT_SLL);
545
        /* sra i0, 24/56, data_reg */
546
        tcg_out_arithi(s, data_reg, TCG_REG_I0,
547
                       sizeof(tcg_target_long) * 8 - 8, SHIFT_SRA);
548
        break;
549
    case 1 | 4:
550
        /* sll i0, 16/48, i0 */
551
        tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0,
552
                       sizeof(tcg_target_long) * 8 - 16, SHIFT_SLL);
553
        /* sra i0, 16/48, data_reg */
554
        tcg_out_arithi(s, data_reg, TCG_REG_I0,
555
                       sizeof(tcg_target_long) * 8 - 16, SHIFT_SRA);
556
        break;
557
    case 2 | 4:
558
        /* sll i0, 32, i0 */
559
        tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0, 32, SHIFT_SLL);
560
        /* sra i0, 32, data_reg */
561
        tcg_out_arithi(s, data_reg, TCG_REG_I0, 32, SHIFT_SRA);
562
        break;
563
    case 0:
564
    case 1:
565
    case 2:
566
    case 3:
567
    default:
568
        /* mov */
569
        tcg_out_mov(s, data_reg, TCG_REG_I0);
570
        break;
571
    }
572

    
573
    /* will become:
574
       ba label2 */
575
    label2_ptr = s->code_ptr;
576
    tcg_out32(s, 0);
577

    
578
    /* label1: */
579
    *label1_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
580
                   INSN_OFF22((unsigned long)label1_ptr -
581
                              (unsigned long)s->code_ptr));
582

    
583
    /* ld [r1 + x], r1 */
584
    tcg_out_ldst(s, r1, r1, offsetof(CPUTLBEntry, addend) -
585
                 offsetof(CPUTLBEntry, addr_read), ld_op);
586
    /* add x(r1), r0 */
587
    tcg_out_arith(s, r0, r1, r0, ARITH_ADD);
588
#else
589
    r0 = addr_reg;
590
#endif
591

    
592
    switch(opc) {
593
    case 0:
594
        /* ldub [r0], data_reg */
595
        tcg_out_ldst(s, data_reg, r0, 0, LDUB);
596
        break;
597
    case 0 | 4:
598
        /* ldsb [r0], data_reg */
599
        tcg_out_ldst(s, data_reg, r0, 0, LDSB);
600
        break;
601
    case 1:
602
#ifdef TARGET_WORDS_BIGENDIAN
603
        /* lduh [r0], data_reg */
604
        tcg_out_ldst(s, data_reg, r0, 0, LDUH);
605
#else
606
        /* lduha [r0] ASI_PRIMARY_LITTLE, data_reg */
607
        tcg_out_ldst_asi(s, data_reg, r0, 0, LDUHA, ASI_PRIMARY_LITTLE);
608
#endif
609
        break;
610
    case 1 | 4:
611
#ifdef TARGET_WORDS_BIGENDIAN
612
        /* ldsh [r0], data_reg */
613
        tcg_out_ldst(s, data_reg, r0, 0, LDSH);
614
#else
615
        /* ldsha [r0] ASI_PRIMARY_LITTLE, data_reg */
616
        tcg_out_ldst_asi(s, data_reg, r0, 0, LDSHA, ASI_PRIMARY_LITTLE);
617
#endif
618
        break;
619
    case 2:
620
#ifdef TARGET_WORDS_BIGENDIAN
621
        /* lduw [r0], data_reg */
622
        tcg_out_ldst(s, data_reg, r0, 0, LDUW);
623
#else
624
        /* lduwa [r0] ASI_PRIMARY_LITTLE, data_reg */
625
        tcg_out_ldst_asi(s, data_reg, r0, 0, LDUWA, ASI_PRIMARY_LITTLE);
626
#endif
627
        break;
628
    case 2 | 4:
629
#ifdef TARGET_WORDS_BIGENDIAN
630
        /* ldsw [r0], data_reg */
631
        tcg_out_ldst(s, data_reg, r0, 0, LDSW);
632
#else
633
        /* ldswa [r0] ASI_PRIMARY_LITTLE, data_reg */
634
        tcg_out_ldst_asi(s, data_reg, r0, 0, LDSWA, ASI_PRIMARY_LITTLE);
635
#endif
636
        break;
637
    case 3:
638
#ifdef TARGET_WORDS_BIGENDIAN
639
        /* ldx [r0], data_reg */
640
        tcg_out_ldst(s, data_reg, r0, 0, LDX);
641
#else
642
        /* ldxa [r0] ASI_PRIMARY_LITTLE, data_reg */
643
        tcg_out_ldst_asi(s, data_reg, r0, 0, LDXA, ASI_PRIMARY_LITTLE);
644
#endif
645
        break;
646
    default:
647
        tcg_abort();
648
    }
649

    
650
#if defined(CONFIG_SOFTMMU)
651
    /* label2: */
652
    *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
653
                   INSN_OFF22((unsigned long)label2_ptr -
654
                              (unsigned long)s->code_ptr));
655
#endif
656
}
657

    
658
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
659
                            int opc)
660
{
661
    int addr_reg, data_reg, r0, r1, mem_index, s_bits, ld_op;
662
#if defined(CONFIG_SOFTMMU)
663
    uint8_t *label1_ptr, *label2_ptr;
664
#endif
665

    
666
    data_reg = *args++;
667
    addr_reg = *args++;
668
    mem_index = *args;
669

    
670
    s_bits = opc;
671

    
672
    r0 = TCG_REG_I5;
673
    r1 = TCG_REG_I4;
674

    
675
#if TARGET_LONG_BITS == 32
676
    ld_op = LDUW;
677
#else
678
    ld_op = LDX;
679
#endif
680

    
681
#if defined(CONFIG_SOFTMMU)
682
    /* srl addr_reg, x, r1 */
683
    tcg_out_arithi(s, r1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
684
                   SHIFT_SRL);
685
    /* and addr_reg, x, r0 */
686
    tcg_out_arithi(s, r0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
687
                   ARITH_AND);
688

    
689
    /* and r1, x, r1 */
690
    tcg_out_arithi(s, r1, r1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS,
691
                   ARITH_AND);
692

    
693
    /* add r1, x, r1 */
694
    tcg_out_arithi(s, r1, r1,
695
                   offsetof(CPUState, tlb_table[mem_index][0].addr_write),
696
                   ARITH_ADD);
697

    
698
    /* ld [env + r1], r1 */
699
    tcg_out_ldst(s, r1, TCG_AREG0, r1, ld_op);
700

    
701
    /* subcc r0, r1, %g0 */
702
    tcg_out_arith(s, TCG_REG_G0, r0, r1, ARITH_SUBCC);
703

    
704
    /* will become:
705
       be label1 */
706
    label1_ptr = s->code_ptr;
707
    tcg_out32(s, 0);
708
    /* mov (delay slot)*/
709
    tcg_out_mov(s, r0, addr_reg);
710

    
711
    switch(opc) {
712
    case 0 | 4:
713
        /* sll i0, 24/56, i0 */
714
        tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0,
715
                       sizeof(tcg_target_long) * 8 - 8, SHIFT_SLL);
716
        /* sra i0, 24/56, data_reg */
717
        tcg_out_arithi(s, data_reg, TCG_REG_I0,
718
                       sizeof(tcg_target_long) * 8 - 8, SHIFT_SRA);
719
        break;
720
    case 1 | 4:
721
        /* sll i0, 16/48, i0 */
722
        tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0,
723
                       sizeof(tcg_target_long) * 8 - 16, SHIFT_SLL);
724
        /* sra i0, 16/48, data_reg */
725
        tcg_out_arithi(s, data_reg, TCG_REG_I0,
726
                       sizeof(tcg_target_long) * 8 - 16, SHIFT_SRA);
727
        break;
728
    case 2 | 4:
729
        /* sll i0, 32, i0 */
730
        tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0, 32, SHIFT_SLL);
731
        /* sra i0, 32, data_reg */
732
        tcg_out_arithi(s, data_reg, TCG_REG_I0, 32, SHIFT_SRA);
733
        break;
734
    case 0:
735
    case 1:
736
    case 2:
737
    case 3:
738
    default:
739
        /* mov */
740
        tcg_out_mov(s, data_reg, TCG_REG_I0);
741
        break;
742
    }
743

    
744
    tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits]
745
                           - (tcg_target_ulong)s->code_ptr) >> 2)
746
                         & 0x3fffffff));
747
    /* mov (delay slot)*/
748
    tcg_out_movi(s, TCG_TYPE_I32, r1, mem_index);
749

    
750
    /* will become:
751
       ba label2 */
752
    label2_ptr = s->code_ptr;
753
    tcg_out32(s, 0);
754

    
755
    /* label1: */
756
    *label1_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
757
                   INSN_OFF22((unsigned long)label1_ptr -
758
                              (unsigned long)s->code_ptr));
759

    
760
    /* ld [r1 + x], r1 */
761
    tcg_out_ldst(s, r1, r1, offsetof(CPUTLBEntry, addend) -
762
                 offsetof(CPUTLBEntry, addr_write), ld_op);
763
    /* add x(r1), r0 */
764
    tcg_out_arith(s, r0, r1, r0, ARITH_ADD);
765
#else
766
    r0 = addr_reg;
767
#endif
768

    
769
    switch(opc) {
770
    case 0:
771
        /* stb data_reg, [r0] */
772
        tcg_out_ldst(s, data_reg, r0, 0, STB);
773
        break;
774
    case 1:
775
#ifdef TARGET_WORDS_BIGENDIAN
776
        /* sth data_reg, [r0] */
777
        tcg_out_ldst(s, data_reg, r0, 0, STH);
778
#else
779
        /* stha data_reg, [r0] ASI_PRIMARY_LITTLE */
780
        tcg_out_ldst_asi(s, data_reg, r0, 0, STHA, ASI_PRIMARY_LITTLE);
781
#endif
782
        break;
783
    case 2:
784
#ifdef TARGET_WORDS_BIGENDIAN
785
        /* stw data_reg, [r0] */
786
        tcg_out_ldst(s, data_reg, r0, 0, STW);
787
#else
788
        /* stwa data_reg, [r0] ASI_PRIMARY_LITTLE */
789
        tcg_out_ldst_asi(s, data_reg, r0, 0, STWA, ASI_PRIMARY_LITTLE);
790
#endif
791
        break;
792
    case 3:
793
#ifdef TARGET_WORDS_BIGENDIAN
794
        /* stx data_reg, [r0] */
795
        tcg_out_ldst(s, data_reg, r0, 0, STX);
796
#else
797
        /* stxa data_reg, [r0] ASI_PRIMARY_LITTLE */
798
        tcg_out_ldst_asi(s, data_reg, r0, 0, STXA, ASI_PRIMARY_LITTLE);
799
#endif
800
        break;
801
    default:
802
        tcg_abort();
803
    }
804

    
805
#if defined(CONFIG_SOFTMMU)
806
    /* label2: */
807
    *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
808
                   INSN_OFF22((unsigned long)label2_ptr -
809
                              (unsigned long)s->code_ptr));
810
#endif
811
}
812

    
813
static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
814
                              const int *const_args)
815
{
816
    int c;
817

    
818
    switch (opc) {
819
    case INDEX_op_exit_tb:
820
        tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
821
        tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) |
822
                  INSN_IMM13(8));
823
        tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) |
824
                      INSN_RS2(TCG_REG_G0));
825
        break;
826
    case INDEX_op_goto_tb:
827
        if (s->tb_jmp_offset) {
828
            /* direct jump method */
829
            tcg_out_sethi(s, TCG_REG_I5, args[0] & 0xffffe000);
830
            tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
831
                      INSN_IMM13((args[0] & 0x1fff)));
832
            s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
833
        } else {
834
            /* indirect jump method */
835
            tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
836
            tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
837
                      INSN_RS2(TCG_REG_G0));
838
        }
839
        tcg_out_nop(s);
840
        s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
841
        break;
842
    case INDEX_op_call:
843
        if (const_args[0]) {
844
            tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
845
                                  - (tcg_target_ulong)s->code_ptr) >> 2)
846
                                 & 0x3fffffff));
847
            tcg_out_nop(s);
848
        } else {
849
            tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
850
            tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) |
851
                      INSN_RS2(TCG_REG_G0));
852
            tcg_out_nop(s);
853
        }
854
        break;
855
    case INDEX_op_jmp:
856
    case INDEX_op_br:
857
        tcg_out_branch(s, COND_A, args[0]);
858
        tcg_out_nop(s);
859
        break;
860
    case INDEX_op_movi_i32:
861
        tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
862
        break;
863

    
864
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
865
#define OP_32_64(x)                             \
866
        glue(glue(case INDEX_op_, x), _i32:)    \
867
        glue(glue(case INDEX_op_, x), _i64:)
868
#else
869
#define OP_32_64(x)                             \
870
        glue(glue(case INDEX_op_, x), _i32:)
871
#endif
872
        OP_32_64(ld8u);
873
        tcg_out_ldst(s, args[0], args[1], args[2], LDUB);
874
        break;
875
        OP_32_64(ld8s);
876
        tcg_out_ldst(s, args[0], args[1], args[2], LDSB);
877
        break;
878
        OP_32_64(ld16u);
879
        tcg_out_ldst(s, args[0], args[1], args[2], LDUH);
880
        break;
881
        OP_32_64(ld16s);
882
        tcg_out_ldst(s, args[0], args[1], args[2], LDSH);
883
        break;
884
    case INDEX_op_ld_i32:
885
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
886
    case INDEX_op_ld32u_i64:
887
#endif
888
        tcg_out_ldst(s, args[0], args[1], args[2], LDUW);
889
        break;
890
        OP_32_64(st8);
891
        tcg_out_ldst(s, args[0], args[1], args[2], STB);
892
        break;
893
        OP_32_64(st16);
894
        tcg_out_ldst(s, args[0], args[1], args[2], STH);
895
        break;
896
    case INDEX_op_st_i32:
897
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
898
    case INDEX_op_st32_i64:
899
#endif
900
        tcg_out_ldst(s, args[0], args[1], args[2], STW);
901
        break;
902
        OP_32_64(add);
903
        c = ARITH_ADD;
904
        goto gen_arith32;
905
        OP_32_64(sub);
906
        c = ARITH_SUB;
907
        goto gen_arith32;
908
        OP_32_64(and);
909
        c = ARITH_AND;
910
        goto gen_arith32;
911
        OP_32_64(or);
912
        c = ARITH_OR;
913
        goto gen_arith32;
914
        OP_32_64(xor);
915
        c = ARITH_XOR;
916
        goto gen_arith32;
917
    case INDEX_op_shl_i32:
918
        c = SHIFT_SLL;
919
        goto gen_arith32;
920
    case INDEX_op_shr_i32:
921
        c = SHIFT_SRL;
922
        goto gen_arith32;
923
    case INDEX_op_sar_i32:
924
        c = SHIFT_SRA;
925
        goto gen_arith32;
926
    case INDEX_op_mul_i32:
927
        c = ARITH_UMUL;
928
        goto gen_arith32;
929
    case INDEX_op_div2_i32:
930
#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
931
        c = ARITH_SDIVX;
932
        goto gen_arith32;
933
#else
934
        tcg_out_sety(s, 0);
935
        c = ARITH_SDIV;
936
        goto gen_arith32;
937
#endif
938
    case INDEX_op_divu2_i32:
939
#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
940
        c = ARITH_UDIVX;
941
        goto gen_arith32;
942
#else
943
        tcg_out_sety(s, 0);
944
        c = ARITH_UDIV;
945
        goto gen_arith32;
946
#endif
947

    
948
    case INDEX_op_brcond_i32:
949
        tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
950
                       args[3]);
951
        break;
952

    
953
    case INDEX_op_qemu_ld8u:
954
        tcg_out_qemu_ld(s, args, 0);
955
        break;
956
    case INDEX_op_qemu_ld8s:
957
        tcg_out_qemu_ld(s, args, 0 | 4);
958
        break;
959
    case INDEX_op_qemu_ld16u:
960
        tcg_out_qemu_ld(s, args, 1);
961
        break;
962
    case INDEX_op_qemu_ld16s:
963
        tcg_out_qemu_ld(s, args, 1 | 4);
964
        break;
965
    case INDEX_op_qemu_ld32u:
966
        tcg_out_qemu_ld(s, args, 2);
967
        break;
968
    case INDEX_op_qemu_ld32s:
969
        tcg_out_qemu_ld(s, args, 2 | 4);
970
        break;
971
    case INDEX_op_qemu_st8:
972
        tcg_out_qemu_st(s, args, 0);
973
        break;
974
    case INDEX_op_qemu_st16:
975
        tcg_out_qemu_st(s, args, 1);
976
        break;
977
    case INDEX_op_qemu_st32:
978
        tcg_out_qemu_st(s, args, 2);
979
        break;
980

    
981
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
982
    case INDEX_op_movi_i64:
983
        tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
984
        break;
985
    case INDEX_op_ld32s_i64:
986
        tcg_out_ldst(s, args[0], args[1], args[2], LDSW);
987
        break;
988
    case INDEX_op_ld_i64:
989
        tcg_out_ldst(s, args[0], args[1], args[2], LDX);
990
        break;
991
    case INDEX_op_st_i64:
992
        tcg_out_ldst(s, args[0], args[1], args[2], STX);
993
        break;
994
    case INDEX_op_shl_i64:
995
        c = SHIFT_SLLX;
996
        goto gen_arith32;
997
    case INDEX_op_shr_i64:
998
        c = SHIFT_SRLX;
999
        goto gen_arith32;
1000
    case INDEX_op_sar_i64:
1001
        c = SHIFT_SRAX;
1002
        goto gen_arith32;
1003
    case INDEX_op_mul_i64:
1004
        c = ARITH_MULX;
1005
        goto gen_arith32;
1006
    case INDEX_op_div2_i64:
1007
        c = ARITH_SDIVX;
1008
        goto gen_arith32;
1009
    case INDEX_op_divu2_i64:
1010
        c = ARITH_UDIVX;
1011
        goto gen_arith32;
1012

    
1013
    case INDEX_op_brcond_i64:
1014
        tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1015
                       args[3]);
1016
        break;
1017
    case INDEX_op_qemu_ld64:
1018
        tcg_out_qemu_ld(s, args, 3);
1019
        break;
1020
    case INDEX_op_qemu_st64:
1021
        tcg_out_qemu_st(s, args, 3);
1022
        break;
1023

    
1024
#endif
1025
    gen_arith32:
1026
        if (const_args[2]) {
1027
            tcg_out_arithi(s, args[0], args[1], args[2], c);
1028
        } else {
1029
            tcg_out_arith(s, args[0], args[1], args[2], c);
1030
        }
1031
        break;
1032

    
1033
    default:
1034
        fprintf(stderr, "unknown opcode 0x%x\n", opc);
1035
        tcg_abort();
1036
    }
1037
}
1038

    
1039
static const TCGTargetOpDef sparc_op_defs[] = {
1040
    { INDEX_op_exit_tb, { } },
1041
    { INDEX_op_goto_tb, { } },
1042
    { INDEX_op_call, { "ri" } },
1043
    { INDEX_op_jmp, { "ri" } },
1044
    { INDEX_op_br, { } },
1045

    
1046
    { INDEX_op_mov_i32, { "r", "r" } },
1047
    { INDEX_op_movi_i32, { "r" } },
1048
    { INDEX_op_ld8u_i32, { "r", "r" } },
1049
    { INDEX_op_ld8s_i32, { "r", "r" } },
1050
    { INDEX_op_ld16u_i32, { "r", "r" } },
1051
    { INDEX_op_ld16s_i32, { "r", "r" } },
1052
    { INDEX_op_ld_i32, { "r", "r" } },
1053
    { INDEX_op_st8_i32, { "r", "r" } },
1054
    { INDEX_op_st16_i32, { "r", "r" } },
1055
    { INDEX_op_st_i32, { "r", "r" } },
1056

    
1057
    { INDEX_op_add_i32, { "r", "r", "rJ" } },
1058
    { INDEX_op_mul_i32, { "r", "r", "rJ" } },
1059
    { INDEX_op_div2_i32, { "r", "r", "0", "1", "r" } },
1060
    { INDEX_op_divu2_i32, { "r", "r", "0", "1", "r" } },
1061
    { INDEX_op_sub_i32, { "r", "r", "rJ" } },
1062
    { INDEX_op_and_i32, { "r", "r", "rJ" } },
1063
    { INDEX_op_or_i32, { "r", "r", "rJ" } },
1064
    { INDEX_op_xor_i32, { "r", "r", "rJ" } },
1065

    
1066
    { INDEX_op_shl_i32, { "r", "r", "rJ" } },
1067
    { INDEX_op_shr_i32, { "r", "r", "rJ" } },
1068
    { INDEX_op_sar_i32, { "r", "r", "rJ" } },
1069

    
1070
    { INDEX_op_brcond_i32, { "r", "ri" } },
1071

    
1072
    { INDEX_op_qemu_ld8u, { "r", "L" } },
1073
    { INDEX_op_qemu_ld8s, { "r", "L" } },
1074
    { INDEX_op_qemu_ld16u, { "r", "L" } },
1075
    { INDEX_op_qemu_ld16s, { "r", "L" } },
1076
    { INDEX_op_qemu_ld32u, { "r", "L" } },
1077
    { INDEX_op_qemu_ld32s, { "r", "L" } },
1078

    
1079
    { INDEX_op_qemu_st8, { "L", "L" } },
1080
    { INDEX_op_qemu_st16, { "L", "L" } },
1081
    { INDEX_op_qemu_st32, { "L", "L" } },
1082

    
1083
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1084
    { INDEX_op_mov_i64, { "r", "r" } },
1085
    { INDEX_op_movi_i64, { "r" } },
1086
    { INDEX_op_ld8u_i64, { "r", "r" } },
1087
    { INDEX_op_ld8s_i64, { "r", "r" } },
1088
    { INDEX_op_ld16u_i64, { "r", "r" } },
1089
    { INDEX_op_ld16s_i64, { "r", "r" } },
1090
    { INDEX_op_ld32u_i64, { "r", "r" } },
1091
    { INDEX_op_ld32s_i64, { "r", "r" } },
1092
    { INDEX_op_ld_i64, { "r", "r" } },
1093
    { INDEX_op_st8_i64, { "r", "r" } },
1094
    { INDEX_op_st16_i64, { "r", "r" } },
1095
    { INDEX_op_st32_i64, { "r", "r" } },
1096
    { INDEX_op_st_i64, { "r", "r" } },
1097

    
1098
    { INDEX_op_add_i64, { "r", "r", "rJ" } },
1099
    { INDEX_op_mul_i64, { "r", "r", "rJ" } },
1100
    { INDEX_op_div2_i64, { "r", "r", "0", "1", "r" } },
1101
    { INDEX_op_divu2_i64, { "r", "r", "0", "1", "r" } },
1102
    { INDEX_op_sub_i64, { "r", "r", "rJ" } },
1103
    { INDEX_op_and_i64, { "r", "r", "rJ" } },
1104
    { INDEX_op_or_i64, { "r", "r", "rJ" } },
1105
    { INDEX_op_xor_i64, { "r", "r", "rJ" } },
1106

    
1107
    { INDEX_op_shl_i64, { "r", "r", "rJ" } },
1108
    { INDEX_op_shr_i64, { "r", "r", "rJ" } },
1109
    { INDEX_op_sar_i64, { "r", "r", "rJ" } },
1110

    
1111
    { INDEX_op_brcond_i64, { "r", "ri" } },
1112
#endif
1113
    { -1 },
1114
};
1115

    
1116
void tcg_target_init(TCGContext *s)
1117
{
1118
    tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1119
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1120
    tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1121
#endif
1122
    tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1123
                     (1 << TCG_REG_G1) |
1124
                     (1 << TCG_REG_G2) |
1125
                     (1 << TCG_REG_G3) |
1126
                     (1 << TCG_REG_G4) |
1127
                     (1 << TCG_REG_G5) |
1128
                     (1 << TCG_REG_G6) |
1129
                     (1 << TCG_REG_G7) |
1130
                     (1 << TCG_REG_O0) |
1131
                     (1 << TCG_REG_O1) |
1132
                     (1 << TCG_REG_O2) |
1133
                     (1 << TCG_REG_O3) |
1134
                     (1 << TCG_REG_O4) |
1135
                     (1 << TCG_REG_O5) |
1136
                     (1 << TCG_REG_O7));
1137

    
1138
    tcg_regset_clear(s->reserved_regs);
1139
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0);
1140
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
1141
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6);
1142
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7);
1143
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6);
1144
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7);
1145
    tcg_add_target_add_op_defs(sparc_op_defs);
1146
}