Revision 8387da81

b/target-arm/translate.c
3257 3257
        break;
3258 3258
    case 0xc:
3259 3259
    case 0xd:
3260
        if (dp && (insn & 0x03e00000) == 0x00400000) {
3260
        if ((insn & 0x03e00000) == 0x00400000) {
3261 3261
            /* two-register transfer */
3262 3262
            rn = (insn >> 16) & 0xf;
3263 3263
            rd = (insn >> 12) & 0xf;
......
3279 3279
                } else {
3280 3280
                    gen_mov_F0_vreg(0, rm);
3281 3281
                    tmp = gen_vfp_mrs();
3282
                    store_reg(s, rn, tmp);
3282
                    store_reg(s, rd, tmp);
3283 3283
                    gen_mov_F0_vreg(0, rm + 1);
3284 3284
                    tmp = gen_vfp_mrs();
3285
                    store_reg(s, rd, tmp);
3285
                    store_reg(s, rn, tmp);
3286 3286
                }
3287 3287
            } else {
3288 3288
                /* arm->vfp */
......
3294 3294
                    gen_vfp_msr(tmp);
3295 3295
                    gen_mov_vreg_F0(0, rm * 2 + 1);
3296 3296
                } else {
3297
                    tmp = load_reg(s, rn);
3297
                    tmp = load_reg(s, rd);
3298 3298
                    gen_vfp_msr(tmp);
3299 3299
                    gen_mov_vreg_F0(0, rm);
3300
                    tmp = load_reg(s, rd);
3300
                    tmp = load_reg(s, rn);
3301 3301
                    gen_vfp_msr(tmp);
3302 3302
                    gen_mov_vreg_F0(0, rm + 1);
3303 3303
                }

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