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/*
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 * QEMU ETRAX System Emulator
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 *
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 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include <stdio.h>
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#include <sys/time.h>
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#include "vl.h"
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void etrax_ack_irq(CPUState *env, uint32_t mask);
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#define R_TIME 0xb001e038
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#define RW_TMR0_DIV 0xb001e000
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#define R_TMR0_DATA 0xb001e004
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#define RW_TMR0_CTRL 0xb001e008
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#define RW_TMR1_DIV 0xb001e010
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#define R_TMR1_DATA 0xb001e014
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#define RW_TMR1_CTRL 0xb001e018
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#define RW_INTR_MASK 0xb001e048
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#define RW_ACK_INTR 0xb001e04c
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#define R_INTR 0xb001e050
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#define R_MASKED_INTR 0xb001e054
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uint32_t rw_intr_mask;
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uint32_t rw_ack_intr;
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uint32_t r_intr;
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struct fs_timer_t {
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        QEMUBH *bh;
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        unsigned int limit;
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        int scale;
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        ptimer_state *ptimer;
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        CPUState *env;
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        qemu_irq *irq;
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        uint32_t mask;
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};
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static struct fs_timer_t timer0;
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/* diff two timevals.  Return a single int in us. */
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int diff_timeval_us(struct timeval *a, struct timeval *b)
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{
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        int diff;
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        /* assume these values are signed.  */
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        diff = (a->tv_sec - b->tv_sec) * 1000 * 1000;
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        diff += (a->tv_usec - b->tv_usec);
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        return diff;
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}
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static uint32_t timer_readb (void *opaque, target_phys_addr_t addr)
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{
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        CPUState *env = opaque;
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        uint32_t r = 0;
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        printf ("%s %x pc=%x\n", __func__, addr, env->pc);
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        return r;
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}
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static uint32_t timer_readw (void *opaque, target_phys_addr_t addr)
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{
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        CPUState *env = opaque;
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        uint32_t r = 0;
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        printf ("%s %x pc=%x\n", __func__, addr, env->pc);
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        return r;
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}
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static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
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{
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        CPUState *env = opaque;
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        uint32_t r = 0;
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        switch (addr) {
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        case R_TMR0_DATA:
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                break;
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        case R_TMR1_DATA:
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                printf ("R_TMR1_DATA\n");
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                break;
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        case R_TIME:
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        {
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                static struct timeval last;
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                struct timeval now;
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                gettimeofday(&now, NULL);
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                if (!(last.tv_sec == 0 && last.tv_usec == 0)) {
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                        r = diff_timeval_us(&now, &last);
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                        r *= 1000; /* convert to ns.  */
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                        r++; /* make sure we increase for each call.  */
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                }
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                last = now;
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                break;
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        }
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        case RW_INTR_MASK:
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                r = rw_intr_mask;
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                break;
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        case R_MASKED_INTR:
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                r = r_intr & rw_intr_mask;
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                break;
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        default:
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                printf ("%s %x p=%x\n", __func__, addr, env->pc);
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                break;
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        }
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        return r;
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}
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static void
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timer_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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        CPUState *env = opaque;
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        printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc);
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}
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static void
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timer_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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        CPUState *env = opaque;
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        printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc);
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}
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static void write_ctrl(struct fs_timer_t *t, uint32_t v)
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{
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        int op;
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        int freq;
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        int freq_hz;
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        op = v & 3;
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        freq = v >> 2;
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        freq_hz = 32000000;
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        switch (freq)
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        {
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        case 0:
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        case 1:
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                printf ("extern or disabled timer clock?\n");
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                break;
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        case 4: freq_hz =  29493000; break;
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        case 5: freq_hz =  32000000; break;
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        case 6: freq_hz =  32768000; break;
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        case 7: freq_hz = 100000000; break;
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        default:
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                abort();
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                break;
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        }
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        printf ("freq_hz=%d limit=%d\n", freq_hz, t->limit);
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        t->scale = 0;
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        if (t->limit > 2048)
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        {
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                t->scale = 2048;
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                ptimer_set_period(timer0.ptimer, freq_hz / t->scale);
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        }
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        printf ("op=%d\n", op);
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        switch (op)
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        {
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                case 0:
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                        printf ("limit=%d %d\n", t->limit, t->limit/t->scale);
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                        ptimer_set_limit(t->ptimer, t->limit / t->scale, 1);
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                        break;
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                case 1:
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                        ptimer_stop(t->ptimer);
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                        break;
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                case 2:
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                        ptimer_run(t->ptimer, 0);
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                        break;
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                default:
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                        abort();
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                        break;
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        }
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}
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static void timer_ack_irq(void)
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{
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        if (!(r_intr & timer0.mask & rw_intr_mask)) {
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                qemu_irq_lower(timer0.irq[0]);
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                etrax_ack_irq(timer0.env, 1 << 0x1b);
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        }
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}
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static void
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timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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        CPUState *env = opaque;
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        printf ("%s %x %x pc=%x\n",
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                __func__, addr, value, env->pc);
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        switch (addr)
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        {
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                case RW_TMR0_DIV:
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                        printf ("RW_TMR0_DIV=%x\n", value);
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                        timer0.limit = value;
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                        break;
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                case RW_TMR0_CTRL:
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                        printf ("RW_TMR0_CTRL=%x\n", value);
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                        write_ctrl(&timer0, value);
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                        break;
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                case RW_TMR1_DIV:
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                        printf ("RW_TMR1_DIV=%x\n", value);
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                        break;
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                case RW_TMR1_CTRL:
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                        printf ("RW_TMR1_CTRL=%x\n", value);
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                        break;
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                case RW_INTR_MASK:
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                        printf ("RW_INTR_MASK=%x\n", value);
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                        rw_intr_mask = value;
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                        break;
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                case RW_ACK_INTR:
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                        r_intr &= ~value;
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                        timer_ack_irq();
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                        break;
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                default:
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                        printf ("%s %x %x pc=%x\n",
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                                __func__, addr, value, env->pc);
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                        break;
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        }
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}
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static CPUReadMemoryFunc *timer_read[] = {
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    &timer_readb,
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    &timer_readw,
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    &timer_readl,
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};
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static CPUWriteMemoryFunc *timer_write[] = {
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    &timer_writeb,
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    &timer_writew,
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    &timer_writel,
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};
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static void timer_irq(void *opaque)
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{
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        struct fs_timer_t *t = opaque;
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        r_intr |= t->mask;
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        if (t->mask & rw_intr_mask) {
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                qemu_irq_raise(t->irq[0]);
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        }
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}
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void etraxfs_timer_init(CPUState *env, qemu_irq *irqs)
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{
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        int timer_regs;
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        timer0.bh = qemu_bh_new(timer_irq, &timer0);
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        timer0.ptimer = ptimer_init(timer0.bh);
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        timer0.irq = irqs + 0x1b;
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        timer0.mask = 1;
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        timer0.env = env;
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        timer_regs = cpu_register_io_memory(0, timer_read, timer_write, env);
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        cpu_register_physical_memory (0xb001e000, 0x5c, timer_regs);
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}