Revision 84108e12
| b/Makefile.objs | ||
|---|---|---|
| 131 | 131 |
hw-obj-y += virtio.o virtio-console.o |
| 132 | 132 |
hw-obj-y += fw_cfg.o |
| 133 | 133 |
hw-obj-y += watchdog.o |
| 134 |
hw-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o |
|
| 134 | 135 |
hw-obj-$(CONFIG_ECC) += ecc.o |
| 135 | 136 |
hw-obj-$(CONFIG_NAND) += nand.o |
| 136 | 137 |
|
| b/Makefile.target | ||
|---|---|---|
| 168 | 168 |
obj-y += virtio-blk.o virtio-balloon.o virtio-net.o virtio-pci.o virtio-serial-bus.o |
| 169 | 169 |
obj-y += rwhandler.o |
| 170 | 170 |
obj-$(CONFIG_KVM) += kvm.o kvm-all.o |
| 171 |
obj-$(CONFIG_ISA_MMIO) += isa_mmio.o |
|
| 172 | 171 |
LIBS+=-lz |
| 173 | 172 |
|
| 174 | 173 |
sound-obj-y = |
| b/hw/gt64xxx.c | ||
|---|---|---|
| 297 | 297 |
s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21; |
| 298 | 298 |
s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; |
| 299 | 299 |
isa_mem_base = s->PCI0IO_start; |
| 300 |
isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length); |
|
| 300 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 301 |
isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length, 1); |
|
| 302 |
#else |
|
| 303 |
isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length, 0); |
|
| 304 |
#endif |
|
| 301 | 305 |
} |
| 302 | 306 |
} |
| 303 | 307 |
|
| b/hw/isa.h | ||
|---|---|---|
| 32 | 32 |
|
| 33 | 33 |
extern target_phys_addr_t isa_mem_base; |
| 34 | 34 |
|
| 35 |
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size); |
|
| 35 |
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be);
|
|
| 36 | 36 |
|
| 37 | 37 |
/* dma.c */ |
| 38 | 38 |
int DMA_get_channel_mode (int nchan); |
| b/hw/isa_mmio.c | ||
|---|---|---|
| 31 | 31 |
cpu_outb(addr & IOPORTS_MASK, val); |
| 32 | 32 |
} |
| 33 | 33 |
|
| 34 |
static void isa_mmio_writew (void *opaque, target_phys_addr_t addr,
|
|
| 35 |
uint32_t val)
|
|
| 34 |
static void isa_mmio_writew_be(void *opaque, target_phys_addr_t addr,
|
|
| 35 |
uint32_t val) |
|
| 36 | 36 |
{
|
| 37 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 38 | 37 |
val = bswap16(val); |
| 39 |
#endif |
|
| 40 | 38 |
cpu_outw(addr & IOPORTS_MASK, val); |
| 41 | 39 |
} |
| 42 | 40 |
|
| 43 |
static void isa_mmio_writel (void *opaque, target_phys_addr_t addr, |
|
| 44 |
uint32_t val) |
|
| 41 |
static void isa_mmio_writew_le(void *opaque, target_phys_addr_t addr, |
|
| 42 |
uint32_t val) |
|
| 43 |
{
|
|
| 44 |
cpu_outw(addr & IOPORTS_MASK, val); |
|
| 45 |
} |
|
| 46 |
|
|
| 47 |
static void isa_mmio_writel_be(void *opaque, target_phys_addr_t addr, |
|
| 48 |
uint32_t val) |
|
| 45 | 49 |
{
|
| 46 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 47 | 50 |
val = bswap32(val); |
| 48 |
#endif |
|
| 51 |
cpu_outl(addr & IOPORTS_MASK, val); |
|
| 52 |
} |
|
| 53 |
|
|
| 54 |
static void isa_mmio_writel_le(void *opaque, target_phys_addr_t addr, |
|
| 55 |
uint32_t val) |
|
| 56 |
{
|
|
| 49 | 57 |
cpu_outl(addr & IOPORTS_MASK, val); |
| 50 | 58 |
} |
| 51 | 59 |
|
| ... | ... | |
| 57 | 65 |
return val; |
| 58 | 66 |
} |
| 59 | 67 |
|
| 60 |
static uint32_t isa_mmio_readw (void *opaque, target_phys_addr_t addr)
|
|
| 68 |
static uint32_t isa_mmio_readw_be(void *opaque, target_phys_addr_t addr)
|
|
| 61 | 69 |
{
|
| 62 | 70 |
uint32_t val; |
| 63 | 71 |
|
| 64 | 72 |
val = cpu_inw(addr & IOPORTS_MASK); |
| 65 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 66 | 73 |
val = bswap16(val); |
| 67 |
#endif |
|
| 68 | 74 |
return val; |
| 69 | 75 |
} |
| 70 | 76 |
|
| 71 |
static uint32_t isa_mmio_readl (void *opaque, target_phys_addr_t addr) |
|
| 77 |
static uint32_t isa_mmio_readw_le(void *opaque, target_phys_addr_t addr) |
|
| 78 |
{
|
|
| 79 |
uint32_t val; |
|
| 80 |
|
|
| 81 |
val = cpu_inw(addr & IOPORTS_MASK); |
|
| 82 |
return val; |
|
| 83 |
} |
|
| 84 |
|
|
| 85 |
static uint32_t isa_mmio_readl_be(void *opaque, target_phys_addr_t addr) |
|
| 72 | 86 |
{
|
| 73 | 87 |
uint32_t val; |
| 74 | 88 |
|
| 75 | 89 |
val = cpu_inl(addr & IOPORTS_MASK); |
| 76 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 77 | 90 |
val = bswap32(val); |
| 78 |
#endif |
|
| 79 | 91 |
return val; |
| 80 | 92 |
} |
| 81 | 93 |
|
| 82 |
static CPUWriteMemoryFunc * const isa_mmio_write[] = {
|
|
| 94 |
static uint32_t isa_mmio_readl_le(void *opaque, target_phys_addr_t addr) |
|
| 95 |
{
|
|
| 96 |
uint32_t val; |
|
| 97 |
|
|
| 98 |
val = cpu_inl(addr & IOPORTS_MASK); |
|
| 99 |
return val; |
|
| 100 |
} |
|
| 101 |
|
|
| 102 |
static CPUWriteMemoryFunc * const isa_mmio_write_be[] = {
|
|
| 103 |
&isa_mmio_writeb, |
|
| 104 |
&isa_mmio_writew_be, |
|
| 105 |
&isa_mmio_writel_be, |
|
| 106 |
}; |
|
| 107 |
|
|
| 108 |
static CPUReadMemoryFunc * const isa_mmio_read_be[] = {
|
|
| 109 |
&isa_mmio_readb, |
|
| 110 |
&isa_mmio_readw_be, |
|
| 111 |
&isa_mmio_readl_be, |
|
| 112 |
}; |
|
| 113 |
|
|
| 114 |
static CPUWriteMemoryFunc * const isa_mmio_write_le[] = {
|
|
| 83 | 115 |
&isa_mmio_writeb, |
| 84 |
&isa_mmio_writew, |
|
| 85 |
&isa_mmio_writel, |
|
| 116 |
&isa_mmio_writew_le,
|
|
| 117 |
&isa_mmio_writel_le,
|
|
| 86 | 118 |
}; |
| 87 | 119 |
|
| 88 |
static CPUReadMemoryFunc * const isa_mmio_read[] = {
|
|
| 120 |
static CPUReadMemoryFunc * const isa_mmio_read_le[] = {
|
|
| 89 | 121 |
&isa_mmio_readb, |
| 90 |
&isa_mmio_readw, |
|
| 91 |
&isa_mmio_readl, |
|
| 122 |
&isa_mmio_readw_le,
|
|
| 123 |
&isa_mmio_readl_le,
|
|
| 92 | 124 |
}; |
| 93 | 125 |
|
| 94 | 126 |
static int isa_mmio_iomemtype = 0; |
| 95 | 127 |
|
| 96 |
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size) |
|
| 128 |
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be)
|
|
| 97 | 129 |
{
|
| 98 | 130 |
if (!isa_mmio_iomemtype) {
|
| 99 |
isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read, |
|
| 100 |
isa_mmio_write, NULL); |
|
| 131 |
if (be) {
|
|
| 132 |
isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_be, |
|
| 133 |
isa_mmio_write_be, |
|
| 134 |
NULL); |
|
| 135 |
} else {
|
|
| 136 |
isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_le, |
|
| 137 |
isa_mmio_write_le, |
|
| 138 |
NULL); |
|
| 139 |
} |
|
| 101 | 140 |
} |
| 102 | 141 |
cpu_register_physical_memory(base, size, isa_mmio_iomemtype); |
| 103 | 142 |
} |
| b/hw/mips_jazz.c | ||
|---|---|---|
| 192 | 192 |
pcspk_init(pit); |
| 193 | 193 |
|
| 194 | 194 |
/* ISA IO space at 0x90000000 */ |
| 195 |
isa_mmio_init(0x90000000, 0x01000000); |
|
| 195 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 196 |
isa_mmio_init(0x90000000, 0x01000000, 1); |
|
| 197 |
#else |
|
| 198 |
isa_mmio_init(0x90000000, 0x01000000, 0); |
|
| 199 |
#endif |
|
| 200 |
|
|
| 196 | 201 |
isa_mem_base = 0x11000000; |
| 197 | 202 |
|
| 198 | 203 |
/* Video card */ |
| b/hw/mips_mipssim.c | ||
|---|---|---|
| 182 | 182 |
cpu_mips_clock_init(env); |
| 183 | 183 |
|
| 184 | 184 |
/* Register 64 KB of ISA IO space at 0x1fd00000. */ |
| 185 |
isa_mmio_init(0x1fd00000, 0x00010000); |
|
| 185 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 186 |
isa_mmio_init(0x1fd00000, 0x00010000, 1); |
|
| 187 |
#else |
|
| 188 |
isa_mmio_init(0x1fd00000, 0x00010000, 0); |
|
| 189 |
#endif |
|
| 186 | 190 |
|
| 187 | 191 |
/* A single 16450 sits at offset 0x3f8. It is attached to |
| 188 | 192 |
MIPS CPU INT2, which is interrupt 4. */ |
| b/hw/mips_r4k.c | ||
|---|---|---|
| 261 | 261 |
rtc_state = rtc_init(2000); |
| 262 | 262 |
|
| 263 | 263 |
/* Register 64 KB of ISA IO space at 0x14000000 */ |
| 264 |
isa_mmio_init(0x14000000, 0x00010000); |
|
| 264 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 265 |
isa_mmio_init(0x14000000, 0x00010000, 1); |
|
| 266 |
#else |
|
| 267 |
isa_mmio_init(0x14000000, 0x00010000, 0); |
|
| 268 |
#endif |
|
| 265 | 269 |
isa_mem_base = 0x10000000; |
| 266 | 270 |
|
| 267 | 271 |
pit = pit_init(0x40, i8259[0]); |
| b/hw/ppc440.c | ||
|---|---|---|
| 85 | 85 |
if (!*pcip) |
| 86 | 86 |
printf("couldn't create PCI controller!\n");
|
| 87 | 87 |
|
| 88 |
isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN); |
|
| 88 |
isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN, 1);
|
|
| 89 | 89 |
|
| 90 | 90 |
if (serial_hds[0] != NULL) {
|
| 91 | 91 |
serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE, |
| b/hw/ppc_newworld.c | ||
|---|---|---|
| 291 | 291 |
isa_mem_base = 0x80000000; |
| 292 | 292 |
|
| 293 | 293 |
/* Register 8 MB of ISA IO space */ |
| 294 |
isa_mmio_init(0xf2000000, 0x00800000); |
|
| 294 |
isa_mmio_init(0xf2000000, 0x00800000, 1);
|
|
| 295 | 295 |
|
| 296 | 296 |
/* UniN init */ |
| 297 | 297 |
unin_memory = cpu_register_io_memory(unin_read, unin_write, NULL); |
| b/hw/ppc_oldworld.c | ||
|---|---|---|
| 304 | 304 |
isa_mem_base = 0x80000000; |
| 305 | 305 |
|
| 306 | 306 |
/* Register 2 MB of ISA IO space */ |
| 307 |
isa_mmio_init(0xfe000000, 0x00200000); |
|
| 307 |
isa_mmio_init(0xfe000000, 0x00200000, 1);
|
|
| 308 | 308 |
|
| 309 | 309 |
/* XXX: we register only 1 output pin for heathrow PIC */ |
| 310 | 310 |
heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *)); |
| b/hw/ppce500_mpc8544ds.c | ||
|---|---|---|
| 218 | 218 |
if (!pci_bus) |
| 219 | 219 |
printf("couldn't create PCI controller!\n");
|
| 220 | 220 |
|
| 221 |
isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN); |
|
| 221 |
isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN, 1);
|
|
| 222 | 222 |
|
| 223 | 223 |
if (pci_bus) {
|
| 224 | 224 |
/* Register network interfaces. */ |
| b/hw/sun4u.c | ||
|---|---|---|
| 520 | 520 |
region_num, addr); |
| 521 | 521 |
switch (region_num) {
|
| 522 | 522 |
case 0: |
| 523 |
isa_mmio_init(addr, 0x1000000); |
|
| 523 |
isa_mmio_init(addr, 0x1000000, 1);
|
|
| 524 | 524 |
break; |
| 525 | 525 |
case 1: |
| 526 |
isa_mmio_init(addr, 0x800000); |
|
| 526 |
isa_mmio_init(addr, 0x800000, 1);
|
|
| 527 | 527 |
break; |
| 528 | 528 |
} |
| 529 | 529 |
} |
| b/hw/versatile_pci.c | ||
|---|---|---|
| 108 | 108 |
|
| 109 | 109 |
if (s->realview) {
|
| 110 | 110 |
/* IO memory area. */ |
| 111 |
isa_mmio_init(base + 0x03000000, 0x00100000); |
|
| 111 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 112 |
isa_mmio_init(base + 0x03000000, 0x00100000, 1); |
|
| 113 |
#else |
|
| 114 |
isa_mmio_init(base + 0x03000000, 0x00100000, 0); |
|
| 115 |
#endif |
|
| 112 | 116 |
} |
| 113 | 117 |
} |
| 114 | 118 |
|
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