Revision 8417845e

b/target-alpha/cpu.h
317 317
    IPR_LAST,
318 318
};
319 319

  
320
typedef struct CPUAlphaState CPUAlphaState;
320
/* MMU modes definitions */
321

  
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/* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user.
323
   The Unix PALcode only exposes the kernel and user modes; presumably
324
   executive and supervisor are used by VMS.
325

  
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   PALcode itself uses physical mode for code and kernel mode for data;
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   there are PALmode instructions that can access data via physical mode
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   or via an os-installed "alternate mode", which is one of the 4 above.
329

  
330
   QEMU does not currently properly distinguish between code/data when
331
   looking up addresses.  To avoid having to address this issue, our
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   emulated PALcode will cheat and use the KSEG mapping for its code+data
333
   rather than physical addresses.
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   Moreover, we're only emulating Unix PALcode, and not attempting VMS.
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   All of which allows us to drop all but kernel and user modes.
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   Elide the unused MMU modes to save space.  */
321 339

  
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#define NB_MMU_MODES 4
340
#define NB_MMU_MODES 2
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#define MMU_MODE0_SUFFIX _kernel
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#define MMU_MODE1_SUFFIX _user
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#define MMU_KERNEL_IDX   0
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#define MMU_USER_IDX     1
346

  
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typedef struct CPUAlphaState CPUAlphaState;
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324 349
struct CPUAlphaState {
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    uint64_t ir[31];
......
370 395
#define cpu_gen_code cpu_alpha_gen_code
371 396
#define cpu_signal_handler cpu_alpha_signal_handler
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _kernel
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#define MMU_MODE1_SUFFIX _executive
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#define MMU_MODE2_SUFFIX _supervisor
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#define MMU_MODE3_SUFFIX _user
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#define MMU_USER_IDX 3
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static inline int cpu_mmu_index (CPUState *env)
380 399
{
381
    return (env->ps >> 3) & 3;
400
    return (env->ps >> 3) & 1;
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}
383 402

  
384 403
#include "cpu-all.h"
b/target-alpha/translate.c
1522 1522
#ifndef CONFIG_USER_ONLY
1523 1523
        if (palcode < 0x40) {
1524 1524
            /* Privileged PAL code */
1525
            if (ctx->mem_idx & 1)
1525
            if (ctx->mem_idx != MMU_KERNEL_IDX) {
1526 1526
                goto invalid_opc;
1527
            }
1527 1528
            ret = gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x3F) << 6), 0);
1528 1529
        }
1529 1530
#endif
......
2651 2652
                goto invalid_opc;
2652 2653
            case 0xA:
2653 2654
                /* Longword virtual access with protection check (hw_ldl/w) */
2654
                tcg_gen_qemu_ld32s(cpu_ir[ra], addr, 0);
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                tcg_gen_qemu_ld32s(cpu_ir[ra], addr, MMU_KERNEL_IDX);
2655 2656
                break;
2656 2657
            case 0xB:
2657 2658
                /* Quadword virtual access with protection check (hw_ldq/w) */
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                tcg_gen_qemu_ld64(cpu_ir[ra], addr, 0);
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                tcg_gen_qemu_ld64(cpu_ir[ra], addr, MMU_KERNEL_IDX);
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                break;
2660 2661
            case 0xC:
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                /* Longword virtual access with alt access mode (hw_ldl/a)*/

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