| 378 |
378 |
VGAState *s = opaque;
|
| 379 |
379 |
uint32_t val;
|
| 380 |
380 |
|
| 381 |
|
if (s->vbe_index <= VBE_DISPI_INDEX_NB)
|
| 382 |
|
val = s->vbe_regs[s->vbe_index];
|
| 383 |
|
else
|
|
381 |
if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
|
|
382 |
if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
|
|
383 |
switch(s->vbe_index) {
|
|
384 |
/* XXX: do not hardcode ? */
|
|
385 |
case VBE_DISPI_INDEX_XRES:
|
|
386 |
val = VBE_DISPI_MAX_XRES;
|
|
387 |
break;
|
|
388 |
case VBE_DISPI_INDEX_YRES:
|
|
389 |
val = VBE_DISPI_MAX_YRES;
|
|
390 |
break;
|
|
391 |
case VBE_DISPI_INDEX_BPP:
|
|
392 |
val = VBE_DISPI_MAX_BPP;
|
|
393 |
break;
|
|
394 |
default:
|
|
395 |
val = s->vbe_regs[s->vbe_index];
|
|
396 |
break;
|
|
397 |
}
|
|
398 |
} else {
|
|
399 |
val = s->vbe_regs[s->vbe_index];
|
|
400 |
}
|
|
401 |
} else {
|
| 384 |
402 |
val = 0;
|
|
403 |
}
|
| 385 |
404 |
#ifdef DEBUG_BOCHS_VBE
|
| 386 |
405 |
printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
|
| 387 |
406 |
#endif
|
| ... | ... | |
| 434 |
453 |
s->bank_offset = (val << 16);
|
| 435 |
454 |
break;
|
| 436 |
455 |
case VBE_DISPI_INDEX_ENABLE:
|
| 437 |
|
if (val & VBE_DISPI_ENABLED) {
|
|
456 |
if ((val & VBE_DISPI_ENABLED) &&
|
|
457 |
!(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
|
| 438 |
458 |
int h, shift_control;
|
| 439 |
459 |
|
| 440 |
460 |
s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
|
| ... | ... | |
| 450 |
470 |
s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
|
| 451 |
471 |
((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
|
| 452 |
472 |
s->vbe_start_addr = 0;
|
| 453 |
|
|
|
473 |
|
| 454 |
474 |
/* clear the screen (should be done in BIOS) */
|
| 455 |
475 |
if (!(val & VBE_DISPI_NOCLEARMEM)) {
|
| 456 |
476 |
memset(s->vram_ptr, 0,
|
| ... | ... | |
| 464 |
484 |
s->cr[0x13] = s->vbe_line_offset >> 3;
|
| 465 |
485 |
/* width */
|
| 466 |
486 |
s->cr[0x01] = (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
|
| 467 |
|
/* height */
|
|
487 |
/* height (only meaningful if < 1024) */
|
| 468 |
488 |
h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
|
| 469 |
489 |
s->cr[0x12] = h;
|
| 470 |
490 |
s->cr[0x07] = (s->cr[0x07] & ~0x42) |
|
| ... | ... | |
| 1310 |
1330 |
{
|
| 1311 |
1331 |
int width, height;
|
| 1312 |
1332 |
|
| 1313 |
|
width = (s->cr[0x01] + 1) * 8;
|
| 1314 |
|
height = s->cr[0x12] |
|
| 1315 |
|
((s->cr[0x07] & 0x02) << 7) |
|
| 1316 |
|
((s->cr[0x07] & 0x40) << 3);
|
| 1317 |
|
height = (height + 1);
|
|
1333 |
#ifdef CONFIG_BOCHS_VBE
|
|
1334 |
if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
|
|
1335 |
width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
|
|
1336 |
height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
|
|
1337 |
} else
|
|
1338 |
#endif
|
|
1339 |
{
|
|
1340 |
width = (s->cr[0x01] + 1) * 8;
|
|
1341 |
height = s->cr[0x12] |
|
|
1342 |
((s->cr[0x07] & 0x02) << 7) |
|
|
1343 |
((s->cr[0x07] & 0x40) << 3);
|
|
1344 |
height = (height + 1);
|
|
1345 |
}
|
| 1318 |
1346 |
*pwidth = width;
|
| 1319 |
1347 |
*pheight = height;
|
| 1320 |
1348 |
}
|