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/*
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 * QEMU Sun4u/Sun4v System Emulator
3
 *
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 * Copyright (c) 2005 Fabrice Bellard
5
 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
23
 */
24
#include "hw.h"
25
#include "pci.h"
26
#include "pc.h"
27
#include "nvram.h"
28
#include "fdc.h"
29
#include "net.h"
30
#include "qemu-timer.h"
31
#include "sysemu.h"
32
#include "boards.h"
33
#include "firmware_abi.h"
34
#include "fw_cfg.h"
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#include "sysbus.h"
36
#include "ide.h"
37

    
38
//#define DEBUG_IRQ
39

    
40
#ifdef DEBUG_IRQ
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#define DPRINTF(fmt, ...)                                       \
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    do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
43
#else
44
#define DPRINTF(fmt, ...)
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#endif
46

    
47
#define KERNEL_LOAD_ADDR     0x00404000
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#define CMDLINE_ADDR         0x003ff000
49
#define INITRD_LOAD_ADDR     0x00300000
50
#define PROM_SIZE_MAX        (4 * 1024 * 1024)
51
#define PROM_VADDR           0x000ffd00000ULL
52
#define APB_SPECIAL_BASE     0x1fe00000000ULL
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#define APB_MEM_BASE         0x1ff00000000ULL
54
#define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
55
#define PROM_FILENAME        "openbios-sparc64"
56
#define NVRAM_SIZE           0x2000
57
#define MAX_IDE_BUS          2
58
#define BIOS_CFG_IOPORT      0x510
59
#define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
60
#define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
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#define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
62

    
63
#define MAX_PILS 16
64

    
65
#define TICK_INT_DIS         0x8000000000000000ULL
66
#define TICK_MAX             0x7fffffffffffffffULL
67

    
68
struct hwdef {
69
    const char * const default_cpu_model;
70
    uint16_t machine_id;
71
    uint64_t prom_addr;
72
    uint64_t console_serial_base;
73
};
74

    
75
int DMA_get_channel_mode (int nchan)
76
{
77
    return 0;
78
}
79
int DMA_read_memory (int nchan, void *buf, int pos, int size)
80
{
81
    return 0;
82
}
83
int DMA_write_memory (int nchan, void *buf, int pos, int size)
84
{
85
    return 0;
86
}
87
void DMA_hold_DREQ (int nchan) {}
88
void DMA_release_DREQ (int nchan) {}
89
void DMA_schedule(int nchan) {}
90
void DMA_init (int high_page_enable) {}
91
void DMA_register_channel (int nchan,
92
                           DMA_transfer_handler transfer_handler,
93
                           void *opaque)
94
{
95
}
96

    
97
static int fw_cfg_boot_set(void *opaque, const char *boot_device)
98
{
99
    fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
100
    return 0;
101
}
102

    
103
static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
104
                                   const char *arch,
105
                                   ram_addr_t RAM_size,
106
                                   const char *boot_devices,
107
                                   uint32_t kernel_image, uint32_t kernel_size,
108
                                   const char *cmdline,
109
                                   uint32_t initrd_image, uint32_t initrd_size,
110
                                   uint32_t NVRAM_image,
111
                                   int width, int height, int depth,
112
                                   const uint8_t *macaddr)
113
{
114
    unsigned int i;
115
    uint32_t start, end;
116
    uint8_t image[0x1ff0];
117
    struct OpenBIOS_nvpart_v1 *part_header;
118

    
119
    memset(image, '\0', sizeof(image));
120

    
121
    start = 0;
122

    
123
    // OpenBIOS nvram variables
124
    // Variable partition
125
    part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
126
    part_header->signature = OPENBIOS_PART_SYSTEM;
127
    pstrcpy(part_header->name, sizeof(part_header->name), "system");
128

    
129
    end = start + sizeof(struct OpenBIOS_nvpart_v1);
130
    for (i = 0; i < nb_prom_envs; i++)
131
        end = OpenBIOS_set_var(image, end, prom_envs[i]);
132

    
133
    // End marker
134
    image[end++] = '\0';
135

    
136
    end = start + ((end - start + 15) & ~15);
137
    OpenBIOS_finish_partition(part_header, end - start);
138

    
139
    // free partition
140
    start = end;
141
    part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
142
    part_header->signature = OPENBIOS_PART_FREE;
143
    pstrcpy(part_header->name, sizeof(part_header->name), "free");
144

    
145
    end = 0x1fd0;
146
    OpenBIOS_finish_partition(part_header, end - start);
147

    
148
    Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
149

    
150
    for (i = 0; i < sizeof(image); i++)
151
        m48t59_write(nvram, i, image[i]);
152

    
153
    return 0;
154
}
155
static unsigned long sun4u_load_kernel(const char *kernel_filename,
156
                                       const char *initrd_filename,
157
                                       ram_addr_t RAM_size, long *initrd_size)
158
{
159
    int linux_boot;
160
    unsigned int i;
161
    long kernel_size;
162

    
163
    linux_boot = (kernel_filename != NULL);
164

    
165
    kernel_size = 0;
166
    if (linux_boot) {
167
        kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
168
        if (kernel_size < 0)
169
            kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
170
                                    RAM_size - KERNEL_LOAD_ADDR);
171
        if (kernel_size < 0)
172
            kernel_size = load_image_targphys(kernel_filename,
173
                                              KERNEL_LOAD_ADDR,
174
                                              RAM_size - KERNEL_LOAD_ADDR);
175
        if (kernel_size < 0) {
176
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
177
                    kernel_filename);
178
            exit(1);
179
        }
180

    
181
        /* load initrd */
182
        *initrd_size = 0;
183
        if (initrd_filename) {
184
            *initrd_size = load_image_targphys(initrd_filename,
185
                                               INITRD_LOAD_ADDR,
186
                                               RAM_size - INITRD_LOAD_ADDR);
187
            if (*initrd_size < 0) {
188
                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
189
                        initrd_filename);
190
                exit(1);
191
            }
192
        }
193
        if (*initrd_size > 0) {
194
            for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
195
                if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
196
                    stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
197
                    stl_phys(KERNEL_LOAD_ADDR + i + 20, *initrd_size);
198
                    break;
199
                }
200
            }
201
        }
202
    }
203
    return kernel_size;
204
}
205

    
206
void pic_info(Monitor *mon)
207
{
208
}
209

    
210
void irq_info(Monitor *mon)
211
{
212
}
213

    
214
void cpu_check_irqs(CPUState *env)
215
{
216
    uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) |
217
        ((env->softint & SOFTINT_TIMER) << 14);
218

    
219
    if (pil && (env->interrupt_index == 0 ||
220
                (env->interrupt_index & ~15) == TT_EXTINT)) {
221
        unsigned int i;
222

    
223
        for (i = 15; i > 0; i--) {
224
            if (pil & (1 << i)) {
225
                int old_interrupt = env->interrupt_index;
226

    
227
                env->interrupt_index = TT_EXTINT | i;
228
                if (old_interrupt != env->interrupt_index) {
229
                    DPRINTF("Set CPU IRQ %d\n", i);
230
                    cpu_interrupt(env, CPU_INTERRUPT_HARD);
231
                }
232
                break;
233
            }
234
        }
235
    } else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) {
236
        DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
237
        env->interrupt_index = 0;
238
        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
239
    }
240
}
241

    
242
static void cpu_set_irq(void *opaque, int irq, int level)
243
{
244
    CPUState *env = opaque;
245

    
246
    if (level) {
247
        DPRINTF("Raise CPU IRQ %d\n", irq);
248
        env->halted = 0;
249
        env->pil_in |= 1 << irq;
250
        cpu_check_irqs(env);
251
    } else {
252
        DPRINTF("Lower CPU IRQ %d\n", irq);
253
        env->pil_in &= ~(1 << irq);
254
        cpu_check_irqs(env);
255
    }
256
}
257

    
258
typedef struct ResetData {
259
    CPUState *env;
260
    uint64_t reset_addr;
261
} ResetData;
262

    
263
static void main_cpu_reset(void *opaque)
264
{
265
    ResetData *s = (ResetData *)opaque;
266
    CPUState *env = s->env;
267

    
268
    cpu_reset(env);
269
    env->tick_cmpr = TICK_INT_DIS | 0;
270
    ptimer_set_limit(env->tick, TICK_MAX, 1);
271
    ptimer_run(env->tick, 1);
272
    env->stick_cmpr = TICK_INT_DIS | 0;
273
    ptimer_set_limit(env->stick, TICK_MAX, 1);
274
    ptimer_run(env->stick, 1);
275
    env->hstick_cmpr = TICK_INT_DIS | 0;
276
    ptimer_set_limit(env->hstick, TICK_MAX, 1);
277
    ptimer_run(env->hstick, 1);
278
    env->gregs[1] = 0; // Memory start
279
    env->gregs[2] = ram_size; // Memory size
280
    env->gregs[3] = 0; // Machine description XXX
281
    env->pc = s->reset_addr;
282
    env->npc = env->pc + 4;
283
}
284

    
285
static void tick_irq(void *opaque)
286
{
287
    CPUState *env = opaque;
288

    
289
    if (!(env->tick_cmpr & TICK_INT_DIS)) {
290
        env->softint |= SOFTINT_TIMER;
291
        cpu_interrupt(env, CPU_INTERRUPT_TIMER);
292
    }
293
}
294

    
295
static void stick_irq(void *opaque)
296
{
297
    CPUState *env = opaque;
298

    
299
    if (!(env->stick_cmpr & TICK_INT_DIS)) {
300
        env->softint |= SOFTINT_STIMER;
301
        cpu_interrupt(env, CPU_INTERRUPT_TIMER);
302
    }
303
}
304

    
305
static void hstick_irq(void *opaque)
306
{
307
    CPUState *env = opaque;
308

    
309
    if (!(env->hstick_cmpr & TICK_INT_DIS)) {
310
        cpu_interrupt(env, CPU_INTERRUPT_TIMER);
311
    }
312
}
313

    
314
void cpu_tick_set_count(void *opaque, uint64_t count)
315
{
316
    ptimer_set_count(opaque, -count);
317
}
318

    
319
uint64_t cpu_tick_get_count(void *opaque)
320
{
321
    return -ptimer_get_count(opaque);
322
}
323

    
324
void cpu_tick_set_limit(void *opaque, uint64_t limit)
325
{
326
    ptimer_set_limit(opaque, -limit, 0);
327
}
328

    
329
static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
330
static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
331

    
332
static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
333
static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
334

    
335
static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
336
                              uint32_t addr, uint32_t size, int type)
337
{
338
    DPRINTF("Mapping region %d registers at %08x\n", region_num, addr);
339
    switch (region_num) {
340
    case 0:
341
        isa_mmio_init(addr, 0x1000000);
342
        break;
343
    case 1:
344
        isa_mmio_init(addr, 0x800000);
345
        break;
346
    }
347
}
348

    
349
static void dummy_isa_irq_handler(void *opaque, int n, int level)
350
{
351
}
352

    
353
/* EBUS (Eight bit bus) bridge */
354
static void
355
pci_ebus_init(PCIBus *bus, int devfn)
356
{
357
    qemu_irq *isa_irq;
358

    
359
    pci_create_simple(bus, devfn, "ebus");
360
    isa_irq = qemu_allocate_irqs(dummy_isa_irq_handler, NULL, 16);
361
    isa_bus_irqs(isa_irq);
362
}
363

    
364
static int
365
pci_ebus_init1(PCIDevice *s)
366
{
367
    isa_bus_new(&s->qdev);
368

    
369
    pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN);
370
    pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS);
371
    s->config[0x04] = 0x06; // command = bus master, pci mem
372
    s->config[0x05] = 0x00;
373
    s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
374
    s->config[0x07] = 0x03; // status = medium devsel
375
    s->config[0x08] = 0x01; // revision
376
    s->config[0x09] = 0x00; // programming i/f
377
    pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER);
378
    s->config[0x0D] = 0x0a; // latency_timer
379
    s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
380

    
381
    pci_register_bar(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM,
382
                           ebus_mmio_mapfunc);
383
    pci_register_bar(s, 1, 0x800000,  PCI_ADDRESS_SPACE_MEM,
384
                           ebus_mmio_mapfunc);
385
    return 0;
386
}
387

    
388
static PCIDeviceInfo ebus_info = {
389
    .qdev.name = "ebus",
390
    .qdev.size = sizeof(PCIDevice),
391
    .init = pci_ebus_init1,
392
};
393

    
394
static void pci_ebus_register(void)
395
{
396
    pci_qdev_register(&ebus_info);
397
}
398

    
399
device_init(pci_ebus_register);
400

    
401
/* Boot PROM (OpenBIOS) */
402
static void prom_init(target_phys_addr_t addr, const char *bios_name)
403
{
404
    DeviceState *dev;
405
    SysBusDevice *s;
406
    char *filename;
407
    int ret;
408

    
409
    dev = qdev_create(NULL, "openprom");
410
    qdev_init(dev);
411
    s = sysbus_from_qdev(dev);
412

    
413
    sysbus_mmio_map(s, 0, addr);
414

    
415
    /* load boot prom */
416
    if (bios_name == NULL) {
417
        bios_name = PROM_FILENAME;
418
    }
419
    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
420
    if (filename) {
421
        ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL);
422
        if (ret < 0 || ret > PROM_SIZE_MAX) {
423
            ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
424
        }
425
        qemu_free(filename);
426
    } else {
427
        ret = -1;
428
    }
429
    if (ret < 0 || ret > PROM_SIZE_MAX) {
430
        fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
431
        exit(1);
432
    }
433
}
434

    
435
static int prom_init1(SysBusDevice *dev)
436
{
437
    ram_addr_t prom_offset;
438

    
439
    prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
440
    sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
441
    return 0;
442
}
443

    
444
static SysBusDeviceInfo prom_info = {
445
    .init = prom_init1,
446
    .qdev.name  = "openprom",
447
    .qdev.size  = sizeof(SysBusDevice),
448
    .qdev.props = (Property[]) {
449
        {/* end of property list */}
450
    }
451
};
452

    
453
static void prom_register_devices(void)
454
{
455
    sysbus_register_withprop(&prom_info);
456
}
457

    
458
device_init(prom_register_devices);
459

    
460

    
461
typedef struct RamDevice
462
{
463
    SysBusDevice busdev;
464
    uint64_t size;
465
} RamDevice;
466

    
467
/* System RAM */
468
static int ram_init1(SysBusDevice *dev)
469
{
470
    ram_addr_t RAM_size, ram_offset;
471
    RamDevice *d = FROM_SYSBUS(RamDevice, dev);
472

    
473
    RAM_size = d->size;
474

    
475
    ram_offset = qemu_ram_alloc(RAM_size);
476
    sysbus_init_mmio(dev, RAM_size, ram_offset);
477
    return 0;
478
}
479

    
480
static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
481
{
482
    DeviceState *dev;
483
    SysBusDevice *s;
484
    RamDevice *d;
485

    
486
    /* allocate RAM */
487
    dev = qdev_create(NULL, "memory");
488
    s = sysbus_from_qdev(dev);
489

    
490
    d = FROM_SYSBUS(RamDevice, s);
491
    d->size = RAM_size;
492
    qdev_init(dev);
493

    
494
    sysbus_mmio_map(s, 0, addr);
495
}
496

    
497
static SysBusDeviceInfo ram_info = {
498
    .init = ram_init1,
499
    .qdev.name  = "memory",
500
    .qdev.size  = sizeof(RamDevice),
501
    .qdev.props = (Property[]) {
502
        DEFINE_PROP_UINT64("size", RamDevice, size, 0),
503
        DEFINE_PROP_END_OF_LIST(),
504
    }
505
};
506

    
507
static void ram_register_devices(void)
508
{
509
    sysbus_register_withprop(&ram_info);
510
}
511

    
512
device_init(ram_register_devices);
513

    
514
static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
515
{
516
    CPUState *env;
517
    QEMUBH *bh;
518
    ResetData *reset_info;
519

    
520
    if (!cpu_model)
521
        cpu_model = hwdef->default_cpu_model;
522
    env = cpu_init(cpu_model);
523
    if (!env) {
524
        fprintf(stderr, "Unable to find Sparc CPU definition\n");
525
        exit(1);
526
    }
527
    bh = qemu_bh_new(tick_irq, env);
528
    env->tick = ptimer_init(bh);
529
    ptimer_set_period(env->tick, 1ULL);
530

    
531
    bh = qemu_bh_new(stick_irq, env);
532
    env->stick = ptimer_init(bh);
533
    ptimer_set_period(env->stick, 1ULL);
534

    
535
    bh = qemu_bh_new(hstick_irq, env);
536
    env->hstick = ptimer_init(bh);
537
    ptimer_set_period(env->hstick, 1ULL);
538

    
539
    reset_info = qemu_mallocz(sizeof(ResetData));
540
    reset_info->env = env;
541
    reset_info->reset_addr = hwdef->prom_addr + 0x40ULL;
542
    qemu_register_reset(main_cpu_reset, reset_info);
543
    main_cpu_reset(reset_info);
544
    // Override warm reset address with cold start address
545
    env->pc = hwdef->prom_addr + 0x20ULL;
546
    env->npc = env->pc + 4;
547

    
548
    return env;
549
}
550

    
551
static void sun4uv_init(ram_addr_t RAM_size,
552
                        const char *boot_devices,
553
                        const char *kernel_filename, const char *kernel_cmdline,
554
                        const char *initrd_filename, const char *cpu_model,
555
                        const struct hwdef *hwdef)
556
{
557
    CPUState *env;
558
    m48t59_t *nvram;
559
    unsigned int i;
560
    long initrd_size, kernel_size;
561
    PCIBus *pci_bus, *pci_bus2, *pci_bus3;
562
    qemu_irq *irq;
563
    DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
564
    BlockDriverState *fd[MAX_FD];
565
    void *fw_cfg;
566
    DriveInfo *dinfo;
567

    
568
    /* init CPUs */
569
    env = cpu_devinit(cpu_model, hwdef);
570

    
571
    /* set up devices */
572
    ram_init(0, RAM_size);
573

    
574
    prom_init(hwdef->prom_addr, bios_name);
575

    
576

    
577
    irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
578
    pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2,
579
                           &pci_bus3);
580
    isa_mem_base = VGA_BASE;
581
    pci_vga_init(pci_bus, 0, 0);
582

    
583
    // XXX Should be pci_bus3
584
    pci_ebus_init(pci_bus, -1);
585

    
586
    i = 0;
587
    if (hwdef->console_serial_base) {
588
        serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
589
                       serial_hds[i], 1);
590
        i++;
591
    }
592
    for(; i < MAX_SERIAL_PORTS; i++) {
593
        if (serial_hds[i]) {
594
            serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200,
595
                        serial_hds[i]);
596
        }
597
    }
598

    
599
    for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
600
        if (parallel_hds[i]) {
601
            parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/,
602
                          parallel_hds[i]);
603
        }
604
    }
605

    
606
    for(i = 0; i < nb_nics; i++)
607
        pci_nic_init(&nd_table[i], "ne2k_pci", NULL);
608

    
609
    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
610
        fprintf(stderr, "qemu: too many IDE bus\n");
611
        exit(1);
612
    }
613
    for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
614
        hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS,
615
                          i % MAX_IDE_DEVS);
616
    }
617

    
618
    pci_cmd646_ide_init(pci_bus, hd, 1);
619

    
620
    isa_create_simple("i8042", 1, 12);
621
    for(i = 0; i < MAX_FD; i++) {
622
        dinfo = drive_get(IF_FLOPPY, 0, i);
623
        fd[i] = dinfo ? dinfo->bdrv : NULL;
624
    }
625
    fdctrl_init_isa(fd);
626
    /* FIXME: wire up interrupts.  */
627
    nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
628

    
629
    initrd_size = 0;
630
    kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename,
631
                                    ram_size, &initrd_size);
632

    
633
    sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
634
                           KERNEL_LOAD_ADDR, kernel_size,
635
                           kernel_cmdline,
636
                           INITRD_LOAD_ADDR, initrd_size,
637
                           /* XXX: need an option to load a NVRAM image */
638
                           0,
639
                           graphic_width, graphic_height, graphic_depth,
640
                           (uint8_t *)&nd_table[0].macaddr);
641

    
642
    fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
643
    fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
644
    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
645
    fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
646
    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
647
    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
648
    if (kernel_cmdline) {
649
        fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
650
        pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
651
    } else {
652
        fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
653
    }
654
    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
655
    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
656
    fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
657

    
658
    fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
659
    fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
660
    fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
661

    
662
    qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
663
}
664

    
665
enum {
666
    sun4u_id = 0,
667
    sun4v_id = 64,
668
    niagara_id,
669
};
670

    
671
static const struct hwdef hwdefs[] = {
672
    /* Sun4u generic PC-like machine */
673
    {
674
        .default_cpu_model = "TI UltraSparc II",
675
        .machine_id = sun4u_id,
676
        .prom_addr = 0x1fff0000000ULL,
677
        .console_serial_base = 0,
678
    },
679
    /* Sun4v generic PC-like machine */
680
    {
681
        .default_cpu_model = "Sun UltraSparc T1",
682
        .machine_id = sun4v_id,
683
        .prom_addr = 0x1fff0000000ULL,
684
        .console_serial_base = 0,
685
    },
686
    /* Sun4v generic Niagara machine */
687
    {
688
        .default_cpu_model = "Sun UltraSparc T1",
689
        .machine_id = niagara_id,
690
        .prom_addr = 0xfff0000000ULL,
691
        .console_serial_base = 0xfff0c2c000ULL,
692
    },
693
};
694

    
695
/* Sun4u hardware initialisation */
696
static void sun4u_init(ram_addr_t RAM_size,
697
                       const char *boot_devices,
698
                       const char *kernel_filename, const char *kernel_cmdline,
699
                       const char *initrd_filename, const char *cpu_model)
700
{
701
    sun4uv_init(RAM_size, boot_devices, kernel_filename,
702
                kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
703
}
704

    
705
/* Sun4v hardware initialisation */
706
static void sun4v_init(ram_addr_t RAM_size,
707
                       const char *boot_devices,
708
                       const char *kernel_filename, const char *kernel_cmdline,
709
                       const char *initrd_filename, const char *cpu_model)
710
{
711
    sun4uv_init(RAM_size, boot_devices, kernel_filename,
712
                kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
713
}
714

    
715
/* Niagara hardware initialisation */
716
static void niagara_init(ram_addr_t RAM_size,
717
                         const char *boot_devices,
718
                         const char *kernel_filename, const char *kernel_cmdline,
719
                         const char *initrd_filename, const char *cpu_model)
720
{
721
    sun4uv_init(RAM_size, boot_devices, kernel_filename,
722
                kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
723
}
724

    
725
static QEMUMachine sun4u_machine = {
726
    .name = "sun4u",
727
    .desc = "Sun4u platform",
728
    .init = sun4u_init,
729
    .max_cpus = 1, // XXX for now
730
    .is_default = 1,
731
};
732

    
733
static QEMUMachine sun4v_machine = {
734
    .name = "sun4v",
735
    .desc = "Sun4v platform",
736
    .init = sun4v_init,
737
    .max_cpus = 1, // XXX for now
738
};
739

    
740
static QEMUMachine niagara_machine = {
741
    .name = "Niagara",
742
    .desc = "Sun4v platform, Niagara",
743
    .init = niagara_init,
744
    .max_cpus = 1, // XXX for now
745
};
746

    
747
static void sun4u_machine_init(void)
748
{
749
    qemu_register_machine(&sun4u_machine);
750
    qemu_register_machine(&sun4v_machine);
751
    qemu_register_machine(&niagara_machine);
752
}
753

    
754
machine_init(sun4u_machine_init);