Revision 873eb012 target-mips/translate.c
b/target-mips/translate.c | ||
---|---|---|
1349 | 1349 |
} |
1350 | 1350 |
|
1351 | 1351 |
/* CP0 (MMU and control) */ |
1352 |
static void gen_mfc0 (DisasContext *ctx, int reg, int sel) |
|
1353 |
{ |
|
1354 |
const unsigned char *rn; |
|
1355 |
|
|
1356 |
if (sel != 0 && reg != 16 && reg != 28) { |
|
1357 |
rn = "invalid"; |
|
1358 |
goto die; |
|
1359 |
} |
|
1360 |
switch (reg) { |
|
1361 |
case 0: |
|
1362 |
gen_op_mfc0_index(); |
|
1363 |
rn = "Index"; |
|
1364 |
break; |
|
1365 |
case 1: |
|
1366 |
gen_op_mfc0_random(); |
|
1367 |
rn = "Random"; |
|
1368 |
break; |
|
1369 |
case 2: |
|
1370 |
gen_op_mfc0_entrylo0(); |
|
1371 |
rn = "EntryLo0"; |
|
1372 |
break; |
|
1373 |
case 3: |
|
1374 |
gen_op_mfc0_entrylo1(); |
|
1375 |
rn = "EntryLo1"; |
|
1376 |
break; |
|
1377 |
case 4: |
|
1378 |
gen_op_mfc0_context(); |
|
1379 |
rn = "Context"; |
|
1380 |
break; |
|
1381 |
case 5: |
|
1382 |
gen_op_mfc0_pagemask(); |
|
1383 |
rn = "PageMask"; |
|
1384 |
break; |
|
1385 |
case 6: |
|
1386 |
gen_op_mfc0_wired(); |
|
1387 |
rn = "Wired"; |
|
1388 |
break; |
|
1389 |
case 8: |
|
1390 |
gen_op_mfc0_badvaddr(); |
|
1391 |
rn = "BadVaddr"; |
|
1392 |
break; |
|
1393 |
case 9: |
|
1394 |
gen_op_mfc0_count(); |
|
1395 |
rn = "Count"; |
|
1396 |
break; |
|
1397 |
case 10: |
|
1398 |
gen_op_mfc0_entryhi(); |
|
1399 |
rn = "EntryHi"; |
|
1400 |
break; |
|
1401 |
case 11: |
|
1402 |
gen_op_mfc0_compare(); |
|
1403 |
rn = "Compare"; |
|
1404 |
break; |
|
1405 |
case 12: |
|
1406 |
gen_op_mfc0_status(); |
|
1407 |
rn = "Status"; |
|
1408 |
break; |
|
1409 |
case 13: |
|
1410 |
gen_op_mfc0_cause(); |
|
1411 |
rn = "Cause"; |
|
1412 |
break; |
|
1413 |
case 14: |
|
1414 |
gen_op_mfc0_epc(); |
|
1415 |
rn = "EPC"; |
|
1416 |
break; |
|
1417 |
case 15: |
|
1418 |
gen_op_mfc0_prid(); |
|
1419 |
rn = "PRid"; |
|
1420 |
break; |
|
1421 |
case 16: |
|
1422 |
switch (sel) { |
|
1423 |
case 0: |
|
1424 |
gen_op_mfc0_config0(); |
|
1425 |
rn = "Config"; |
|
1426 |
break; |
|
1427 |
case 1: |
|
1428 |
gen_op_mfc0_config1(); |
|
1429 |
rn = "Config1"; |
|
1430 |
break; |
|
1431 |
default: |
|
1432 |
rn = "Unknown config register"; |
|
1433 |
goto die; |
|
1434 |
} |
|
1435 |
break; |
|
1436 |
case 17: |
|
1437 |
gen_op_mfc0_lladdr(); |
|
1438 |
rn = "LLAddr"; |
|
1439 |
break; |
|
1440 |
case 18: |
|
1441 |
gen_op_mfc0_watchlo(); |
|
1442 |
rn = "WatchLo"; |
|
1443 |
break; |
|
1444 |
case 19: |
|
1445 |
gen_op_mfc0_watchhi(); |
|
1446 |
rn = "WatchHi"; |
|
1447 |
break; |
|
1448 |
case 23: |
|
1449 |
gen_op_mfc0_debug(); |
|
1450 |
rn = "Debug"; |
|
1451 |
break; |
|
1452 |
case 24: |
|
1453 |
gen_op_mfc0_depc(); |
|
1454 |
rn = "DEPC"; |
|
1455 |
break; |
|
1456 |
case 28: |
|
1457 |
switch (sel) { |
|
1458 |
case 0: |
|
1459 |
gen_op_mfc0_taglo(); |
|
1460 |
rn = "TagLo"; |
|
1461 |
break; |
|
1462 |
case 1: |
|
1463 |
gen_op_mfc0_datalo(); |
|
1464 |
rn = "DataLo"; |
|
1465 |
break; |
|
1466 |
default: |
|
1467 |
rn = "unknown sel"; |
|
1468 |
goto die; |
|
1469 |
} |
|
1470 |
break; |
|
1471 |
case 30: |
|
1472 |
gen_op_mfc0_errorepc(); |
|
1473 |
rn = "ErrorEPC"; |
|
1474 |
break; |
|
1475 |
case 31: |
|
1476 |
gen_op_mfc0_desave(); |
|
1477 |
rn = "DESAVE"; |
|
1478 |
break; |
|
1479 |
default: |
|
1480 |
rn = "unknown"; |
|
1481 |
goto die; |
|
1482 |
} |
|
1483 |
#if defined MIPS_DEBUG_DISAS |
|
1484 |
if (loglevel & CPU_LOG_TB_IN_ASM) { |
|
1485 |
fprintf(logfile, "%08x mfc0 %s => %08x (%d %d)\n", |
|
1486 |
env->PC, rn, T0, reg, sel); |
|
1487 |
} |
|
1488 |
#endif |
|
1489 |
return; |
|
1490 |
|
|
1491 |
die: |
|
1492 |
#if defined MIPS_DEBUG_DISAS |
|
1493 |
if (loglevel & CPU_LOG_TB_IN_ASM) { |
|
1494 |
fprintf(logfile, "%08x mfc0 %s => %08x (%d %d)\n", |
|
1495 |
env->PC, rn, T0, reg, sel); |
|
1496 |
} |
|
1497 |
#endif |
|
1498 |
generate_exception(ctx, EXCP_RI); |
|
1499 |
} |
|
1500 |
|
|
1352 | 1501 |
static void gen_cp0 (DisasContext *ctx, uint16_t opc, int rt, int rd) |
1353 | 1502 |
{ |
1354 | 1503 |
const unsigned char *opn = "unk"; |
... | ... | |
1370 | 1519 |
/* Treat as NOP */ |
1371 | 1520 |
return; |
1372 | 1521 |
} |
1373 |
gen_op_mfc0(rd, ctx->opcode & 0x7);
|
|
1522 |
gen_mfc0(ctx, rd, ctx->opcode & 0x7);
|
|
1374 | 1523 |
gen_op_store_T0_gpr(rt); |
1375 | 1524 |
opn = "mfc0"; |
1376 | 1525 |
break; |
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