Revision 878d3096

b/target-sparc/cpu.h
18 18 
/*#define EXCP_INTERRUPT 0x100*/
19 19 

  		





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/* trap definitions */


  		





  
  21
  
    
#define TT_TFAULT   0x01


  		





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#define TT_ILL_INSN 0x02


  		





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#define TT_PRIV_INSN 0x03


  		





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#define TT_NFPU_INSN 0x04


  		





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#define TT_WIN_OVF  0x05


  		





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#define TT_WIN_UNF  0x06 


  		





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#define TT_FP_EXCP  0x08


  		





  
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#define TT_DFAULT   0x09


  		





  
  29
  
    
#define TT_EXTINT   0x10


  		





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#define TT_DIV_ZERO 0x2a


  		





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#define TT_TRAP     0x80


  		





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#define TT_EXTINT   0x10


  		





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#define PSR_NEG   (1<<23)


  		





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#define PSR_ZERO  (1<<22)


  		





  ......




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    /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */


  		





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    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];


  		





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    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];


  		





  145
  
  
    
    int error_code;


  		





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    /* MMU regs */


  		





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    uint32_t mmuregs[16];


  		





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    /* temporary float registers */


  		












  

    
      b/target-sparc/exec.h
    
  






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void do_ldd_kernel(target_ulong addr);


  		





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void do_ldd_user(target_ulong addr);


  		





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void do_ldd_raw(target_ulong addr);


  		





  44
  
  
    
void do_interrupt(int intno, int error_code);


  		





  
  44
  
    
void do_interrupt(int intno);


  		





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void raise_exception(int tt);


  		





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void memcpy32(target_ulong *dst, const target_ulong *src);


  		





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target_ulong mmu_probe(target_ulong address, int mmulev);


  		












  

    
      b/target-sparc/helper.c
    
  






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                               int is_user, int is_softmmu)


  		





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{


  		





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    env->mmuregs[4] = address;


  		





  47
  
  
    
    env->exception_index = 0; /* XXX: must be incorrect */


  		





  48
  
  
    
    env->error_code = -2; /* XXX: is it really used ! */


  		





  
  47
  
    
    if (rw & 2)


  		





  
  48
  
    
        env->exception_index = TT_TFAULT;


  		





  
  49
  
    
    else


  		





  
  50
  
    
        env->exception_index = TT_DFAULT;


  		





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    return 1;


  		





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}


  		





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  ......




  95
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                cpu_restore_state(tb, env, pc, NULL);


  		





  96
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            }


  		





  97
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        }


  		





  98
  
  
    
        raise_exception(ret);


  		





  
  100
  
    
        cpu_loop_exit();


  		





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    }


  		





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    env = saved_env;


  		





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}


  		





  ......




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int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,


  		





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                              int is_user, int is_softmmu)


  		





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{


  		





  232
  
  
    
    int exception = 0;


  		





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    target_ulong virt_addr;


  		





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    target_phys_addr_t paddr;


  		





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    unsigned long vaddr;


  		





  ......




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    env->mmuregs[3] |= (access_index << 5) | (error_code << 2) | 2;


  		





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    env->mmuregs[4] = address; /* Fault address register */


  		





  250
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  251
  
  
    
    if (env->mmuregs[0] & MMU_NF || env->psret == 0) // No fault


  		





  252
  
  
    
	return 0;


  		





  253
  
  
    
    env->exception_index = exception;


  		





  254
  
  
    
    env->error_code = error_code;


  		





  255
  
  
    
    return error_code;


  		





  
  252
  
    
    if ((env->mmuregs[0] & MMU_NF) || env->psret == 0)  {


  		





  
  253
  
    
        // No fault


  		





  
  254
  
    
	cpu_abort(env, "Unsupported MMU no fault case");


  		





  
  255
  
    
    }


  		





  
  256
  
    
    if (rw & 2)


  		





  
  257
  
    
        env->exception_index = TT_TFAULT;


  		





  
  258
  
    
    else


  		





  
  259
  
    
        env->exception_index = TT_DFAULT;


  		





  
  260
  
    
    return 1;


  		





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}


  		





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#endif


  		





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  ......




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    env = saved_env;


  		





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}


  		





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void do_interrupt(int intno, int error_code)


  		





  
  297
  
    
void do_interrupt(int intno)


  		





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{


  		





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    int cwp;


  		





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#ifdef DEBUG_PCALL


  		





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    if (loglevel & CPU_LOG_INT) {


  		





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	static int count;


  		





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	fprintf(logfile, "%6d: v=%02x e=%04x pc=%08x npc=%08x SP=%08x\n",


  		





  300
  
  
    
                count, intno, error_code,


  		





  
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	fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",


  		





  
  305
  
    
                count, intno,


  		





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                env->pc,


  		





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                env->npc, env->regwptr[6]);


  		





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#if 1


  		





  ......




  319
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#endif


  		





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#if !defined(CONFIG_USER_ONLY) 


  		





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    if (env->psret == 0) {


  		





  322
  
  
    
        cpu_abort(cpu_single_env, "Trap while interrupts disabled, Error state");


  		





  
  327
  
    
        cpu_abort(cpu_single_env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);


  		





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	return;


  		





  324
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    }


  		





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#endif


  		





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    env->psret = 0;


  		





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    cwp = (env->cwp - 1) & (NWINDOWS - 1); 


  		





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    set_cwp(cwp);


  		





  329
  
  
    
    if (intno & 0x80) {


  		





  330
  
  
    
	env->regwptr[9] = env->pc;


  		





  331
  
  
    
	env->regwptr[10] = env->npc;


  		





  332
  
  
    
    } else {


  		





  333
  
  
    
        /* XXX: this code is clearly incorrect - npc should have the


  		





  334
  
  
    
           incorrect value */


  		





  335
  
  
    
	env->regwptr[9] = env->pc - 4; // XXX?


  		





  336
  
  
    
	env->regwptr[10] = env->pc;


  		





  337
  
  
    
    }


  		





  
  334
  
    
    env->regwptr[9] = env->pc;


  		





  
  335
  
    
    env->regwptr[10] = env->npc;


  		





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    env->psrps = env->psrs;


  		





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    env->psrs = 1;


  		





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    env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);


  		












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