Revision 878d3096 target-sparc/helper.c
| b/target-sparc/helper.c | ||
|---|---|---|
| 44 | 44 |
int is_user, int is_softmmu) |
| 45 | 45 |
{
|
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env->mmuregs[4] = address; |
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env->exception_index = 0; /* XXX: must be incorrect */ |
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env->error_code = -2; /* XXX: is it really used ! */ |
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if (rw & 2) |
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env->exception_index = TT_TFAULT; |
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else |
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env->exception_index = TT_DFAULT; |
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| 49 | 51 |
return 1; |
| 50 | 52 |
} |
| 51 | 53 |
|
| ... | ... | |
| 95 | 97 |
cpu_restore_state(tb, env, pc, NULL); |
| 96 | 98 |
} |
| 97 | 99 |
} |
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raise_exception(ret);
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cpu_loop_exit();
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} |
| 100 | 102 |
env = saved_env; |
| 101 | 103 |
} |
| ... | ... | |
| 229 | 231 |
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
| 230 | 232 |
int is_user, int is_softmmu) |
| 231 | 233 |
{
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int exception = 0; |
|
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target_ulong virt_addr; |
| 234 | 235 |
target_phys_addr_t paddr; |
| 235 | 236 |
unsigned long vaddr; |
| ... | ... | |
| 248 | 249 |
env->mmuregs[3] |= (access_index << 5) | (error_code << 2) | 2; |
| 249 | 250 |
env->mmuregs[4] = address; /* Fault address register */ |
| 250 | 251 |
|
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if (env->mmuregs[0] & MMU_NF || env->psret == 0) // No fault |
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return 0; |
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env->exception_index = exception; |
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env->error_code = error_code; |
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return error_code; |
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if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) {
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// No fault |
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cpu_abort(env, "Unsupported MMU no fault case"); |
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} |
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if (rw & 2) |
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env->exception_index = TT_TFAULT; |
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else |
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env->exception_index = TT_DFAULT; |
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return 1; |
|
| 256 | 261 |
} |
| 257 | 262 |
#endif |
| 258 | 263 |
|
| ... | ... | |
| 289 | 294 |
env = saved_env; |
| 290 | 295 |
} |
| 291 | 296 |
|
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void do_interrupt(int intno, int error_code)
|
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void do_interrupt(int intno) |
|
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{
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int cwp; |
| 295 | 300 |
|
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#ifdef DEBUG_PCALL |
| 297 | 302 |
if (loglevel & CPU_LOG_INT) {
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static int count; |
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fprintf(logfile, "%6d: v=%02x e=%04x pc=%08x npc=%08x SP=%08x\n",
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count, intno, error_code,
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fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n", |
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count, intno, |
|
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env->pc, |
| 302 | 307 |
env->npc, env->regwptr[6]); |
| 303 | 308 |
#if 1 |
| ... | ... | |
| 319 | 324 |
#endif |
| 320 | 325 |
#if !defined(CONFIG_USER_ONLY) |
| 321 | 326 |
if (env->psret == 0) {
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cpu_abort(cpu_single_env, "Trap while interrupts disabled, Error state");
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cpu_abort(cpu_single_env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
|
|
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return; |
| 324 | 329 |
} |
| 325 | 330 |
#endif |
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env->psret = 0; |
| 327 | 332 |
cwp = (env->cwp - 1) & (NWINDOWS - 1); |
| 328 | 333 |
set_cwp(cwp); |
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if (intno & 0x80) {
|
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env->regwptr[9] = env->pc; |
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env->regwptr[10] = env->npc; |
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} else {
|
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/* XXX: this code is clearly incorrect - npc should have the |
|
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incorrect value */ |
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env->regwptr[9] = env->pc - 4; // XXX? |
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env->regwptr[10] = env->pc; |
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} |
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env->regwptr[9] = env->pc; |
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env->regwptr[10] = env->npc; |
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| 338 | 336 |
env->psrps = env->psrs; |
| 339 | 337 |
env->psrs = 1; |
| 340 | 338 |
env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4); |
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