Revision 87e92502 target-sparc/translate.c
b/target-sparc/translate.c | ||
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46 | 46 |
according to jump_pc[T2] */ |
47 | 47 |
|
48 | 48 |
/* global register indexes */ |
49 |
static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_dst, cpu_psr;
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|
50 |
static TCGv cpu_gregs[8]; |
|
49 |
static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_dst; |
|
50 |
static TCGv cpu_psr, cpu_fsr, cpu_gregs[8];
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|
51 | 51 |
#ifdef TARGET_SPARC64 |
52 | 52 |
static TCGv cpu_xcc; |
53 | 53 |
#endif |
... | ... | |
1269 | 1269 |
|
1270 | 1270 |
static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) |
1271 | 1271 |
{ |
1272 |
TCGv r_src; |
|
1273 | 1272 |
unsigned int offset; |
1274 | 1273 |
|
1275 |
r_src = tcg_temp_new(TCG_TYPE_TL); |
|
1276 |
tcg_gen_ld_tl(r_src, cpu_env, offsetof(CPUSPARCState, fsr)); |
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1277 |
|
|
1278 | 1274 |
switch (cc) { |
1279 | 1275 |
default: |
1280 | 1276 |
case 0x0: |
... | ... | |
1296 | 1292 |
gen_op_eval_bn(r_dst); |
1297 | 1293 |
break; |
1298 | 1294 |
case 0x1: |
1299 |
gen_op_eval_fbne(r_dst, r_src, offset);
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|
1295 |
gen_op_eval_fbne(r_dst, cpu_fsr, offset);
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|
1300 | 1296 |
break; |
1301 | 1297 |
case 0x2: |
1302 |
gen_op_eval_fblg(r_dst, r_src, offset);
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|
1298 |
gen_op_eval_fblg(r_dst, cpu_fsr, offset);
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|
1303 | 1299 |
break; |
1304 | 1300 |
case 0x3: |
1305 |
gen_op_eval_fbul(r_dst, r_src, offset);
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|
1301 |
gen_op_eval_fbul(r_dst, cpu_fsr, offset);
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|
1306 | 1302 |
break; |
1307 | 1303 |
case 0x4: |
1308 |
gen_op_eval_fbl(r_dst, r_src, offset);
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|
1304 |
gen_op_eval_fbl(r_dst, cpu_fsr, offset);
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|
1309 | 1305 |
break; |
1310 | 1306 |
case 0x5: |
1311 |
gen_op_eval_fbug(r_dst, r_src, offset);
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|
1307 |
gen_op_eval_fbug(r_dst, cpu_fsr, offset);
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|
1312 | 1308 |
break; |
1313 | 1309 |
case 0x6: |
1314 |
gen_op_eval_fbg(r_dst, r_src, offset);
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|
1310 |
gen_op_eval_fbg(r_dst, cpu_fsr, offset);
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|
1315 | 1311 |
break; |
1316 | 1312 |
case 0x7: |
1317 |
gen_op_eval_fbu(r_dst, r_src, offset);
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|
1313 |
gen_op_eval_fbu(r_dst, cpu_fsr, offset);
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|
1318 | 1314 |
break; |
1319 | 1315 |
case 0x8: |
1320 | 1316 |
gen_op_eval_ba(r_dst); |
1321 | 1317 |
break; |
1322 | 1318 |
case 0x9: |
1323 |
gen_op_eval_fbe(r_dst, r_src, offset);
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|
1319 |
gen_op_eval_fbe(r_dst, cpu_fsr, offset);
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|
1324 | 1320 |
break; |
1325 | 1321 |
case 0xa: |
1326 |
gen_op_eval_fbue(r_dst, r_src, offset);
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|
1322 |
gen_op_eval_fbue(r_dst, cpu_fsr, offset);
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|
1327 | 1323 |
break; |
1328 | 1324 |
case 0xb: |
1329 |
gen_op_eval_fbge(r_dst, r_src, offset);
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|
1325 |
gen_op_eval_fbge(r_dst, cpu_fsr, offset);
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|
1330 | 1326 |
break; |
1331 | 1327 |
case 0xc: |
1332 |
gen_op_eval_fbuge(r_dst, r_src, offset);
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|
1328 |
gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
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|
1333 | 1329 |
break; |
1334 | 1330 |
case 0xd: |
1335 |
gen_op_eval_fble(r_dst, r_src, offset);
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|
1331 |
gen_op_eval_fble(r_dst, cpu_fsr, offset);
|
|
1336 | 1332 |
break; |
1337 | 1333 |
case 0xe: |
1338 |
gen_op_eval_fbule(r_dst, r_src, offset);
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|
1334 |
gen_op_eval_fbule(r_dst, cpu_fsr, offset);
|
|
1339 | 1335 |
break; |
1340 | 1336 |
case 0xf: |
1341 |
gen_op_eval_fbo(r_dst, r_src, offset);
|
|
1337 |
gen_op_eval_fbo(r_dst, cpu_fsr, offset);
|
|
1342 | 1338 |
break; |
1343 | 1339 |
} |
1344 | 1340 |
} |
... | ... | |
1588 | 1584 |
|
1589 | 1585 |
static inline void gen_op_fpexception_im(int fsr_flags) |
1590 | 1586 |
{ |
1591 |
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr)); |
|
1592 |
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, ~FSR_FTT_MASK); |
|
1593 |
tcg_gen_ori_tl(cpu_tmp0, cpu_tmp0, fsr_flags); |
|
1594 |
tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr)); |
|
1587 |
tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK); |
|
1588 |
tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); |
|
1595 | 1589 |
gen_op_exception(TT_FP_EXCP); |
1596 | 1590 |
} |
1597 | 1591 |
|
... | ... | |
1610 | 1604 |
|
1611 | 1605 |
static inline void gen_op_clear_ieee_excp_and_FTT(void) |
1612 | 1606 |
{ |
1613 |
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr)); |
|
1614 |
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, ~(FSR_FTT_MASK | FSR_CEXC_MASK)); |
|
1615 |
tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr)); |
|
1607 |
tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK)); |
|
1616 | 1608 |
} |
1617 | 1609 |
|
1618 | 1610 |
static inline void gen_clear_float_exceptions(void) |
... | ... | |
4769 | 4761 |
cpu_psr = tcg_global_mem_new(TCG_TYPE_I32, |
4770 | 4762 |
TCG_AREG0, offsetof(CPUState, psr), |
4771 | 4763 |
"psr"); |
4764 |
cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL, |
|
4765 |
TCG_AREG0, offsetof(CPUState, fsr), |
|
4766 |
"fsr"); |
|
4772 | 4767 |
for (i = 1; i < 8; i++) |
4773 | 4768 |
cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
4774 | 4769 |
offsetof(CPUState, gregs[i]), |
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