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1 | c3d2689d | balrog | /*
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2 | c3d2689d | balrog | * Texas Instruments OMAP processors.
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3 | c3d2689d | balrog | *
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4 | c3d2689d | balrog | * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
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5 | c3d2689d | balrog | *
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6 | c3d2689d | balrog | * This program is free software; you can redistribute it and/or
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7 | c3d2689d | balrog | * modify it under the terms of the GNU General Public License as
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8 | c3d2689d | balrog | * published by the Free Software Foundation; either version 2 of
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9 | c3d2689d | balrog | * the License, or (at your option) any later version.
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10 | c3d2689d | balrog | *
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11 | c3d2689d | balrog | * This program is distributed in the hope that it will be useful,
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12 | c3d2689d | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | c3d2689d | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 | c3d2689d | balrog | * GNU General Public License for more details.
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15 | c3d2689d | balrog | *
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16 | c3d2689d | balrog | * You should have received a copy of the GNU General Public License
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17 | c3d2689d | balrog | * along with this program; if not, write to the Free Software
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18 | c3d2689d | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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19 | c3d2689d | balrog | * MA 02111-1307 USA
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20 | c3d2689d | balrog | */
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21 | c3d2689d | balrog | #ifndef hw_omap_h
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22 | c3d2689d | balrog | # define hw_omap_h "omap.h" |
23 | c3d2689d | balrog | |
24 | c3d2689d | balrog | # define OMAP_EMIFS_BASE 0x00000000 |
25 | c3d2689d | balrog | # define OMAP_CS0_BASE 0x00000000 |
26 | c3d2689d | balrog | # define OMAP_CS1_BASE 0x04000000 |
27 | c3d2689d | balrog | # define OMAP_CS2_BASE 0x08000000 |
28 | c3d2689d | balrog | # define OMAP_CS3_BASE 0x0c000000 |
29 | c3d2689d | balrog | # define OMAP_EMIFF_BASE 0x10000000 |
30 | c3d2689d | balrog | # define OMAP_IMIF_BASE 0x20000000 |
31 | c3d2689d | balrog | # define OMAP_LOCALBUS_BASE 0x30000000 |
32 | c3d2689d | balrog | # define OMAP_MPUI_BASE 0xe1000000 |
33 | c3d2689d | balrog | |
34 | c3d2689d | balrog | # define OMAP730_SRAM_SIZE 0x00032000 |
35 | c3d2689d | balrog | # define OMAP15XX_SRAM_SIZE 0x00030000 |
36 | c3d2689d | balrog | # define OMAP16XX_SRAM_SIZE 0x00004000 |
37 | c3d2689d | balrog | # define OMAP1611_SRAM_SIZE 0x0003e800 |
38 | c3d2689d | balrog | # define OMAP_CS0_SIZE 0x04000000 |
39 | c3d2689d | balrog | # define OMAP_CS1_SIZE 0x04000000 |
40 | c3d2689d | balrog | # define OMAP_CS2_SIZE 0x04000000 |
41 | c3d2689d | balrog | # define OMAP_CS3_SIZE 0x04000000 |
42 | c3d2689d | balrog | |
43 | c3d2689d | balrog | /* omap1_clk.c */
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44 | c3d2689d | balrog | struct omap_mpu_state_s;
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45 | c3d2689d | balrog | typedef struct clk *omap_clk; |
46 | c3d2689d | balrog | omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); |
47 | c3d2689d | balrog | void omap_clk_init(struct omap_mpu_state_s *mpu); |
48 | c3d2689d | balrog | void omap_clk_adduser(struct clk *clk, qemu_irq user); |
49 | c3d2689d | balrog | void omap_clk_get(omap_clk clk);
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50 | c3d2689d | balrog | void omap_clk_put(omap_clk clk);
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51 | c3d2689d | balrog | void omap_clk_onoff(omap_clk clk, int on); |
52 | c3d2689d | balrog | void omap_clk_canidle(omap_clk clk, int can); |
53 | c3d2689d | balrog | void omap_clk_setrate(omap_clk clk, int divide, int multiply); |
54 | c3d2689d | balrog | int64_t omap_clk_getrate(omap_clk clk); |
55 | c3d2689d | balrog | void omap_clk_reparent(omap_clk clk, omap_clk parent);
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56 | c3d2689d | balrog | |
57 | c3d2689d | balrog | /* omap.c */
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58 | c3d2689d | balrog | struct omap_intr_handler_s;
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59 | c3d2689d | balrog | struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
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60 | c3d2689d | balrog | unsigned long size, qemu_irq parent[2], omap_clk clk); |
61 | c3d2689d | balrog | |
62 | c3d2689d | balrog | /*
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63 | c3d2689d | balrog | * Common IRQ numbers for level 1 interrupt handler
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64 | c3d2689d | balrog | * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
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65 | c3d2689d | balrog | */
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66 | c3d2689d | balrog | # define OMAP_INT_CAMERA 1 |
67 | c3d2689d | balrog | # define OMAP_INT_FIQ 3 |
68 | c3d2689d | balrog | # define OMAP_INT_RTDX 6 |
69 | c3d2689d | balrog | # define OMAP_INT_DSP_MMU_ABORT 7 |
70 | c3d2689d | balrog | # define OMAP_INT_HOST 8 |
71 | c3d2689d | balrog | # define OMAP_INT_ABORT 9 |
72 | c3d2689d | balrog | # define OMAP_INT_BRIDGE_PRIV 13 |
73 | c3d2689d | balrog | # define OMAP_INT_GPIO_BANK1 14 |
74 | c3d2689d | balrog | # define OMAP_INT_UART3 15 |
75 | c3d2689d | balrog | # define OMAP_INT_TIMER3 16 |
76 | c3d2689d | balrog | # define OMAP_INT_DMA_CH0_6 19 |
77 | c3d2689d | balrog | # define OMAP_INT_DMA_CH1_7 20 |
78 | c3d2689d | balrog | # define OMAP_INT_DMA_CH2_8 21 |
79 | c3d2689d | balrog | # define OMAP_INT_DMA_CH3 22 |
80 | c3d2689d | balrog | # define OMAP_INT_DMA_CH4 23 |
81 | c3d2689d | balrog | # define OMAP_INT_DMA_CH5 24 |
82 | c3d2689d | balrog | # define OMAP_INT_DMA_LCD 25 |
83 | c3d2689d | balrog | # define OMAP_INT_TIMER1 26 |
84 | c3d2689d | balrog | # define OMAP_INT_WD_TIMER 27 |
85 | c3d2689d | balrog | # define OMAP_INT_BRIDGE_PUB 28 |
86 | c3d2689d | balrog | # define OMAP_INT_TIMER2 30 |
87 | c3d2689d | balrog | # define OMAP_INT_LCD_CTRL 31 |
88 | c3d2689d | balrog | |
89 | c3d2689d | balrog | /*
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90 | c3d2689d | balrog | * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
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91 | c3d2689d | balrog | */
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92 | c3d2689d | balrog | # define OMAP_INT_15XX_IH2_IRQ 0 |
93 | c3d2689d | balrog | # define OMAP_INT_15XX_LB_MMU 17 |
94 | c3d2689d | balrog | # define OMAP_INT_15XX_LOCAL_BUS 29 |
95 | c3d2689d | balrog | |
96 | c3d2689d | balrog | /*
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97 | c3d2689d | balrog | * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
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98 | c3d2689d | balrog | */
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99 | c3d2689d | balrog | # define OMAP_INT_1510_SPI_TX 4 |
100 | c3d2689d | balrog | # define OMAP_INT_1510_SPI_RX 5 |
101 | c3d2689d | balrog | # define OMAP_INT_1510_DSP_MAILBOX1 10 |
102 | c3d2689d | balrog | # define OMAP_INT_1510_DSP_MAILBOX2 11 |
103 | c3d2689d | balrog | |
104 | c3d2689d | balrog | /*
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105 | c3d2689d | balrog | * OMAP-310 specific IRQ numbers for level 1 interrupt handler
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106 | c3d2689d | balrog | */
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107 | c3d2689d | balrog | # define OMAP_INT_310_McBSP2_TX 4 |
108 | c3d2689d | balrog | # define OMAP_INT_310_McBSP2_RX 5 |
109 | c3d2689d | balrog | # define OMAP_INT_310_HSB_MAILBOX1 12 |
110 | c3d2689d | balrog | # define OMAP_INT_310_HSAB_MMU 18 |
111 | c3d2689d | balrog | |
112 | c3d2689d | balrog | /*
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113 | c3d2689d | balrog | * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
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114 | c3d2689d | balrog | */
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115 | c3d2689d | balrog | # define OMAP_INT_1610_IH2_IRQ 0 |
116 | c3d2689d | balrog | # define OMAP_INT_1610_IH2_FIQ 2 |
117 | c3d2689d | balrog | # define OMAP_INT_1610_McBSP2_TX 4 |
118 | c3d2689d | balrog | # define OMAP_INT_1610_McBSP2_RX 5 |
119 | c3d2689d | balrog | # define OMAP_INT_1610_DSP_MAILBOX1 10 |
120 | c3d2689d | balrog | # define OMAP_INT_1610_DSP_MAILBOX2 11 |
121 | c3d2689d | balrog | # define OMAP_INT_1610_LCD_LINE 12 |
122 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER1 17 |
123 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER2 18 |
124 | c3d2689d | balrog | # define OMAP_INT_1610_SSR_FIFO_0 29 |
125 | c3d2689d | balrog | |
126 | c3d2689d | balrog | /*
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127 | c3d2689d | balrog | * OMAP-730 specific IRQ numbers for level 1 interrupt handler
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128 | c3d2689d | balrog | */
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129 | c3d2689d | balrog | # define OMAP_INT_730_IH2_FIQ 0 |
130 | c3d2689d | balrog | # define OMAP_INT_730_IH2_IRQ 1 |
131 | c3d2689d | balrog | # define OMAP_INT_730_USB_NON_ISO 2 |
132 | c3d2689d | balrog | # define OMAP_INT_730_USB_ISO 3 |
133 | c3d2689d | balrog | # define OMAP_INT_730_ICR 4 |
134 | c3d2689d | balrog | # define OMAP_INT_730_EAC 5 |
135 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK1 6 |
136 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK2 7 |
137 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK3 8 |
138 | c3d2689d | balrog | # define OMAP_INT_730_McBSP2TX 10 |
139 | c3d2689d | balrog | # define OMAP_INT_730_McBSP2RX 11 |
140 | c3d2689d | balrog | # define OMAP_INT_730_McBSP2RX_OVF 12 |
141 | c3d2689d | balrog | # define OMAP_INT_730_LCD_LINE 14 |
142 | c3d2689d | balrog | # define OMAP_INT_730_GSM_PROTECT 15 |
143 | c3d2689d | balrog | # define OMAP_INT_730_TIMER3 16 |
144 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK5 17 |
145 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK6 18 |
146 | c3d2689d | balrog | # define OMAP_INT_730_SPGIO_WR 29 |
147 | c3d2689d | balrog | |
148 | c3d2689d | balrog | /*
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149 | c3d2689d | balrog | * Common IRQ numbers for level 2 interrupt handler
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150 | c3d2689d | balrog | */
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151 | c3d2689d | balrog | # define OMAP_INT_KEYBOARD 1 |
152 | c3d2689d | balrog | # define OMAP_INT_uWireTX 2 |
153 | c3d2689d | balrog | # define OMAP_INT_uWireRX 3 |
154 | c3d2689d | balrog | # define OMAP_INT_I2C 4 |
155 | c3d2689d | balrog | # define OMAP_INT_MPUIO 5 |
156 | c3d2689d | balrog | # define OMAP_INT_USB_HHC_1 6 |
157 | c3d2689d | balrog | # define OMAP_INT_McBSP3TX 10 |
158 | c3d2689d | balrog | # define OMAP_INT_McBSP3RX 11 |
159 | c3d2689d | balrog | # define OMAP_INT_McBSP1TX 12 |
160 | c3d2689d | balrog | # define OMAP_INT_McBSP1RX 13 |
161 | c3d2689d | balrog | # define OMAP_INT_UART1 14 |
162 | c3d2689d | balrog | # define OMAP_INT_UART2 15 |
163 | c3d2689d | balrog | # define OMAP_INT_USB_W2FC 20 |
164 | c3d2689d | balrog | # define OMAP_INT_1WIRE 21 |
165 | c3d2689d | balrog | # define OMAP_INT_OS_TIMER 22 |
166 | b30bb3a2 | balrog | # define OMAP_INT_OQN 23 |
167 | c3d2689d | balrog | # define OMAP_INT_GAUGE_32K 24 |
168 | c3d2689d | balrog | # define OMAP_INT_RTC_TIMER 25 |
169 | c3d2689d | balrog | # define OMAP_INT_RTC_ALARM 26 |
170 | c3d2689d | balrog | # define OMAP_INT_DSP_MMU 28 |
171 | c3d2689d | balrog | |
172 | c3d2689d | balrog | /*
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173 | c3d2689d | balrog | * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
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174 | c3d2689d | balrog | */
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175 | c3d2689d | balrog | # define OMAP_INT_1510_BT_MCSI1TX 16 |
176 | c3d2689d | balrog | # define OMAP_INT_1510_BT_MCSI1RX 17 |
177 | c3d2689d | balrog | # define OMAP_INT_1510_SoSSI_MATCH 19 |
178 | c3d2689d | balrog | # define OMAP_INT_1510_MEM_STICK 27 |
179 | c3d2689d | balrog | # define OMAP_INT_1510_COM_SPI_RO 31 |
180 | c3d2689d | balrog | |
181 | c3d2689d | balrog | /*
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182 | c3d2689d | balrog | * OMAP-310 specific IRQ numbers for level 2 interrupt handler
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183 | c3d2689d | balrog | */
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184 | c3d2689d | balrog | # define OMAP_INT_310_FAC 0 |
185 | c3d2689d | balrog | # define OMAP_INT_310_USB_HHC_2 7 |
186 | c3d2689d | balrog | # define OMAP_INT_310_MCSI1_FE 16 |
187 | c3d2689d | balrog | # define OMAP_INT_310_MCSI2_FE 17 |
188 | c3d2689d | balrog | # define OMAP_INT_310_USB_W2FC_ISO 29 |
189 | c3d2689d | balrog | # define OMAP_INT_310_USB_W2FC_NON_ISO 30 |
190 | c3d2689d | balrog | # define OMAP_INT_310_McBSP2RX_OF 31 |
191 | c3d2689d | balrog | |
192 | c3d2689d | balrog | /*
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193 | c3d2689d | balrog | * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
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194 | c3d2689d | balrog | */
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195 | c3d2689d | balrog | # define OMAP_INT_1610_FAC 0 |
196 | c3d2689d | balrog | # define OMAP_INT_1610_USB_HHC_2 7 |
197 | c3d2689d | balrog | # define OMAP_INT_1610_USB_OTG 8 |
198 | c3d2689d | balrog | # define OMAP_INT_1610_SoSSI 9 |
199 | c3d2689d | balrog | # define OMAP_INT_1610_BT_MCSI1TX 16 |
200 | c3d2689d | balrog | # define OMAP_INT_1610_BT_MCSI1RX 17 |
201 | c3d2689d | balrog | # define OMAP_INT_1610_SoSSI_MATCH 19 |
202 | c3d2689d | balrog | # define OMAP_INT_1610_MEM_STICK 27 |
203 | c3d2689d | balrog | # define OMAP_INT_1610_McBSP2RX_OF 31 |
204 | c3d2689d | balrog | # define OMAP_INT_1610_STI 32 |
205 | c3d2689d | balrog | # define OMAP_INT_1610_STI_WAKEUP 33 |
206 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER3 34 |
207 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER4 35 |
208 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER5 36 |
209 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER6 37 |
210 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER7 38 |
211 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER8 39 |
212 | c3d2689d | balrog | # define OMAP_INT_1610_GPIO_BANK2 40 |
213 | c3d2689d | balrog | # define OMAP_INT_1610_GPIO_BANK3 41 |
214 | c3d2689d | balrog | # define OMAP_INT_1610_MMC2 42 |
215 | c3d2689d | balrog | # define OMAP_INT_1610_CF 43 |
216 | c3d2689d | balrog | # define OMAP_INT_1610_WAKE_UP_REQ 46 |
217 | c3d2689d | balrog | # define OMAP_INT_1610_GPIO_BANK4 48 |
218 | c3d2689d | balrog | # define OMAP_INT_1610_SPI 49 |
219 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH6 53 |
220 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH7 54 |
221 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH8 55 |
222 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH9 56 |
223 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH10 57 |
224 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH11 58 |
225 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH12 59 |
226 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH13 60 |
227 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH14 61 |
228 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH15 62 |
229 | c3d2689d | balrog | # define OMAP_INT_1610_NAND 63 |
230 | c3d2689d | balrog | |
231 | c3d2689d | balrog | /*
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232 | c3d2689d | balrog | * OMAP-730 specific IRQ numbers for level 2 interrupt handler
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233 | c3d2689d | balrog | */
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234 | c3d2689d | balrog | # define OMAP_INT_730_HW_ERRORS 0 |
235 | c3d2689d | balrog | # define OMAP_INT_730_NFIQ_PWR_FAIL 1 |
236 | c3d2689d | balrog | # define OMAP_INT_730_CFCD 2 |
237 | c3d2689d | balrog | # define OMAP_INT_730_CFIREQ 3 |
238 | c3d2689d | balrog | # define OMAP_INT_730_I2C 4 |
239 | c3d2689d | balrog | # define OMAP_INT_730_PCC 5 |
240 | c3d2689d | balrog | # define OMAP_INT_730_MPU_EXT_NIRQ 6 |
241 | c3d2689d | balrog | # define OMAP_INT_730_SPI_100K_1 7 |
242 | c3d2689d | balrog | # define OMAP_INT_730_SYREN_SPI 8 |
243 | c3d2689d | balrog | # define OMAP_INT_730_VLYNQ 9 |
244 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK4 10 |
245 | c3d2689d | balrog | # define OMAP_INT_730_McBSP1TX 11 |
246 | c3d2689d | balrog | # define OMAP_INT_730_McBSP1RX 12 |
247 | c3d2689d | balrog | # define OMAP_INT_730_McBSP1RX_OF 13 |
248 | c3d2689d | balrog | # define OMAP_INT_730_UART_MODEM_IRDA_2 14 |
249 | c3d2689d | balrog | # define OMAP_INT_730_UART_MODEM_1 15 |
250 | c3d2689d | balrog | # define OMAP_INT_730_MCSI 16 |
251 | c3d2689d | balrog | # define OMAP_INT_730_uWireTX 17 |
252 | c3d2689d | balrog | # define OMAP_INT_730_uWireRX 18 |
253 | c3d2689d | balrog | # define OMAP_INT_730_SMC_CD 19 |
254 | c3d2689d | balrog | # define OMAP_INT_730_SMC_IREQ 20 |
255 | c3d2689d | balrog | # define OMAP_INT_730_HDQ_1WIRE 21 |
256 | c3d2689d | balrog | # define OMAP_INT_730_TIMER32K 22 |
257 | c3d2689d | balrog | # define OMAP_INT_730_MMC_SDIO 23 |
258 | c3d2689d | balrog | # define OMAP_INT_730_UPLD 24 |
259 | c3d2689d | balrog | # define OMAP_INT_730_USB_HHC_1 27 |
260 | c3d2689d | balrog | # define OMAP_INT_730_USB_HHC_2 28 |
261 | c3d2689d | balrog | # define OMAP_INT_730_USB_GENI 29 |
262 | c3d2689d | balrog | # define OMAP_INT_730_USB_OTG 30 |
263 | c3d2689d | balrog | # define OMAP_INT_730_CAMERA_IF 31 |
264 | c3d2689d | balrog | # define OMAP_INT_730_RNG 32 |
265 | c3d2689d | balrog | # define OMAP_INT_730_DUAL_MODE_TIMER 33 |
266 | c3d2689d | balrog | # define OMAP_INT_730_DBB_RF_EN 34 |
267 | c3d2689d | balrog | # define OMAP_INT_730_MPUIO_KEYPAD 35 |
268 | c3d2689d | balrog | # define OMAP_INT_730_SHA1_MD5 36 |
269 | c3d2689d | balrog | # define OMAP_INT_730_SPI_100K_2 37 |
270 | c3d2689d | balrog | # define OMAP_INT_730_RNG_IDLE 38 |
271 | c3d2689d | balrog | # define OMAP_INT_730_MPUIO 39 |
272 | c3d2689d | balrog | # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 |
273 | c3d2689d | balrog | # define OMAP_INT_730_LLPC_OE_FALLING 41 |
274 | c3d2689d | balrog | # define OMAP_INT_730_LLPC_OE_RISING 42 |
275 | c3d2689d | balrog | # define OMAP_INT_730_LLPC_VSYNC 43 |
276 | c3d2689d | balrog | # define OMAP_INT_730_WAKE_UP_REQ 46 |
277 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH6 53 |
278 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH7 54 |
279 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH8 55 |
280 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH9 56 |
281 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH10 57 |
282 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH11 58 |
283 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH12 59 |
284 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH13 60 |
285 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH14 61 |
286 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH15 62 |
287 | c3d2689d | balrog | # define OMAP_INT_730_NAND 63 |
288 | c3d2689d | balrog | |
289 | c3d2689d | balrog | /*
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290 | c3d2689d | balrog | * OMAP-24xx common IRQ numbers
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291 | c3d2689d | balrog | */
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292 | c3d2689d | balrog | # define OMAP_INT_24XX_SYS_NIRQ 7 |
293 | c3d2689d | balrog | # define OMAP_INT_24XX_SDMA_IRQ0 12 |
294 | c3d2689d | balrog | # define OMAP_INT_24XX_SDMA_IRQ1 13 |
295 | c3d2689d | balrog | # define OMAP_INT_24XX_SDMA_IRQ2 14 |
296 | c3d2689d | balrog | # define OMAP_INT_24XX_SDMA_IRQ3 15 |
297 | c3d2689d | balrog | # define OMAP_INT_24XX_CAM_IRQ 24 |
298 | c3d2689d | balrog | # define OMAP_INT_24XX_DSS_IRQ 25 |
299 | c3d2689d | balrog | # define OMAP_INT_24XX_MAIL_U0_MPU 26 |
300 | c3d2689d | balrog | # define OMAP_INT_24XX_DSP_UMA 27 |
301 | c3d2689d | balrog | # define OMAP_INT_24XX_DSP_MMU 28 |
302 | c3d2689d | balrog | # define OMAP_INT_24XX_GPIO_BANK1 29 |
303 | c3d2689d | balrog | # define OMAP_INT_24XX_GPIO_BANK2 30 |
304 | c3d2689d | balrog | # define OMAP_INT_24XX_GPIO_BANK3 31 |
305 | c3d2689d | balrog | # define OMAP_INT_24XX_GPIO_BANK4 32 |
306 | c3d2689d | balrog | # define OMAP_INT_24XX_GPIO_BANK5 33 |
307 | c3d2689d | balrog | # define OMAP_INT_24XX_MAIL_U3_MPU 34 |
308 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER1 37 |
309 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER2 38 |
310 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER3 39 |
311 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER4 40 |
312 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER5 41 |
313 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER6 42 |
314 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER7 43 |
315 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER8 44 |
316 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER9 45 |
317 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER10 46 |
318 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER11 47 |
319 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER12 48 |
320 | c3d2689d | balrog | # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59 |
321 | c3d2689d | balrog | # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60 |
322 | c3d2689d | balrog | # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62 |
323 | c3d2689d | balrog | # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63 |
324 | c3d2689d | balrog | # define OMAP_INT_24XX_UART1_IRQ 72 |
325 | c3d2689d | balrog | # define OMAP_INT_24XX_UART2_IRQ 73 |
326 | c3d2689d | balrog | # define OMAP_INT_24XX_UART3_IRQ 74 |
327 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_GEN 75 |
328 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_NISO 76 |
329 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_ISO 77 |
330 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_HGEN 78 |
331 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_HSOF 79 |
332 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_OTG 80 |
333 | c3d2689d | balrog | # define OMAP_INT_24XX_MMC_IRQ 83 |
334 | c3d2689d | balrog | # define OMAP_INT_243X_HS_USB_MC 92 |
335 | c3d2689d | balrog | # define OMAP_INT_243X_HS_USB_DMA 93 |
336 | c3d2689d | balrog | # define OMAP_INT_243X_CARKIT 94 |
337 | c3d2689d | balrog | |
338 | c3d2689d | balrog | struct omap_dma_s;
|
339 | c3d2689d | balrog | struct omap_dma_s *omap_dma_init(target_phys_addr_t base,
|
340 | c3d2689d | balrog | qemu_irq pic[], struct omap_mpu_state_s *mpu, omap_clk clk);
|
341 | c3d2689d | balrog | |
342 | c3d2689d | balrog | enum omap_dma_port {
|
343 | c3d2689d | balrog | emiff = 0,
|
344 | c3d2689d | balrog | emifs, |
345 | c3d2689d | balrog | imif, |
346 | c3d2689d | balrog | tipb, |
347 | c3d2689d | balrog | local, |
348 | c3d2689d | balrog | tipb_mpui, |
349 | c3d2689d | balrog | omap_dma_port_last, |
350 | c3d2689d | balrog | }; |
351 | c3d2689d | balrog | |
352 | c3d2689d | balrog | struct omap_dma_lcd_channel_s {
|
353 | c3d2689d | balrog | enum omap_dma_port src;
|
354 | c3d2689d | balrog | target_phys_addr_t src_f1_top; |
355 | c3d2689d | balrog | target_phys_addr_t src_f1_bottom; |
356 | c3d2689d | balrog | target_phys_addr_t src_f2_top; |
357 | c3d2689d | balrog | target_phys_addr_t src_f2_bottom; |
358 | c3d2689d | balrog | /* Destination port is fixed. */
|
359 | c3d2689d | balrog | int interrupts;
|
360 | c3d2689d | balrog | int condition;
|
361 | c3d2689d | balrog | int dual;
|
362 | c3d2689d | balrog | |
363 | c3d2689d | balrog | int current_frame;
|
364 | c3d2689d | balrog | ram_addr_t phys_framebuffer[2];
|
365 | c3d2689d | balrog | qemu_irq irq; |
366 | c3d2689d | balrog | struct omap_mpu_state_s *mpu;
|
367 | c3d2689d | balrog | }; |
368 | c3d2689d | balrog | |
369 | c3d2689d | balrog | /*
|
370 | c3d2689d | balrog | * DMA request numbers for OMAP1
|
371 | c3d2689d | balrog | * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
|
372 | c3d2689d | balrog | */
|
373 | c3d2689d | balrog | # define OMAP_DMA_NO_DEVICE 0 |
374 | c3d2689d | balrog | # define OMAP_DMA_MCSI1_TX 1 |
375 | c3d2689d | balrog | # define OMAP_DMA_MCSI1_RX 2 |
376 | c3d2689d | balrog | # define OMAP_DMA_I2C_RX 3 |
377 | c3d2689d | balrog | # define OMAP_DMA_I2C_TX 4 |
378 | c3d2689d | balrog | # define OMAP_DMA_EXT_NDMA_REQ0 5 |
379 | c3d2689d | balrog | # define OMAP_DMA_EXT_NDMA_REQ1 6 |
380 | c3d2689d | balrog | # define OMAP_DMA_UWIRE_TX 7 |
381 | c3d2689d | balrog | # define OMAP_DMA_MCBSP1_TX 8 |
382 | c3d2689d | balrog | # define OMAP_DMA_MCBSP1_RX 9 |
383 | c3d2689d | balrog | # define OMAP_DMA_MCBSP3_TX 10 |
384 | c3d2689d | balrog | # define OMAP_DMA_MCBSP3_RX 11 |
385 | c3d2689d | balrog | # define OMAP_DMA_UART1_TX 12 |
386 | c3d2689d | balrog | # define OMAP_DMA_UART1_RX 13 |
387 | c3d2689d | balrog | # define OMAP_DMA_UART2_TX 14 |
388 | c3d2689d | balrog | # define OMAP_DMA_UART2_RX 15 |
389 | c3d2689d | balrog | # define OMAP_DMA_MCBSP2_TX 16 |
390 | c3d2689d | balrog | # define OMAP_DMA_MCBSP2_RX 17 |
391 | c3d2689d | balrog | # define OMAP_DMA_UART3_TX 18 |
392 | c3d2689d | balrog | # define OMAP_DMA_UART3_RX 19 |
393 | c3d2689d | balrog | # define OMAP_DMA_CAMERA_IF_RX 20 |
394 | c3d2689d | balrog | # define OMAP_DMA_MMC_TX 21 |
395 | c3d2689d | balrog | # define OMAP_DMA_MMC_RX 22 |
396 | c3d2689d | balrog | # define OMAP_DMA_NAND 23 /* Not in OMAP310 */ |
397 | c3d2689d | balrog | # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ |
398 | c3d2689d | balrog | # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ |
399 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_RX0 26 |
400 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_RX1 27 |
401 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_RX2 28 |
402 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_TX0 29 |
403 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_TX1 30 |
404 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_TX2 31 |
405 | c3d2689d | balrog | |
406 | c3d2689d | balrog | /* These are only for 1610 */
|
407 | c3d2689d | balrog | # define OMAP_DMA_CRYPTO_DES_IN 32 |
408 | c3d2689d | balrog | # define OMAP_DMA_SPI_TX 33 |
409 | c3d2689d | balrog | # define OMAP_DMA_SPI_RX 34 |
410 | c3d2689d | balrog | # define OMAP_DMA_CRYPTO_HASH 35 |
411 | c3d2689d | balrog | # define OMAP_DMA_CCP_ATTN 36 |
412 | c3d2689d | balrog | # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 |
413 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_0 38 |
414 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_0 39 |
415 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_1 40 |
416 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_1 41 |
417 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_2 42 |
418 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_2 43 |
419 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_3 44 |
420 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_3 45 |
421 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_4 46 |
422 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_4 47 |
423 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_5 48 |
424 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_5 49 |
425 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_6 50 |
426 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_6 51 |
427 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_7 52 |
428 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_7 53 |
429 | c3d2689d | balrog | # define OMAP_DMA_MMC2_TX 54 |
430 | c3d2689d | balrog | # define OMAP_DMA_MMC2_RX 55 |
431 | c3d2689d | balrog | # define OMAP_DMA_CRYPTO_DES_OUT 56 |
432 | c3d2689d | balrog | |
433 | c3d2689d | balrog | struct omap_mpu_timer_s;
|
434 | c3d2689d | balrog | struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
|
435 | c3d2689d | balrog | qemu_irq irq, omap_clk clk); |
436 | c3d2689d | balrog | |
437 | c3d2689d | balrog | struct omap_watchdog_timer_s;
|
438 | c3d2689d | balrog | struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
|
439 | c3d2689d | balrog | qemu_irq irq, omap_clk clk); |
440 | c3d2689d | balrog | |
441 | c3d2689d | balrog | struct omap_32khz_timer_s;
|
442 | c3d2689d | balrog | struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
|
443 | c3d2689d | balrog | qemu_irq irq, omap_clk clk); |
444 | c3d2689d | balrog | |
445 | c3d2689d | balrog | struct omap_tipb_bridge_s;
|
446 | c3d2689d | balrog | struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
|
447 | c3d2689d | balrog | qemu_irq abort_irq, omap_clk clk); |
448 | c3d2689d | balrog | |
449 | c3d2689d | balrog | struct omap_uart_s;
|
450 | c3d2689d | balrog | struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
|
451 | c3d2689d | balrog | qemu_irq irq, omap_clk clk, CharDriverState *chr); |
452 | c3d2689d | balrog | |
453 | fe71e81a | balrog | struct omap_mpuio_s;
|
454 | fe71e81a | balrog | struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
|
455 | fe71e81a | balrog | qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, |
456 | fe71e81a | balrog | omap_clk clk); |
457 | fe71e81a | balrog | qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
|
458 | fe71e81a | balrog | void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); |
459 | fe71e81a | balrog | void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); |
460 | fe71e81a | balrog | |
461 | 64330148 | balrog | struct omap_gpio_s;
|
462 | 64330148 | balrog | struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
|
463 | 64330148 | balrog | qemu_irq irq, omap_clk clk); |
464 | 64330148 | balrog | qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s);
|
465 | 64330148 | balrog | void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler); |
466 | 64330148 | balrog | |
467 | d951f6ff | balrog | struct uwire_slave_s {
|
468 | d951f6ff | balrog | uint16_t (*receive)(void *opaque);
|
469 | d951f6ff | balrog | void (*send)(void *opaque, uint16_t data); |
470 | d951f6ff | balrog | void *opaque;
|
471 | d951f6ff | balrog | }; |
472 | d951f6ff | balrog | struct omap_uwire_s;
|
473 | d951f6ff | balrog | struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
|
474 | d951f6ff | balrog | qemu_irq *irq, qemu_irq dma, omap_clk clk); |
475 | d951f6ff | balrog | void omap_uwire_attach(struct omap_uwire_s *s, |
476 | d951f6ff | balrog | struct uwire_slave_s *slave, int chipselect); |
477 | d951f6ff | balrog | |
478 | 5c1c390f | balrog | struct omap_rtc_s;
|
479 | 5c1c390f | balrog | struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
|
480 | 5c1c390f | balrog | qemu_irq *irq, omap_clk clk); |
481 | 5c1c390f | balrog | |
482 | d8f699cb | balrog | struct i2s_codec_s {
|
483 | d8f699cb | balrog | void *opaque;
|
484 | d8f699cb | balrog | |
485 | d8f699cb | balrog | /* The CPU can call this if it is generating the clock signal on the
|
486 | d8f699cb | balrog | * i2s port. The CODEC can ignore it if it is set up as a clock
|
487 | d8f699cb | balrog | * master and generates its own clock. */
|
488 | d8f699cb | balrog | void (*set_rate)(void *opaque, int in, int out); |
489 | d8f699cb | balrog | |
490 | d8f699cb | balrog | void (*tx_swallow)(void *opaque); |
491 | d8f699cb | balrog | qemu_irq rx_swallow; |
492 | d8f699cb | balrog | qemu_irq tx_start; |
493 | d8f699cb | balrog | |
494 | d8f699cb | balrog | struct i2s_fifo_s {
|
495 | d8f699cb | balrog | uint8_t *fifo; |
496 | d8f699cb | balrog | int len;
|
497 | d8f699cb | balrog | int start;
|
498 | d8f699cb | balrog | int size;
|
499 | d8f699cb | balrog | } in, out; |
500 | d8f699cb | balrog | }; |
501 | d8f699cb | balrog | struct omap_mcbsp_s;
|
502 | d8f699cb | balrog | struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
|
503 | d8f699cb | balrog | qemu_irq *irq, qemu_irq *dma, omap_clk clk); |
504 | d8f699cb | balrog | void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave); |
505 | d8f699cb | balrog | |
506 | c3d2689d | balrog | /* omap_lcdc.c */
|
507 | c3d2689d | balrog | struct omap_lcd_panel_s;
|
508 | c3d2689d | balrog | void omap_lcdc_reset(struct omap_lcd_panel_s *s); |
509 | c3d2689d | balrog | struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
|
510 | c3d2689d | balrog | struct omap_dma_lcd_channel_s *dma, DisplayState *ds,
|
511 | c3d2689d | balrog | ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk); |
512 | c3d2689d | balrog | |
513 | b30bb3a2 | balrog | /* omap_mmc.c */
|
514 | b30bb3a2 | balrog | struct omap_mmc_s;
|
515 | b30bb3a2 | balrog | struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
|
516 | 87ecb68b | pbrook | BlockDriverState *bd, |
517 | b30bb3a2 | balrog | qemu_irq irq, qemu_irq dma[], omap_clk clk); |
518 | b30bb3a2 | balrog | void omap_mmc_reset(struct omap_mmc_s *s); |
519 | 8e129e07 | balrog | void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); |
520 | b30bb3a2 | balrog | |
521 | 02645926 | balrog | /* omap_i2c.c */
|
522 | 02645926 | balrog | struct omap_i2c_s;
|
523 | 02645926 | balrog | struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
|
524 | 02645926 | balrog | qemu_irq irq, qemu_irq *dma, omap_clk clk); |
525 | 02645926 | balrog | void omap_i2c_reset(struct omap_i2c_s *s); |
526 | 02645926 | balrog | i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
|
527 | 02645926 | balrog | |
528 | c3d2689d | balrog | # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
|
529 | c3d2689d | balrog | # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
|
530 | c3d2689d | balrog | # define cpu_is_omap15xx(cpu) \
|
531 | c3d2689d | balrog | (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) |
532 | c3d2689d | balrog | # define cpu_class_omap1(cpu) 1 |
533 | c3d2689d | balrog | |
534 | c3d2689d | balrog | struct omap_mpu_state_s {
|
535 | c3d2689d | balrog | enum omap1_mpu_model {
|
536 | c3d2689d | balrog | omap310, |
537 | c3d2689d | balrog | omap1510, |
538 | c3d2689d | balrog | } mpu_model; |
539 | c3d2689d | balrog | |
540 | c3d2689d | balrog | CPUState *env; |
541 | c3d2689d | balrog | |
542 | c3d2689d | balrog | qemu_irq *irq[2];
|
543 | c3d2689d | balrog | qemu_irq *drq; |
544 | c3d2689d | balrog | |
545 | c3d2689d | balrog | qemu_irq wakeup; |
546 | c3d2689d | balrog | |
547 | c3d2689d | balrog | struct omap_dma_port_if_s {
|
548 | 5fafdf24 | ths | uint32_t (*read[3])(struct omap_mpu_state_s *s, |
549 | c3d2689d | balrog | target_phys_addr_t offset); |
550 | c3d2689d | balrog | void (*write[3])(struct omap_mpu_state_s *s, |
551 | c3d2689d | balrog | target_phys_addr_t offset, uint32_t value); |
552 | c3d2689d | balrog | int (*addr_valid)(struct omap_mpu_state_s *s, |
553 | c3d2689d | balrog | target_phys_addr_t addr); |
554 | c3d2689d | balrog | } port[omap_dma_port_last]; |
555 | c3d2689d | balrog | |
556 | c3d2689d | balrog | unsigned long sdram_size; |
557 | c3d2689d | balrog | unsigned long sram_size; |
558 | c3d2689d | balrog | |
559 | c3d2689d | balrog | /* MPUI-TIPB peripherals */
|
560 | d951f6ff | balrog | struct omap_uart_s *uart[3]; |
561 | d951f6ff | balrog | |
562 | d951f6ff | balrog | struct omap_gpio_s *gpio;
|
563 | c3d2689d | balrog | |
564 | d8f699cb | balrog | struct omap_mcbsp_s *mcbsp1;
|
565 | d8f699cb | balrog | struct omap_mcbsp_s *mcbsp3;
|
566 | d8f699cb | balrog | |
567 | c3d2689d | balrog | /* MPU public TIPB peripherals */
|
568 | c3d2689d | balrog | struct omap_32khz_timer_s *os_timer;
|
569 | c3d2689d | balrog | |
570 | b30bb3a2 | balrog | struct omap_mmc_s *mmc;
|
571 | b30bb3a2 | balrog | |
572 | d951f6ff | balrog | struct omap_mpuio_s *mpuio;
|
573 | d951f6ff | balrog | |
574 | d951f6ff | balrog | struct omap_uwire_s *microwire;
|
575 | d951f6ff | balrog | |
576 | 66450b15 | balrog | struct {
|
577 | 66450b15 | balrog | uint8_t output; |
578 | 66450b15 | balrog | uint8_t level; |
579 | 66450b15 | balrog | uint8_t enable; |
580 | 66450b15 | balrog | int clk;
|
581 | 66450b15 | balrog | } pwl; |
582 | 66450b15 | balrog | |
583 | f34c417b | balrog | struct {
|
584 | f34c417b | balrog | uint8_t frc; |
585 | f34c417b | balrog | uint8_t vrc; |
586 | f34c417b | balrog | uint8_t gcr; |
587 | f34c417b | balrog | omap_clk clk; |
588 | f34c417b | balrog | } pwt; |
589 | f34c417b | balrog | |
590 | 4a2c8ac2 | balrog | struct omap_i2c_s *i2c;
|
591 | 4a2c8ac2 | balrog | |
592 | 02645926 | balrog | struct omap_rtc_s *rtc;
|
593 | 02645926 | balrog | |
594 | d8f699cb | balrog | struct omap_mcbsp_s *mcbsp2;
|
595 | d8f699cb | balrog | |
596 | c3d2689d | balrog | /* MPU private TIPB peripherals */
|
597 | c3d2689d | balrog | struct omap_intr_handler_s *ih[2]; |
598 | c3d2689d | balrog | |
599 | c3d2689d | balrog | struct omap_dma_s *dma;
|
600 | c3d2689d | balrog | |
601 | c3d2689d | balrog | struct omap_mpu_timer_s *timer[3]; |
602 | c3d2689d | balrog | struct omap_watchdog_timer_s *wdt;
|
603 | c3d2689d | balrog | |
604 | c3d2689d | balrog | struct omap_lcd_panel_s *lcd;
|
605 | c3d2689d | balrog | |
606 | c3d2689d | balrog | target_phys_addr_t ulpd_pm_base; |
607 | c3d2689d | balrog | uint32_t ulpd_pm_regs[21];
|
608 | c3d2689d | balrog | int64_t ulpd_gauge_start; |
609 | c3d2689d | balrog | |
610 | c3d2689d | balrog | target_phys_addr_t pin_cfg_base; |
611 | c3d2689d | balrog | uint32_t func_mux_ctrl[14];
|
612 | c3d2689d | balrog | uint32_t comp_mode_ctrl[1];
|
613 | c3d2689d | balrog | uint32_t pull_dwn_ctrl[4];
|
614 | c3d2689d | balrog | uint32_t gate_inh_ctrl[1];
|
615 | c3d2689d | balrog | uint32_t voltage_ctrl[1];
|
616 | c3d2689d | balrog | uint32_t test_dbg_ctrl[1];
|
617 | c3d2689d | balrog | uint32_t mod_conf_ctrl[1];
|
618 | c3d2689d | balrog | int compat1509;
|
619 | c3d2689d | balrog | |
620 | c3d2689d | balrog | uint32_t mpui_ctrl; |
621 | c3d2689d | balrog | target_phys_addr_t mpui_base; |
622 | c3d2689d | balrog | |
623 | c3d2689d | balrog | struct omap_tipb_bridge_s *private_tipb;
|
624 | c3d2689d | balrog | struct omap_tipb_bridge_s *public_tipb;
|
625 | c3d2689d | balrog | |
626 | c3d2689d | balrog | target_phys_addr_t tcmi_base; |
627 | c3d2689d | balrog | uint32_t tcmi_regs[17];
|
628 | c3d2689d | balrog | |
629 | c3d2689d | balrog | struct dpll_ctl_s {
|
630 | c3d2689d | balrog | target_phys_addr_t base; |
631 | c3d2689d | balrog | uint16_t mode; |
632 | c3d2689d | balrog | omap_clk dpll; |
633 | c3d2689d | balrog | } dpll[3];
|
634 | c3d2689d | balrog | |
635 | c3d2689d | balrog | omap_clk clks; |
636 | c3d2689d | balrog | struct {
|
637 | c3d2689d | balrog | target_phys_addr_t mpu_base; |
638 | c3d2689d | balrog | target_phys_addr_t dsp_base; |
639 | c3d2689d | balrog | |
640 | c3d2689d | balrog | int cold_start;
|
641 | c3d2689d | balrog | int clocking_scheme;
|
642 | c3d2689d | balrog | uint16_t arm_ckctl; |
643 | c3d2689d | balrog | uint16_t arm_idlect1; |
644 | c3d2689d | balrog | uint16_t arm_idlect2; |
645 | c3d2689d | balrog | uint16_t arm_ewupct; |
646 | c3d2689d | balrog | uint16_t arm_rstct1; |
647 | c3d2689d | balrog | uint16_t arm_rstct2; |
648 | c3d2689d | balrog | uint16_t arm_ckout1; |
649 | c3d2689d | balrog | int dpll1_mode;
|
650 | c3d2689d | balrog | uint16_t dsp_idlect1; |
651 | c3d2689d | balrog | uint16_t dsp_idlect2; |
652 | c3d2689d | balrog | uint16_t dsp_rstct2; |
653 | c3d2689d | balrog | } clkm; |
654 | c3d2689d | balrog | } *omap310_mpu_init(unsigned long sdram_size, |
655 | c3d2689d | balrog | DisplayState *ds, const char *core); |
656 | c3d2689d | balrog | |
657 | c3d2689d | balrog | # if TARGET_PHYS_ADDR_BITS == 32 |
658 | c3d2689d | balrog | # define OMAP_FMT_plx "%#08x" |
659 | c3d2689d | balrog | # elif TARGET_PHYS_ADDR_BITS == 64 |
660 | c3d2689d | balrog | # define OMAP_FMT_plx "%#08" PRIx64 |
661 | c3d2689d | balrog | # else
|
662 | c3d2689d | balrog | # error TARGET_PHYS_ADDR_BITS undefined
|
663 | c3d2689d | balrog | # endif
|
664 | c3d2689d | balrog | |
665 | b30bb3a2 | balrog | uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
|
666 | b30bb3a2 | balrog | void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, |
667 | b30bb3a2 | balrog | uint32_t value); |
668 | b30bb3a2 | balrog | uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
|
669 | b30bb3a2 | balrog | void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, |
670 | b30bb3a2 | balrog | uint32_t value); |
671 | b30bb3a2 | balrog | |
672 | c3d2689d | balrog | # define OMAP_BAD_REG(paddr) \
|
673 | c3d2689d | balrog | printf("%s: Bad register " OMAP_FMT_plx "\n", __FUNCTION__, paddr) |
674 | c3d2689d | balrog | # define OMAP_RO_REG(paddr) \
|
675 | c3d2689d | balrog | printf("%s: Read-only register " OMAP_FMT_plx "\n", \ |
676 | c3d2689d | balrog | __FUNCTION__, paddr) |
677 | b854bc19 | balrog | |
678 | b854bc19 | balrog | # define TCMI_VERBOSE 1 |
679 | d8f699cb | balrog | //# define MEM_VERBOSE 1
|
680 | b854bc19 | balrog | |
681 | b854bc19 | balrog | # ifdef TCMI_VERBOSE
|
682 | b854bc19 | balrog | # define OMAP_8B_REG(paddr) \
|
683 | 66450b15 | balrog | printf("%s: 8-bit register " OMAP_FMT_plx "\n", \ |
684 | 66450b15 | balrog | __FUNCTION__, paddr) |
685 | b854bc19 | balrog | # define OMAP_16B_REG(paddr) \
|
686 | c3d2689d | balrog | printf("%s: 16-bit register " OMAP_FMT_plx "\n", \ |
687 | c3d2689d | balrog | __FUNCTION__, paddr) |
688 | b854bc19 | balrog | # define OMAP_32B_REG(paddr) \
|
689 | c3d2689d | balrog | printf("%s: 32-bit register " OMAP_FMT_plx "\n", \ |
690 | c3d2689d | balrog | __FUNCTION__, paddr) |
691 | b854bc19 | balrog | # else
|
692 | b854bc19 | balrog | # define OMAP_8B_REG(paddr)
|
693 | b854bc19 | balrog | # define OMAP_16B_REG(paddr)
|
694 | b854bc19 | balrog | # define OMAP_32B_REG(paddr)
|
695 | b854bc19 | balrog | # endif
|
696 | c3d2689d | balrog | |
697 | cf965d24 | balrog | # define OMAP_MPUI_REG_MASK 0x000007ff |
698 | cf965d24 | balrog | |
699 | d8f699cb | balrog | # ifdef MEM_VERBOSE
|
700 | d8f699cb | balrog | struct io_fn {
|
701 | d8f699cb | balrog | CPUReadMemoryFunc **mem_read; |
702 | d8f699cb | balrog | CPUWriteMemoryFunc **mem_write; |
703 | d8f699cb | balrog | void *opaque;
|
704 | d8f699cb | balrog | int in;
|
705 | d8f699cb | balrog | }; |
706 | d8f699cb | balrog | |
707 | d8f699cb | balrog | static uint32_t io_readb(void *opaque, target_phys_addr_t addr) |
708 | d8f699cb | balrog | { |
709 | d8f699cb | balrog | struct io_fn *s = opaque;
|
710 | d8f699cb | balrog | uint32_t ret; |
711 | d8f699cb | balrog | |
712 | d8f699cb | balrog | s->in ++; |
713 | d8f699cb | balrog | ret = s->mem_read[0](s->opaque, addr);
|
714 | d8f699cb | balrog | s->in --; |
715 | d8f699cb | balrog | if (!s->in)
|
716 | d8f699cb | balrog | fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
|
717 | d8f699cb | balrog | return ret;
|
718 | d8f699cb | balrog | } |
719 | d8f699cb | balrog | static uint32_t io_readh(void *opaque, target_phys_addr_t addr) |
720 | d8f699cb | balrog | { |
721 | d8f699cb | balrog | struct io_fn *s = opaque;
|
722 | d8f699cb | balrog | uint32_t ret; |
723 | d8f699cb | balrog | |
724 | d8f699cb | balrog | s->in ++; |
725 | d8f699cb | balrog | ret = s->mem_read[1](s->opaque, addr);
|
726 | d8f699cb | balrog | s->in --; |
727 | d8f699cb | balrog | if (!s->in)
|
728 | d8f699cb | balrog | fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
|
729 | d8f699cb | balrog | return ret;
|
730 | d8f699cb | balrog | } |
731 | d8f699cb | balrog | static uint32_t io_readw(void *opaque, target_phys_addr_t addr) |
732 | d8f699cb | balrog | { |
733 | d8f699cb | balrog | struct io_fn *s = opaque;
|
734 | d8f699cb | balrog | uint32_t ret; |
735 | d8f699cb | balrog | |
736 | d8f699cb | balrog | s->in ++; |
737 | d8f699cb | balrog | ret = s->mem_read[2](s->opaque, addr);
|
738 | d8f699cb | balrog | s->in --; |
739 | d8f699cb | balrog | if (!s->in)
|
740 | d8f699cb | balrog | fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
|
741 | d8f699cb | balrog | return ret;
|
742 | d8f699cb | balrog | } |
743 | d8f699cb | balrog | static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) |
744 | d8f699cb | balrog | { |
745 | d8f699cb | balrog | struct io_fn *s = opaque;
|
746 | d8f699cb | balrog | |
747 | d8f699cb | balrog | if (!s->in)
|
748 | d8f699cb | balrog | fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);
|
749 | d8f699cb | balrog | s->in ++; |
750 | d8f699cb | balrog | s->mem_write[0](s->opaque, addr, value);
|
751 | d8f699cb | balrog | s->in --; |
752 | d8f699cb | balrog | } |
753 | d8f699cb | balrog | static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value) |
754 | d8f699cb | balrog | { |
755 | d8f699cb | balrog | struct io_fn *s = opaque;
|
756 | d8f699cb | balrog | |
757 | d8f699cb | balrog | if (!s->in)
|
758 | d8f699cb | balrog | fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);
|
759 | d8f699cb | balrog | s->in ++; |
760 | d8f699cb | balrog | s->mem_write[1](s->opaque, addr, value);
|
761 | d8f699cb | balrog | s->in --; |
762 | d8f699cb | balrog | } |
763 | d8f699cb | balrog | static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value) |
764 | d8f699cb | balrog | { |
765 | d8f699cb | balrog | struct io_fn *s = opaque;
|
766 | d8f699cb | balrog | |
767 | d8f699cb | balrog | if (!s->in)
|
768 | d8f699cb | balrog | fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);
|
769 | d8f699cb | balrog | s->in ++; |
770 | d8f699cb | balrog | s->mem_write[2](s->opaque, addr, value);
|
771 | d8f699cb | balrog | s->in --; |
772 | d8f699cb | balrog | } |
773 | d8f699cb | balrog | |
774 | d8f699cb | balrog | static CPUReadMemoryFunc *io_readfn[] = { io_readb, io_readh, io_readw, };
|
775 | d8f699cb | balrog | static CPUWriteMemoryFunc *io_writefn[] = { io_writeb, io_writeh, io_writew, };
|
776 | d8f699cb | balrog | |
777 | d8f699cb | balrog | inline static int debug_register_io_memory(int io_index, |
778 | d8f699cb | balrog | CPUReadMemoryFunc **mem_read, CPUWriteMemoryFunc **mem_write, |
779 | d8f699cb | balrog | void *opaque)
|
780 | d8f699cb | balrog | { |
781 | d8f699cb | balrog | struct io_fn *s = qemu_malloc(sizeof(struct io_fn)); |
782 | d8f699cb | balrog | |
783 | d8f699cb | balrog | s->mem_read = mem_read; |
784 | d8f699cb | balrog | s->mem_write = mem_write; |
785 | d8f699cb | balrog | s->opaque = opaque; |
786 | d8f699cb | balrog | s->in = 0;
|
787 | d8f699cb | balrog | return cpu_register_io_memory(io_index, io_readfn, io_writefn, s);
|
788 | d8f699cb | balrog | } |
789 | d8f699cb | balrog | # define cpu_register_io_memory debug_register_io_memory
|
790 | d8f699cb | balrog | # endif
|
791 | d8f699cb | balrog | |
792 | 87ecb68b | pbrook | /* Not really omap specific, but is the only thing that uses the
|
793 | 87ecb68b | pbrook | uwire interface. */
|
794 | 87ecb68b | pbrook | /* tsc210x.c */
|
795 | 87ecb68b | pbrook | struct uwire_slave_s *tsc2102_init(qemu_irq pint, AudioState *audio);
|
796 | 87ecb68b | pbrook | struct i2s_codec_s *tsc210x_codec(struct uwire_slave_s *chip); |
797 | 87ecb68b | pbrook | |
798 | c3d2689d | balrog | #endif /* hw_omap_h */ |