root / hw / pxa2xx_timer.c @ 87ecb68b
History | View | Annotate | Download (13.3 kB)
1 | a171fe39 | balrog | /*
|
---|---|---|---|
2 | a171fe39 | balrog | * Intel XScale PXA255/270 OS Timers.
|
3 | a171fe39 | balrog | *
|
4 | a171fe39 | balrog | * Copyright (c) 2006 Openedhand Ltd.
|
5 | a171fe39 | balrog | * Copyright (c) 2006 Thorsten Zitterell
|
6 | a171fe39 | balrog | *
|
7 | a171fe39 | balrog | * This code is licenced under the GPL.
|
8 | a171fe39 | balrog | */
|
9 | a171fe39 | balrog | |
10 | 87ecb68b | pbrook | #include "hw.h" |
11 | 87ecb68b | pbrook | #include "qemu-timer.h" |
12 | 87ecb68b | pbrook | #include "sysemu.h" |
13 | 87ecb68b | pbrook | #include "pxa.h" |
14 | a171fe39 | balrog | |
15 | a171fe39 | balrog | #define OSMR0 0x00 |
16 | a171fe39 | balrog | #define OSMR1 0x04 |
17 | a171fe39 | balrog | #define OSMR2 0x08 |
18 | a171fe39 | balrog | #define OSMR3 0x0c |
19 | a171fe39 | balrog | #define OSMR4 0x80 |
20 | a171fe39 | balrog | #define OSMR5 0x84 |
21 | a171fe39 | balrog | #define OSMR6 0x88 |
22 | a171fe39 | balrog | #define OSMR7 0x8c |
23 | a171fe39 | balrog | #define OSMR8 0x90 |
24 | a171fe39 | balrog | #define OSMR9 0x94 |
25 | a171fe39 | balrog | #define OSMR10 0x98 |
26 | a171fe39 | balrog | #define OSMR11 0x9c |
27 | a171fe39 | balrog | #define OSCR 0x10 /* OS Timer Count */ |
28 | a171fe39 | balrog | #define OSCR4 0x40 |
29 | a171fe39 | balrog | #define OSCR5 0x44 |
30 | a171fe39 | balrog | #define OSCR6 0x48 |
31 | a171fe39 | balrog | #define OSCR7 0x4c |
32 | a171fe39 | balrog | #define OSCR8 0x50 |
33 | a171fe39 | balrog | #define OSCR9 0x54 |
34 | a171fe39 | balrog | #define OSCR10 0x58 |
35 | a171fe39 | balrog | #define OSCR11 0x5c |
36 | a171fe39 | balrog | #define OSSR 0x14 /* Timer status register */ |
37 | a171fe39 | balrog | #define OWER 0x18 |
38 | a171fe39 | balrog | #define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */ |
39 | a171fe39 | balrog | #define OMCR4 0xc0 /* OS Match Control registers */ |
40 | a171fe39 | balrog | #define OMCR5 0xc4 |
41 | a171fe39 | balrog | #define OMCR6 0xc8 |
42 | a171fe39 | balrog | #define OMCR7 0xcc |
43 | a171fe39 | balrog | #define OMCR8 0xd0 |
44 | a171fe39 | balrog | #define OMCR9 0xd4 |
45 | a171fe39 | balrog | #define OMCR10 0xd8 |
46 | a171fe39 | balrog | #define OMCR11 0xdc |
47 | a171fe39 | balrog | #define OSNR 0x20 |
48 | a171fe39 | balrog | |
49 | a171fe39 | balrog | #define PXA25X_FREQ 3686400 /* 3.6864 MHz */ |
50 | a171fe39 | balrog | #define PXA27X_FREQ 3250000 /* 3.25 MHz */ |
51 | a171fe39 | balrog | |
52 | a171fe39 | balrog | static int pxa2xx_timer4_freq[8] = { |
53 | a171fe39 | balrog | [0] = 0, |
54 | a171fe39 | balrog | [1] = 32768, |
55 | a171fe39 | balrog | [2] = 1000, |
56 | a171fe39 | balrog | [3] = 1, |
57 | a171fe39 | balrog | [4] = 1000000, |
58 | a171fe39 | balrog | /* [5] is the "Externally supplied clock". Assign if necessary. */
|
59 | a171fe39 | balrog | [5 ... 7] = 0, |
60 | a171fe39 | balrog | }; |
61 | a171fe39 | balrog | |
62 | a171fe39 | balrog | struct pxa2xx_timer0_s {
|
63 | a171fe39 | balrog | uint32_t value; |
64 | a171fe39 | balrog | int level;
|
65 | a171fe39 | balrog | qemu_irq irq; |
66 | a171fe39 | balrog | QEMUTimer *qtimer; |
67 | a171fe39 | balrog | int num;
|
68 | a171fe39 | balrog | void *info;
|
69 | a171fe39 | balrog | }; |
70 | a171fe39 | balrog | |
71 | a171fe39 | balrog | struct pxa2xx_timer4_s {
|
72 | 3bdd58a4 | balrog | struct pxa2xx_timer0_s tm;
|
73 | a171fe39 | balrog | int32_t oldclock; |
74 | a171fe39 | balrog | int32_t clock; |
75 | a171fe39 | balrog | uint64_t lastload; |
76 | a171fe39 | balrog | uint32_t freq; |
77 | a171fe39 | balrog | uint32_t control; |
78 | a171fe39 | balrog | }; |
79 | a171fe39 | balrog | |
80 | a171fe39 | balrog | typedef struct { |
81 | 3f582262 | balrog | target_phys_addr_t base; |
82 | a171fe39 | balrog | int32_t clock; |
83 | a171fe39 | balrog | int32_t oldclock; |
84 | a171fe39 | balrog | uint64_t lastload; |
85 | a171fe39 | balrog | uint32_t freq; |
86 | a171fe39 | balrog | struct pxa2xx_timer0_s timer[4]; |
87 | a171fe39 | balrog | struct pxa2xx_timer4_s *tm4;
|
88 | a171fe39 | balrog | uint32_t events; |
89 | a171fe39 | balrog | uint32_t irq_enabled; |
90 | a171fe39 | balrog | uint32_t reset3; |
91 | a171fe39 | balrog | uint32_t snapshot; |
92 | a171fe39 | balrog | } pxa2xx_timer_info; |
93 | a171fe39 | balrog | |
94 | a171fe39 | balrog | static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu) |
95 | a171fe39 | balrog | { |
96 | a171fe39 | balrog | pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque; |
97 | a171fe39 | balrog | int i;
|
98 | a171fe39 | balrog | uint32_t now_vm; |
99 | a171fe39 | balrog | uint64_t new_qemu; |
100 | a171fe39 | balrog | |
101 | a171fe39 | balrog | now_vm = s->clock + |
102 | a171fe39 | balrog | muldiv64(now_qemu - s->lastload, s->freq, ticks_per_sec); |
103 | a171fe39 | balrog | |
104 | a171fe39 | balrog | for (i = 0; i < 4; i ++) { |
105 | a171fe39 | balrog | new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm), |
106 | a171fe39 | balrog | ticks_per_sec, s->freq); |
107 | a171fe39 | balrog | qemu_mod_timer(s->timer[i].qtimer, new_qemu); |
108 | a171fe39 | balrog | } |
109 | a171fe39 | balrog | } |
110 | a171fe39 | balrog | |
111 | a171fe39 | balrog | static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n) |
112 | a171fe39 | balrog | { |
113 | a171fe39 | balrog | pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque; |
114 | a171fe39 | balrog | uint32_t now_vm; |
115 | a171fe39 | balrog | uint64_t new_qemu; |
116 | a171fe39 | balrog | static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 }; |
117 | a171fe39 | balrog | int counter;
|
118 | a171fe39 | balrog | |
119 | a171fe39 | balrog | if (s->tm4[n].control & (1 << 7)) |
120 | a171fe39 | balrog | counter = n; |
121 | a171fe39 | balrog | else
|
122 | a171fe39 | balrog | counter = counters[n]; |
123 | a171fe39 | balrog | |
124 | a171fe39 | balrog | if (!s->tm4[counter].freq) {
|
125 | 3f582262 | balrog | qemu_del_timer(s->tm4[n].tm.qtimer); |
126 | a171fe39 | balrog | return;
|
127 | a171fe39 | balrog | } |
128 | a171fe39 | balrog | |
129 | a171fe39 | balrog | now_vm = s->tm4[counter].clock + muldiv64(now_qemu - |
130 | a171fe39 | balrog | s->tm4[counter].lastload, |
131 | a171fe39 | balrog | s->tm4[counter].freq, ticks_per_sec); |
132 | a171fe39 | balrog | |
133 | 3bdd58a4 | balrog | new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm), |
134 | a171fe39 | balrog | ticks_per_sec, s->tm4[counter].freq); |
135 | 3f582262 | balrog | qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu); |
136 | a171fe39 | balrog | } |
137 | a171fe39 | balrog | |
138 | a171fe39 | balrog | static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset) |
139 | a171fe39 | balrog | { |
140 | a171fe39 | balrog | pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque; |
141 | a171fe39 | balrog | int tm = 0; |
142 | a171fe39 | balrog | |
143 | a171fe39 | balrog | offset -= s->base; |
144 | a171fe39 | balrog | |
145 | a171fe39 | balrog | switch (offset) {
|
146 | a171fe39 | balrog | case OSMR3: tm ++;
|
147 | a171fe39 | balrog | case OSMR2: tm ++;
|
148 | a171fe39 | balrog | case OSMR1: tm ++;
|
149 | a171fe39 | balrog | case OSMR0:
|
150 | a171fe39 | balrog | return s->timer[tm].value;
|
151 | a171fe39 | balrog | case OSMR11: tm ++;
|
152 | a171fe39 | balrog | case OSMR10: tm ++;
|
153 | a171fe39 | balrog | case OSMR9: tm ++;
|
154 | a171fe39 | balrog | case OSMR8: tm ++;
|
155 | a171fe39 | balrog | case OSMR7: tm ++;
|
156 | a171fe39 | balrog | case OSMR6: tm ++;
|
157 | a171fe39 | balrog | case OSMR5: tm ++;
|
158 | a171fe39 | balrog | case OSMR4:
|
159 | a171fe39 | balrog | if (!s->tm4)
|
160 | a171fe39 | balrog | goto badreg;
|
161 | 3bdd58a4 | balrog | return s->tm4[tm].tm.value;
|
162 | a171fe39 | balrog | case OSCR:
|
163 | a171fe39 | balrog | return s->clock + muldiv64(qemu_get_clock(vm_clock) -
|
164 | a171fe39 | balrog | s->lastload, s->freq, ticks_per_sec); |
165 | a171fe39 | balrog | case OSCR11: tm ++;
|
166 | a171fe39 | balrog | case OSCR10: tm ++;
|
167 | a171fe39 | balrog | case OSCR9: tm ++;
|
168 | a171fe39 | balrog | case OSCR8: tm ++;
|
169 | a171fe39 | balrog | case OSCR7: tm ++;
|
170 | a171fe39 | balrog | case OSCR6: tm ++;
|
171 | a171fe39 | balrog | case OSCR5: tm ++;
|
172 | a171fe39 | balrog | case OSCR4:
|
173 | a171fe39 | balrog | if (!s->tm4)
|
174 | a171fe39 | balrog | goto badreg;
|
175 | a171fe39 | balrog | |
176 | a171fe39 | balrog | if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) { |
177 | a171fe39 | balrog | if (s->tm4[tm - 1].freq) |
178 | a171fe39 | balrog | s->snapshot = s->tm4[tm - 1].clock + muldiv64(
|
179 | a171fe39 | balrog | qemu_get_clock(vm_clock) - |
180 | a171fe39 | balrog | s->tm4[tm - 1].lastload,
|
181 | a171fe39 | balrog | s->tm4[tm - 1].freq, ticks_per_sec);
|
182 | a171fe39 | balrog | else
|
183 | a171fe39 | balrog | s->snapshot = s->tm4[tm - 1].clock;
|
184 | a171fe39 | balrog | } |
185 | a171fe39 | balrog | |
186 | a171fe39 | balrog | if (!s->tm4[tm].freq)
|
187 | a171fe39 | balrog | return s->tm4[tm].clock;
|
188 | a171fe39 | balrog | return s->tm4[tm].clock + muldiv64(qemu_get_clock(vm_clock) -
|
189 | a171fe39 | balrog | s->tm4[tm].lastload, s->tm4[tm].freq, ticks_per_sec); |
190 | a171fe39 | balrog | case OIER:
|
191 | a171fe39 | balrog | return s->irq_enabled;
|
192 | a171fe39 | balrog | case OSSR: /* Status register */ |
193 | a171fe39 | balrog | return s->events;
|
194 | a171fe39 | balrog | case OWER:
|
195 | a171fe39 | balrog | return s->reset3;
|
196 | a171fe39 | balrog | case OMCR11: tm ++;
|
197 | a171fe39 | balrog | case OMCR10: tm ++;
|
198 | a171fe39 | balrog | case OMCR9: tm ++;
|
199 | a171fe39 | balrog | case OMCR8: tm ++;
|
200 | a171fe39 | balrog | case OMCR7: tm ++;
|
201 | a171fe39 | balrog | case OMCR6: tm ++;
|
202 | a171fe39 | balrog | case OMCR5: tm ++;
|
203 | a171fe39 | balrog | case OMCR4:
|
204 | a171fe39 | balrog | if (!s->tm4)
|
205 | a171fe39 | balrog | goto badreg;
|
206 | a171fe39 | balrog | return s->tm4[tm].control;
|
207 | a171fe39 | balrog | case OSNR:
|
208 | a171fe39 | balrog | return s->snapshot;
|
209 | a171fe39 | balrog | default:
|
210 | a171fe39 | balrog | badreg:
|
211 | a171fe39 | balrog | cpu_abort(cpu_single_env, "pxa2xx_timer_read: Bad offset "
|
212 | a171fe39 | balrog | REG_FMT "\n", offset);
|
213 | a171fe39 | balrog | } |
214 | a171fe39 | balrog | |
215 | a171fe39 | balrog | return 0; |
216 | a171fe39 | balrog | } |
217 | a171fe39 | balrog | |
218 | a171fe39 | balrog | static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset, |
219 | a171fe39 | balrog | uint32_t value) |
220 | a171fe39 | balrog | { |
221 | a171fe39 | balrog | int i, tm = 0; |
222 | a171fe39 | balrog | pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque; |
223 | a171fe39 | balrog | |
224 | a171fe39 | balrog | offset -= s->base; |
225 | a171fe39 | balrog | |
226 | a171fe39 | balrog | switch (offset) {
|
227 | a171fe39 | balrog | case OSMR3: tm ++;
|
228 | a171fe39 | balrog | case OSMR2: tm ++;
|
229 | a171fe39 | balrog | case OSMR1: tm ++;
|
230 | a171fe39 | balrog | case OSMR0:
|
231 | a171fe39 | balrog | s->timer[tm].value = value; |
232 | a171fe39 | balrog | pxa2xx_timer_update(s, qemu_get_clock(vm_clock)); |
233 | a171fe39 | balrog | break;
|
234 | a171fe39 | balrog | case OSMR11: tm ++;
|
235 | a171fe39 | balrog | case OSMR10: tm ++;
|
236 | a171fe39 | balrog | case OSMR9: tm ++;
|
237 | a171fe39 | balrog | case OSMR8: tm ++;
|
238 | a171fe39 | balrog | case OSMR7: tm ++;
|
239 | a171fe39 | balrog | case OSMR6: tm ++;
|
240 | a171fe39 | balrog | case OSMR5: tm ++;
|
241 | a171fe39 | balrog | case OSMR4:
|
242 | a171fe39 | balrog | if (!s->tm4)
|
243 | a171fe39 | balrog | goto badreg;
|
244 | 3bdd58a4 | balrog | s->tm4[tm].tm.value = value; |
245 | a171fe39 | balrog | pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm); |
246 | a171fe39 | balrog | break;
|
247 | a171fe39 | balrog | case OSCR:
|
248 | a171fe39 | balrog | s->oldclock = s->clock; |
249 | a171fe39 | balrog | s->lastload = qemu_get_clock(vm_clock); |
250 | a171fe39 | balrog | s->clock = value; |
251 | a171fe39 | balrog | pxa2xx_timer_update(s, s->lastload); |
252 | a171fe39 | balrog | break;
|
253 | a171fe39 | balrog | case OSCR11: tm ++;
|
254 | a171fe39 | balrog | case OSCR10: tm ++;
|
255 | a171fe39 | balrog | case OSCR9: tm ++;
|
256 | a171fe39 | balrog | case OSCR8: tm ++;
|
257 | a171fe39 | balrog | case OSCR7: tm ++;
|
258 | a171fe39 | balrog | case OSCR6: tm ++;
|
259 | a171fe39 | balrog | case OSCR5: tm ++;
|
260 | a171fe39 | balrog | case OSCR4:
|
261 | a171fe39 | balrog | if (!s->tm4)
|
262 | a171fe39 | balrog | goto badreg;
|
263 | a171fe39 | balrog | s->tm4[tm].oldclock = s->tm4[tm].clock; |
264 | a171fe39 | balrog | s->tm4[tm].lastload = qemu_get_clock(vm_clock); |
265 | a171fe39 | balrog | s->tm4[tm].clock = value; |
266 | a171fe39 | balrog | pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm); |
267 | a171fe39 | balrog | break;
|
268 | a171fe39 | balrog | case OIER:
|
269 | a171fe39 | balrog | s->irq_enabled = value & 0xfff;
|
270 | a171fe39 | balrog | break;
|
271 | a171fe39 | balrog | case OSSR: /* Status register */ |
272 | a171fe39 | balrog | s->events &= ~value; |
273 | a171fe39 | balrog | for (i = 0; i < 4; i ++, value >>= 1) { |
274 | a171fe39 | balrog | if (s->timer[i].level && (value & 1)) { |
275 | a171fe39 | balrog | s->timer[i].level = 0;
|
276 | a171fe39 | balrog | qemu_irq_lower(s->timer[i].irq); |
277 | a171fe39 | balrog | } |
278 | a171fe39 | balrog | } |
279 | a171fe39 | balrog | if (s->tm4) {
|
280 | a171fe39 | balrog | for (i = 0; i < 8; i ++, value >>= 1) |
281 | 3bdd58a4 | balrog | if (s->tm4[i].tm.level && (value & 1)) |
282 | 3bdd58a4 | balrog | s->tm4[i].tm.level = 0;
|
283 | a171fe39 | balrog | if (!(s->events & 0xff0)) |
284 | 3bdd58a4 | balrog | qemu_irq_lower(s->tm4->tm.irq); |
285 | a171fe39 | balrog | } |
286 | a171fe39 | balrog | break;
|
287 | a171fe39 | balrog | case OWER: /* XXX: Reset on OSMR3 match? */ |
288 | a171fe39 | balrog | s->reset3 = value; |
289 | a171fe39 | balrog | break;
|
290 | a171fe39 | balrog | case OMCR7: tm ++;
|
291 | a171fe39 | balrog | case OMCR6: tm ++;
|
292 | a171fe39 | balrog | case OMCR5: tm ++;
|
293 | a171fe39 | balrog | case OMCR4:
|
294 | a171fe39 | balrog | if (!s->tm4)
|
295 | a171fe39 | balrog | goto badreg;
|
296 | a171fe39 | balrog | s->tm4[tm].control = value & 0x0ff;
|
297 | a171fe39 | balrog | /* XXX Stop if running (shouldn't happen) */
|
298 | a171fe39 | balrog | if ((value & (1 << 7)) || tm == 0) |
299 | a171fe39 | balrog | s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
|
300 | a171fe39 | balrog | else {
|
301 | a171fe39 | balrog | s->tm4[tm].freq = 0;
|
302 | a171fe39 | balrog | pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm); |
303 | a171fe39 | balrog | } |
304 | a171fe39 | balrog | break;
|
305 | a171fe39 | balrog | case OMCR11: tm ++;
|
306 | a171fe39 | balrog | case OMCR10: tm ++;
|
307 | a171fe39 | balrog | case OMCR9: tm ++;
|
308 | a171fe39 | balrog | case OMCR8: tm += 4; |
309 | a171fe39 | balrog | if (!s->tm4)
|
310 | a171fe39 | balrog | goto badreg;
|
311 | a171fe39 | balrog | s->tm4[tm].control = value & 0x3ff;
|
312 | a171fe39 | balrog | /* XXX Stop if running (shouldn't happen) */
|
313 | a171fe39 | balrog | if ((value & (1 << 7)) || !(tm & 1)) |
314 | a171fe39 | balrog | s->tm4[tm].freq = |
315 | a171fe39 | balrog | pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)]; |
316 | a171fe39 | balrog | else {
|
317 | a171fe39 | balrog | s->tm4[tm].freq = 0;
|
318 | a171fe39 | balrog | pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm); |
319 | a171fe39 | balrog | } |
320 | a171fe39 | balrog | break;
|
321 | a171fe39 | balrog | default:
|
322 | a171fe39 | balrog | badreg:
|
323 | a171fe39 | balrog | cpu_abort(cpu_single_env, "pxa2xx_timer_write: Bad offset "
|
324 | a171fe39 | balrog | REG_FMT "\n", offset);
|
325 | a171fe39 | balrog | } |
326 | a171fe39 | balrog | } |
327 | a171fe39 | balrog | |
328 | a171fe39 | balrog | static CPUReadMemoryFunc *pxa2xx_timer_readfn[] = {
|
329 | a171fe39 | balrog | pxa2xx_timer_read, |
330 | a171fe39 | balrog | pxa2xx_timer_read, |
331 | a171fe39 | balrog | pxa2xx_timer_read, |
332 | a171fe39 | balrog | }; |
333 | a171fe39 | balrog | |
334 | a171fe39 | balrog | static CPUWriteMemoryFunc *pxa2xx_timer_writefn[] = {
|
335 | a171fe39 | balrog | pxa2xx_timer_write, |
336 | a171fe39 | balrog | pxa2xx_timer_write, |
337 | a171fe39 | balrog | pxa2xx_timer_write, |
338 | a171fe39 | balrog | }; |
339 | a171fe39 | balrog | |
340 | a171fe39 | balrog | static void pxa2xx_timer_tick(void *opaque) |
341 | a171fe39 | balrog | { |
342 | a171fe39 | balrog | struct pxa2xx_timer0_s *t = (struct pxa2xx_timer0_s *) opaque; |
343 | a171fe39 | balrog | pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->info; |
344 | a171fe39 | balrog | |
345 | a171fe39 | balrog | if (i->irq_enabled & (1 << t->num)) { |
346 | a171fe39 | balrog | t->level = 1;
|
347 | a171fe39 | balrog | i->events |= 1 << t->num;
|
348 | a171fe39 | balrog | qemu_irq_raise(t->irq); |
349 | a171fe39 | balrog | } |
350 | a171fe39 | balrog | |
351 | a171fe39 | balrog | if (t->num == 3) |
352 | a171fe39 | balrog | if (i->reset3 & 1) { |
353 | a171fe39 | balrog | i->reset3 = 0;
|
354 | 3f582262 | balrog | qemu_system_reset_request(); |
355 | a171fe39 | balrog | } |
356 | a171fe39 | balrog | } |
357 | a171fe39 | balrog | |
358 | a171fe39 | balrog | static void pxa2xx_timer_tick4(void *opaque) |
359 | a171fe39 | balrog | { |
360 | a171fe39 | balrog | struct pxa2xx_timer4_s *t = (struct pxa2xx_timer4_s *) opaque; |
361 | 3bdd58a4 | balrog | pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->tm.info; |
362 | a171fe39 | balrog | |
363 | 3bdd58a4 | balrog | pxa2xx_timer_tick(&t->tm); |
364 | a171fe39 | balrog | if (t->control & (1 << 3)) |
365 | a171fe39 | balrog | t->clock = 0;
|
366 | a171fe39 | balrog | if (t->control & (1 << 6)) |
367 | 3bdd58a4 | balrog | pxa2xx_timer_update4(i, qemu_get_clock(vm_clock), t->tm.num - 4);
|
368 | a171fe39 | balrog | } |
369 | a171fe39 | balrog | |
370 | aa941b94 | balrog | static void pxa2xx_timer_save(QEMUFile *f, void *opaque) |
371 | aa941b94 | balrog | { |
372 | aa941b94 | balrog | pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque; |
373 | aa941b94 | balrog | int i;
|
374 | aa941b94 | balrog | |
375 | aa941b94 | balrog | qemu_put_be32s(f, &s->clock); |
376 | aa941b94 | balrog | qemu_put_be32s(f, &s->oldclock); |
377 | aa941b94 | balrog | qemu_put_be64s(f, &s->lastload); |
378 | aa941b94 | balrog | |
379 | aa941b94 | balrog | for (i = 0; i < 4; i ++) { |
380 | aa941b94 | balrog | qemu_put_be32s(f, &s->timer[i].value); |
381 | aa941b94 | balrog | qemu_put_be32(f, s->timer[i].level); |
382 | aa941b94 | balrog | } |
383 | aa941b94 | balrog | if (s->tm4)
|
384 | aa941b94 | balrog | for (i = 0; i < 8; i ++) { |
385 | aa941b94 | balrog | qemu_put_be32s(f, &s->tm4[i].tm.value); |
386 | aa941b94 | balrog | qemu_put_be32(f, s->tm4[i].tm.level); |
387 | aa941b94 | balrog | qemu_put_be32s(f, &s->tm4[i].oldclock); |
388 | aa941b94 | balrog | qemu_put_be32s(f, &s->tm4[i].clock); |
389 | aa941b94 | balrog | qemu_put_be64s(f, &s->tm4[i].lastload); |
390 | aa941b94 | balrog | qemu_put_be32s(f, &s->tm4[i].freq); |
391 | aa941b94 | balrog | qemu_put_be32s(f, &s->tm4[i].control); |
392 | aa941b94 | balrog | } |
393 | aa941b94 | balrog | |
394 | aa941b94 | balrog | qemu_put_be32s(f, &s->events); |
395 | aa941b94 | balrog | qemu_put_be32s(f, &s->irq_enabled); |
396 | aa941b94 | balrog | qemu_put_be32s(f, &s->reset3); |
397 | aa941b94 | balrog | qemu_put_be32s(f, &s->snapshot); |
398 | aa941b94 | balrog | } |
399 | aa941b94 | balrog | |
400 | aa941b94 | balrog | static int pxa2xx_timer_load(QEMUFile *f, void *opaque, int version_id) |
401 | aa941b94 | balrog | { |
402 | aa941b94 | balrog | pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque; |
403 | aa941b94 | balrog | int64_t now; |
404 | aa941b94 | balrog | int i;
|
405 | aa941b94 | balrog | |
406 | aa941b94 | balrog | qemu_get_be32s(f, &s->clock); |
407 | aa941b94 | balrog | qemu_get_be32s(f, &s->oldclock); |
408 | aa941b94 | balrog | qemu_get_be64s(f, &s->lastload); |
409 | aa941b94 | balrog | |
410 | aa941b94 | balrog | now = qemu_get_clock(vm_clock); |
411 | aa941b94 | balrog | for (i = 0; i < 4; i ++) { |
412 | aa941b94 | balrog | qemu_get_be32s(f, &s->timer[i].value); |
413 | aa941b94 | balrog | s->timer[i].level = qemu_get_be32(f); |
414 | aa941b94 | balrog | } |
415 | aa941b94 | balrog | pxa2xx_timer_update(s, now); |
416 | aa941b94 | balrog | |
417 | aa941b94 | balrog | if (s->tm4)
|
418 | aa941b94 | balrog | for (i = 0; i < 8; i ++) { |
419 | aa941b94 | balrog | qemu_get_be32s(f, &s->tm4[i].tm.value); |
420 | aa941b94 | balrog | s->tm4[i].tm.level = qemu_get_be32(f); |
421 | aa941b94 | balrog | qemu_get_be32s(f, &s->tm4[i].oldclock); |
422 | aa941b94 | balrog | qemu_get_be32s(f, &s->tm4[i].clock); |
423 | aa941b94 | balrog | qemu_get_be64s(f, &s->tm4[i].lastload); |
424 | aa941b94 | balrog | qemu_get_be32s(f, &s->tm4[i].freq); |
425 | aa941b94 | balrog | qemu_get_be32s(f, &s->tm4[i].control); |
426 | aa941b94 | balrog | pxa2xx_timer_update4(s, now, i); |
427 | aa941b94 | balrog | } |
428 | aa941b94 | balrog | |
429 | aa941b94 | balrog | qemu_get_be32s(f, &s->events); |
430 | aa941b94 | balrog | qemu_get_be32s(f, &s->irq_enabled); |
431 | aa941b94 | balrog | qemu_get_be32s(f, &s->reset3); |
432 | aa941b94 | balrog | qemu_get_be32s(f, &s->snapshot); |
433 | aa941b94 | balrog | |
434 | aa941b94 | balrog | return 0; |
435 | aa941b94 | balrog | } |
436 | aa941b94 | balrog | |
437 | a171fe39 | balrog | static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
|
438 | 3f582262 | balrog | qemu_irq *irqs) |
439 | a171fe39 | balrog | { |
440 | a171fe39 | balrog | int i;
|
441 | a171fe39 | balrog | int iomemtype;
|
442 | a171fe39 | balrog | pxa2xx_timer_info *s; |
443 | a171fe39 | balrog | |
444 | a171fe39 | balrog | s = (pxa2xx_timer_info *) qemu_mallocz(sizeof(pxa2xx_timer_info));
|
445 | a171fe39 | balrog | s->base = base; |
446 | a171fe39 | balrog | s->irq_enabled = 0;
|
447 | a171fe39 | balrog | s->oldclock = 0;
|
448 | a171fe39 | balrog | s->clock = 0;
|
449 | a171fe39 | balrog | s->lastload = qemu_get_clock(vm_clock); |
450 | a171fe39 | balrog | s->reset3 = 0;
|
451 | a171fe39 | balrog | |
452 | a171fe39 | balrog | for (i = 0; i < 4; i ++) { |
453 | a171fe39 | balrog | s->timer[i].value = 0;
|
454 | a171fe39 | balrog | s->timer[i].irq = irqs[i]; |
455 | a171fe39 | balrog | s->timer[i].info = s; |
456 | a171fe39 | balrog | s->timer[i].num = i; |
457 | a171fe39 | balrog | s->timer[i].level = 0;
|
458 | a171fe39 | balrog | s->timer[i].qtimer = qemu_new_timer(vm_clock, |
459 | a171fe39 | balrog | pxa2xx_timer_tick, &s->timer[i]); |
460 | a171fe39 | balrog | } |
461 | a171fe39 | balrog | |
462 | a171fe39 | balrog | iomemtype = cpu_register_io_memory(0, pxa2xx_timer_readfn,
|
463 | a171fe39 | balrog | pxa2xx_timer_writefn, s); |
464 | 187337f8 | pbrook | cpu_register_physical_memory(base, 0x00001000, iomemtype);
|
465 | aa941b94 | balrog | |
466 | aa941b94 | balrog | register_savevm("pxa2xx_timer", 0, 0, |
467 | aa941b94 | balrog | pxa2xx_timer_save, pxa2xx_timer_load, s); |
468 | aa941b94 | balrog | |
469 | a171fe39 | balrog | return s;
|
470 | a171fe39 | balrog | } |
471 | a171fe39 | balrog | |
472 | 3f582262 | balrog | void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs)
|
473 | a171fe39 | balrog | { |
474 | 3f582262 | balrog | pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs); |
475 | a171fe39 | balrog | s->freq = PXA25X_FREQ; |
476 | a171fe39 | balrog | s->tm4 = 0;
|
477 | a171fe39 | balrog | } |
478 | a171fe39 | balrog | |
479 | a171fe39 | balrog | void pxa27x_timer_init(target_phys_addr_t base,
|
480 | 3f582262 | balrog | qemu_irq *irqs, qemu_irq irq4) |
481 | a171fe39 | balrog | { |
482 | 3f582262 | balrog | pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs); |
483 | a171fe39 | balrog | int i;
|
484 | a171fe39 | balrog | s->freq = PXA27X_FREQ; |
485 | a171fe39 | balrog | s->tm4 = (struct pxa2xx_timer4_s *) qemu_mallocz(8 * |
486 | a171fe39 | balrog | sizeof(struct pxa2xx_timer4_s)); |
487 | a171fe39 | balrog | for (i = 0; i < 8; i ++) { |
488 | 3bdd58a4 | balrog | s->tm4[i].tm.value = 0;
|
489 | 3bdd58a4 | balrog | s->tm4[i].tm.irq = irq4; |
490 | 3bdd58a4 | balrog | s->tm4[i].tm.info = s; |
491 | 3bdd58a4 | balrog | s->tm4[i].tm.num = i + 4;
|
492 | 3bdd58a4 | balrog | s->tm4[i].tm.level = 0;
|
493 | a171fe39 | balrog | s->tm4[i].freq = 0;
|
494 | a171fe39 | balrog | s->tm4[i].control = 0x0;
|
495 | 3bdd58a4 | balrog | s->tm4[i].tm.qtimer = qemu_new_timer(vm_clock, |
496 | a171fe39 | balrog | pxa2xx_timer_tick4, &s->tm4[i]); |
497 | a171fe39 | balrog | } |
498 | a171fe39 | balrog | } |