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/*
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* QEMU PowerMac CUDA device support
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*
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* Copyright (c) 2004-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "ppc_mac.h" |
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#include "qemu-timer.h" |
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#include "sysemu.h" |
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|
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/* XXX: implement all timer modes */
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|
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//#define DEBUG_CUDA
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//#define DEBUG_CUDA_PACKET
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|
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/* Bits in B data register: all active low */
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#define TREQ 0x08 /* Transfer request (input) */ |
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#define TACK 0x10 /* Transfer acknowledge (output) */ |
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#define TIP 0x20 /* Transfer in progress (output) */ |
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|
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/* Bits in ACR */
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#define SR_CTRL 0x1c /* Shift register control bits */ |
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#define SR_EXT 0x0c /* Shift on external clock */ |
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#define SR_OUT 0x10 /* Shift out if 1 */ |
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|
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/* Bits in IFR and IER */
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#define IER_SET 0x80 /* set bits in IER */ |
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#define IER_CLR 0 /* clear bits in IER */ |
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#define SR_INT 0x04 /* Shift register full/empty */ |
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#define T1_INT 0x40 /* Timer 1 interrupt */ |
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#define T2_INT 0x20 /* Timer 2 interrupt */ |
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|
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/* Bits in ACR */
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#define T1MODE 0xc0 /* Timer 1 mode */ |
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#define T1MODE_CONT 0x40 /* continuous interrupts */ |
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|
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/* commands (1st byte) */
|
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#define ADB_PACKET 0 |
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#define CUDA_PACKET 1 |
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#define ERROR_PACKET 2 |
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#define TIMER_PACKET 3 |
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#define POWER_PACKET 4 |
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#define MACIIC_PACKET 5 |
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#define PMU_PACKET 6 |
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|
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|
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/* CUDA commands (2nd byte) */
|
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#define CUDA_WARM_START 0x0 |
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#define CUDA_AUTOPOLL 0x1 |
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#define CUDA_GET_6805_ADDR 0x2 |
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#define CUDA_GET_TIME 0x3 |
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#define CUDA_GET_PRAM 0x7 |
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#define CUDA_SET_6805_ADDR 0x8 |
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#define CUDA_SET_TIME 0x9 |
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#define CUDA_POWERDOWN 0xa |
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#define CUDA_POWERUP_TIME 0xb |
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#define CUDA_SET_PRAM 0xc |
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#define CUDA_MS_RESET 0xd |
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#define CUDA_SEND_DFAC 0xe |
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#define CUDA_BATTERY_SWAP_SENSE 0x10 |
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#define CUDA_RESET_SYSTEM 0x11 |
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#define CUDA_SET_IPL 0x12 |
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#define CUDA_FILE_SERVER_FLAG 0x13 |
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#define CUDA_SET_AUTO_RATE 0x14 |
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#define CUDA_GET_AUTO_RATE 0x16 |
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#define CUDA_SET_DEVICE_LIST 0x19 |
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#define CUDA_GET_DEVICE_LIST 0x1a |
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#define CUDA_SET_ONE_SECOND_MODE 0x1b |
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#define CUDA_SET_POWER_MESSAGES 0x21 |
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#define CUDA_GET_SET_IIC 0x22 |
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#define CUDA_WAKEUP 0x23 |
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#define CUDA_TIMER_TICKLE 0x24 |
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#define CUDA_COMBINED_FORMAT_IIC 0x25 |
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|
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#define CUDA_TIMER_FREQ (4700000 / 6) |
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#define CUDA_ADB_POLL_FREQ 50 |
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|
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/* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
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#define RTC_OFFSET 2082844800 |
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|
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typedef struct CUDATimer { |
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int index;
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uint16_t latch; |
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uint16_t counter_value; /* counter value at load time */
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int64_t load_time; |
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int64_t next_irq_time; |
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QEMUTimer *timer; |
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} CUDATimer; |
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|
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typedef struct CUDAState { |
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/* cuda registers */
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uint8_t b; /* B-side data */
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uint8_t a; /* A-side data */
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uint8_t dirb; /* B-side direction (1=output) */
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uint8_t dira; /* A-side direction (1=output) */
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uint8_t sr; /* Shift register */
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uint8_t acr; /* Auxiliary control register */
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uint8_t pcr; /* Peripheral control register */
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uint8_t ifr; /* Interrupt flag register */
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uint8_t ier; /* Interrupt enable register */
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uint8_t anh; /* A-side data, no handshake */
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CUDATimer timers[2];
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uint8_t last_b; /* last value of B register */
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uint8_t last_acr; /* last value of B register */
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|
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int data_in_size;
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int data_in_index;
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int data_out_index;
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|
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qemu_irq irq; |
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uint8_t autopoll; |
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uint8_t data_in[128];
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uint8_t data_out[16];
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QEMUTimer *adb_poll_timer; |
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} CUDAState; |
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|
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static CUDAState cuda_state;
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ADBBusState adb_bus; |
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|
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static void cuda_update(CUDAState *s); |
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static void cuda_receive_packet_from_host(CUDAState *s, |
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const uint8_t *data, int len); |
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static void cuda_timer_update(CUDAState *s, CUDATimer *ti, |
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int64_t current_time); |
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|
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static void cuda_update_irq(CUDAState *s) |
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{
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if (s->ifr & s->ier & (SR_INT | T1_INT)) {
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qemu_irq_raise(s->irq); |
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} else {
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qemu_irq_lower(s->irq); |
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} |
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} |
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|
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static unsigned int get_counter(CUDATimer *s) |
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{
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int64_t d; |
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unsigned int counter; |
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d = muldiv64(qemu_get_clock(vm_clock) - s->load_time, |
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CUDA_TIMER_FREQ, ticks_per_sec); |
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if (s->index == 0) { |
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/* the timer goes down from latch to -1 (period of latch + 2) */
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if (d <= (s->counter_value + 1)) { |
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counter = (s->counter_value - d) & 0xffff;
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} else {
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counter = (d - (s->counter_value + 1)) % (s->latch + 2); |
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counter = (s->latch - counter) & 0xffff;
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} |
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} else {
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counter = (s->counter_value - d) & 0xffff;
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} |
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return counter;
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} |
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static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) |
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{
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#ifdef DEBUG_CUDA
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printf("cuda: T%d.counter=%d\n",
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1 + (ti->timer == NULL), val); |
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#endif
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ti->load_time = qemu_get_clock(vm_clock); |
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ti->counter_value = val; |
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cuda_timer_update(s, ti, ti->load_time); |
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} |
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static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
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{
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int64_t d, next_time; |
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unsigned int counter; |
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/* current counter value */
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d = muldiv64(current_time - s->load_time, |
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CUDA_TIMER_FREQ, ticks_per_sec); |
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/* the timer goes down from latch to -1 (period of latch + 2) */
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if (d <= (s->counter_value + 1)) { |
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counter = (s->counter_value - d) & 0xffff;
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} else {
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counter = (d - (s->counter_value + 1)) % (s->latch + 2); |
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counter = (s->latch - counter) & 0xffff;
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} |
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/* Note: we consider the irq is raised on 0 */
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if (counter == 0xffff) { |
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next_time = d + s->latch + 1;
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} else if (counter == 0) { |
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next_time = d + s->latch + 2;
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} else {
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next_time = d + counter; |
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} |
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#if 0
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#ifdef DEBUG_CUDA
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printf("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
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s->latch, d, next_time - d);
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#endif
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#endif
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next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) + |
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s->load_time; |
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if (next_time <= current_time)
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next_time = current_time + 1;
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return next_time;
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} |
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|
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static void cuda_timer_update(CUDAState *s, CUDATimer *ti, |
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int64_t current_time) |
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{
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if (!ti->timer)
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return;
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if ((s->acr & T1MODE) != T1MODE_CONT) {
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qemu_del_timer(ti->timer); |
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} else {
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ti->next_irq_time = get_next_irq_time(ti, current_time); |
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qemu_mod_timer(ti->timer, ti->next_irq_time); |
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} |
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} |
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|
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static void cuda_timer1(void *opaque) |
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{
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CUDAState *s = opaque; |
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CUDATimer *ti = &s->timers[0];
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|
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cuda_timer_update(s, ti, ti->next_irq_time); |
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s->ifr |= T1_INT; |
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cuda_update_irq(s); |
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} |
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|
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static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr) |
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{
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CUDAState *s = opaque; |
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uint32_t val; |
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|
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addr = (addr >> 9) & 0xf; |
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switch(addr) {
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case 0: |
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val = s->b; |
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break;
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case 1: |
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val = s->a; |
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break;
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case 2: |
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val = s->dirb; |
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break;
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case 3: |
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val = s->dira; |
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break;
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case 4: |
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val = get_counter(&s->timers[0]) & 0xff; |
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s->ifr &= ~T1_INT; |
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cuda_update_irq(s); |
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break;
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case 5: |
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val = get_counter(&s->timers[0]) >> 8; |
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cuda_update_irq(s); |
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break;
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case 6: |
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val = s->timers[0].latch & 0xff; |
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break;
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case 7: |
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/* XXX: check this */
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val = (s->timers[0].latch >> 8) & 0xff; |
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break;
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case 8: |
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val = get_counter(&s->timers[1]) & 0xff; |
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s->ifr &= ~T2_INT; |
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break;
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case 9: |
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val = get_counter(&s->timers[1]) >> 8; |
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break;
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case 10: |
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val = s->sr; |
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s->ifr &= ~SR_INT; |
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cuda_update_irq(s); |
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break;
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case 11: |
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val = s->acr; |
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break;
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case 12: |
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val = s->pcr; |
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break;
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case 13: |
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val = s->ifr; |
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if (s->ifr & s->ier)
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val |= 0x80;
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break;
|
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case 14: |
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val = s->ier | 0x80;
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break;
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default:
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case 15: |
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val = s->anh; |
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break;
|
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} |
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#ifdef DEBUG_CUDA
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if (addr != 13 || val != 0) |
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printf("cuda: read: reg=0x%x val=%02x\n", addr, val);
|
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#endif
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return val;
|
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} |
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|
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static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
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{
|
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CUDAState *s = opaque; |
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|
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addr = (addr >> 9) & 0xf; |
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#ifdef DEBUG_CUDA
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printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
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#endif
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switch(addr) {
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case 0: |
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s->b = val; |
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cuda_update(s); |
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break;
|
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case 1: |
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s->a = val; |
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break;
|
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case 2: |
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s->dirb = val; |
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break;
|
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case 3: |
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s->dira = val; |
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break;
|
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case 4: |
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s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
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cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
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break;
|
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case 5: |
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s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
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s->ifr &= ~T1_INT; |
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set_counter(s, &s->timers[0], s->timers[0].latch); |
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break;
|
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case 6: |
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s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
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cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
|
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break;
|
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case 7: |
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s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
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s->ifr &= ~T1_INT; |
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cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
|
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break;
|
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case 8: |
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s->timers[1].latch = val;
|
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set_counter(s, &s->timers[1], val);
|
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break;
|
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case 9: |
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set_counter(s, &s->timers[1], (val << 8) | s->timers[1].latch); |
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break;
|
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case 10: |
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s->sr = val; |
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break;
|
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case 11: |
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s->acr = val; |
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cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
|
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cuda_update(s); |
| 376 |
break;
|
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case 12: |
| 378 |
s->pcr = val; |
| 379 |
break;
|
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case 13: |
| 381 |
/* reset bits */
|
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s->ifr &= ~val; |
| 383 |
cuda_update_irq(s); |
| 384 |
break;
|
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case 14: |
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if (val & IER_SET) {
|
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/* set bits */
|
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s->ier |= val & 0x7f;
|
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} else {
|
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/* reset bits */
|
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s->ier &= ~val; |
| 392 |
} |
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cuda_update_irq(s); |
| 394 |
break;
|
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default:
|
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case 15: |
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s->anh = val; |
| 398 |
break;
|
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} |
| 400 |
} |
| 401 |
|
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/* NOTE: TIP and TREQ are negated */
|
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static void cuda_update(CUDAState *s) |
| 404 |
{
|
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int packet_received, len;
|
| 406 |
|
| 407 |
packet_received = 0;
|
| 408 |
if (!(s->b & TIP)) {
|
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/* transfer requested from host */
|
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|
| 411 |
if (s->acr & SR_OUT) {
|
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/* data output */
|
| 413 |
if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
|
| 414 |
if (s->data_out_index < sizeof(s->data_out)) { |
| 415 |
#ifdef DEBUG_CUDA
|
| 416 |
printf("cuda: send: %02x\n", s->sr);
|
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#endif
|
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s->data_out[s->data_out_index++] = s->sr; |
| 419 |
s->ifr |= SR_INT; |
| 420 |
cuda_update_irq(s); |
| 421 |
} |
| 422 |
} |
| 423 |
} else {
|
| 424 |
if (s->data_in_index < s->data_in_size) {
|
| 425 |
/* data input */
|
| 426 |
if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
|
| 427 |
s->sr = s->data_in[s->data_in_index++]; |
| 428 |
#ifdef DEBUG_CUDA
|
| 429 |
printf("cuda: recv: %02x\n", s->sr);
|
| 430 |
#endif
|
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/* indicate end of transfer */
|
| 432 |
if (s->data_in_index >= s->data_in_size) {
|
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s->b = (s->b | TREQ); |
| 434 |
} |
| 435 |
s->ifr |= SR_INT; |
| 436 |
cuda_update_irq(s); |
| 437 |
} |
| 438 |
} |
| 439 |
} |
| 440 |
} else {
|
| 441 |
/* no transfer requested: handle sync case */
|
| 442 |
if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
|
| 443 |
/* update TREQ state each time TACK change state */
|
| 444 |
if (s->b & TACK)
|
| 445 |
s->b = (s->b | TREQ); |
| 446 |
else
|
| 447 |
s->b = (s->b & ~TREQ); |
| 448 |
s->ifr |= SR_INT; |
| 449 |
cuda_update_irq(s); |
| 450 |
} else {
|
| 451 |
if (!(s->last_b & TIP)) {
|
| 452 |
/* handle end of host to cuda transfer */
|
| 453 |
packet_received = (s->data_out_index > 0);
|
| 454 |
/* always an IRQ at the end of transfer */
|
| 455 |
s->ifr |= SR_INT; |
| 456 |
cuda_update_irq(s); |
| 457 |
} |
| 458 |
/* signal if there is data to read */
|
| 459 |
if (s->data_in_index < s->data_in_size) {
|
| 460 |
s->b = (s->b & ~TREQ); |
| 461 |
} |
| 462 |
} |
| 463 |
} |
| 464 |
|
| 465 |
s->last_acr = s->acr; |
| 466 |
s->last_b = s->b; |
| 467 |
|
| 468 |
/* NOTE: cuda_receive_packet_from_host() can call cuda_update()
|
| 469 |
recursively */
|
| 470 |
if (packet_received) {
|
| 471 |
len = s->data_out_index; |
| 472 |
s->data_out_index = 0;
|
| 473 |
cuda_receive_packet_from_host(s, s->data_out, len); |
| 474 |
} |
| 475 |
} |
| 476 |
|
| 477 |
static void cuda_send_packet_to_host(CUDAState *s, |
| 478 |
const uint8_t *data, int len) |
| 479 |
{
|
| 480 |
#ifdef DEBUG_CUDA_PACKET
|
| 481 |
{
|
| 482 |
int i;
|
| 483 |
printf("cuda_send_packet_to_host:\n");
|
| 484 |
for(i = 0; i < len; i++) |
| 485 |
printf(" %02x", data[i]);
|
| 486 |
printf("\n");
|
| 487 |
} |
| 488 |
#endif
|
| 489 |
memcpy(s->data_in, data, len); |
| 490 |
s->data_in_size = len; |
| 491 |
s->data_in_index = 0;
|
| 492 |
cuda_update(s); |
| 493 |
s->ifr |= SR_INT; |
| 494 |
cuda_update_irq(s); |
| 495 |
} |
| 496 |
|
| 497 |
static void cuda_adb_poll(void *opaque) |
| 498 |
{
|
| 499 |
CUDAState *s = opaque; |
| 500 |
uint8_t obuf[ADB_MAX_OUT_LEN + 2];
|
| 501 |
int olen;
|
| 502 |
|
| 503 |
olen = adb_poll(&adb_bus, obuf + 2);
|
| 504 |
if (olen > 0) { |
| 505 |
obuf[0] = ADB_PACKET;
|
| 506 |
obuf[1] = 0x40; /* polled data */ |
| 507 |
cuda_send_packet_to_host(s, obuf, olen + 2);
|
| 508 |
} |
| 509 |
qemu_mod_timer(s->adb_poll_timer, |
| 510 |
qemu_get_clock(vm_clock) + |
| 511 |
(ticks_per_sec / CUDA_ADB_POLL_FREQ)); |
| 512 |
} |
| 513 |
|
| 514 |
static void cuda_receive_packet(CUDAState *s, |
| 515 |
const uint8_t *data, int len) |
| 516 |
{
|
| 517 |
uint8_t obuf[16];
|
| 518 |
int ti, autopoll;
|
| 519 |
|
| 520 |
switch(data[0]) { |
| 521 |
case CUDA_AUTOPOLL:
|
| 522 |
autopoll = (data[1] != 0); |
| 523 |
if (autopoll != s->autopoll) {
|
| 524 |
s->autopoll = autopoll; |
| 525 |
if (autopoll) {
|
| 526 |
qemu_mod_timer(s->adb_poll_timer, |
| 527 |
qemu_get_clock(vm_clock) + |
| 528 |
(ticks_per_sec / CUDA_ADB_POLL_FREQ)); |
| 529 |
} else {
|
| 530 |
qemu_del_timer(s->adb_poll_timer); |
| 531 |
} |
| 532 |
} |
| 533 |
obuf[0] = CUDA_PACKET;
|
| 534 |
obuf[1] = data[1]; |
| 535 |
cuda_send_packet_to_host(s, obuf, 2);
|
| 536 |
break;
|
| 537 |
case CUDA_GET_TIME:
|
| 538 |
case CUDA_SET_TIME:
|
| 539 |
/* XXX: add time support ? */
|
| 540 |
ti = time(NULL) + RTC_OFFSET;
|
| 541 |
obuf[0] = CUDA_PACKET;
|
| 542 |
obuf[1] = 0; |
| 543 |
obuf[2] = 0; |
| 544 |
obuf[3] = ti >> 24; |
| 545 |
obuf[4] = ti >> 16; |
| 546 |
obuf[5] = ti >> 8; |
| 547 |
obuf[6] = ti;
|
| 548 |
cuda_send_packet_to_host(s, obuf, 7);
|
| 549 |
break;
|
| 550 |
case CUDA_FILE_SERVER_FLAG:
|
| 551 |
case CUDA_SET_DEVICE_LIST:
|
| 552 |
case CUDA_SET_AUTO_RATE:
|
| 553 |
case CUDA_SET_POWER_MESSAGES:
|
| 554 |
obuf[0] = CUDA_PACKET;
|
| 555 |
obuf[1] = 0; |
| 556 |
cuda_send_packet_to_host(s, obuf, 2);
|
| 557 |
break;
|
| 558 |
case CUDA_POWERDOWN:
|
| 559 |
obuf[0] = CUDA_PACKET;
|
| 560 |
obuf[1] = 0; |
| 561 |
cuda_send_packet_to_host(s, obuf, 2);
|
| 562 |
qemu_system_shutdown_request(); |
| 563 |
break;
|
| 564 |
case CUDA_RESET_SYSTEM:
|
| 565 |
obuf[0] = CUDA_PACKET;
|
| 566 |
obuf[1] = 0; |
| 567 |
cuda_send_packet_to_host(s, obuf, 2);
|
| 568 |
qemu_system_reset_request(); |
| 569 |
break;
|
| 570 |
default:
|
| 571 |
break;
|
| 572 |
} |
| 573 |
} |
| 574 |
|
| 575 |
static void cuda_receive_packet_from_host(CUDAState *s, |
| 576 |
const uint8_t *data, int len) |
| 577 |
{
|
| 578 |
#ifdef DEBUG_CUDA_PACKET
|
| 579 |
{
|
| 580 |
int i;
|
| 581 |
printf("cuda_receive_packet_from_host:\n");
|
| 582 |
for(i = 0; i < len; i++) |
| 583 |
printf(" %02x", data[i]);
|
| 584 |
printf("\n");
|
| 585 |
} |
| 586 |
#endif
|
| 587 |
switch(data[0]) { |
| 588 |
case ADB_PACKET:
|
| 589 |
{
|
| 590 |
uint8_t obuf[ADB_MAX_OUT_LEN + 2];
|
| 591 |
int olen;
|
| 592 |
olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1); |
| 593 |
if (olen > 0) { |
| 594 |
obuf[0] = ADB_PACKET;
|
| 595 |
obuf[1] = 0x00; |
| 596 |
} else {
|
| 597 |
/* error */
|
| 598 |
obuf[0] = ADB_PACKET;
|
| 599 |
obuf[1] = -olen;
|
| 600 |
olen = 0;
|
| 601 |
} |
| 602 |
cuda_send_packet_to_host(s, obuf, olen + 2);
|
| 603 |
} |
| 604 |
break;
|
| 605 |
case CUDA_PACKET:
|
| 606 |
cuda_receive_packet(s, data + 1, len - 1); |
| 607 |
break;
|
| 608 |
} |
| 609 |
} |
| 610 |
|
| 611 |
static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
| 612 |
{
|
| 613 |
} |
| 614 |
|
| 615 |
static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
| 616 |
{
|
| 617 |
} |
| 618 |
|
| 619 |
static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr) |
| 620 |
{
|
| 621 |
return 0; |
| 622 |
} |
| 623 |
|
| 624 |
static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr) |
| 625 |
{
|
| 626 |
return 0; |
| 627 |
} |
| 628 |
|
| 629 |
static CPUWriteMemoryFunc *cuda_write[] = {
|
| 630 |
&cuda_writeb, |
| 631 |
&cuda_writew, |
| 632 |
&cuda_writel, |
| 633 |
}; |
| 634 |
|
| 635 |
static CPUReadMemoryFunc *cuda_read[] = {
|
| 636 |
&cuda_readb, |
| 637 |
&cuda_readw, |
| 638 |
&cuda_readl, |
| 639 |
}; |
| 640 |
|
| 641 |
void cuda_init (int *cuda_mem_index, qemu_irq irq) |
| 642 |
{
|
| 643 |
CUDAState *s = &cuda_state; |
| 644 |
|
| 645 |
s->irq = irq; |
| 646 |
|
| 647 |
s->timers[0].index = 0; |
| 648 |
s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
|
| 649 |
s->timers[0].latch = 0xffff; |
| 650 |
set_counter(s, &s->timers[0], 0xffff); |
| 651 |
|
| 652 |
s->timers[1].index = 1; |
| 653 |
s->timers[1].latch = 0; |
| 654 |
// s->ier = T1_INT | SR_INT;
|
| 655 |
s->ier = 0;
|
| 656 |
set_counter(s, &s->timers[1], 0xffff); |
| 657 |
|
| 658 |
s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s); |
| 659 |
*cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
|
| 660 |
} |