Statistics
| Branch: | Revision:

root / hw / pci.h @ 87ecb68b

History | View | Annotate | Download (4.5 kB)

1
#ifndef QEMU_PCI_H
2
#define QEMU_PCI_H
3

    
4
/* PCI includes legacy ISA access.  */
5
#include "isa.h"
6

    
7
/* PCI bus */
8

    
9
extern target_phys_addr_t pci_mem_base;
10

    
11
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
12
                                uint32_t address, uint32_t data, int len);
13
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
14
                                   uint32_t address, int len);
15
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
16
                                uint32_t addr, uint32_t size, int type);
17

    
18
#define PCI_ADDRESS_SPACE_MEM                0x00
19
#define PCI_ADDRESS_SPACE_IO                0x01
20
#define PCI_ADDRESS_SPACE_MEM_PREFETCH        0x08
21

    
22
typedef struct PCIIORegion {
23
    uint32_t addr; /* current PCI mapping address. -1 means not mapped */
24
    uint32_t size;
25
    uint8_t type;
26
    PCIMapIORegionFunc *map_func;
27
} PCIIORegion;
28

    
29
#define PCI_ROM_SLOT 6
30
#define PCI_NUM_REGIONS 7
31

    
32
#define PCI_DEVICES_MAX 64
33

    
34
#define PCI_VENDOR_ID                0x00        /* 16 bits */
35
#define PCI_DEVICE_ID                0x02        /* 16 bits */
36
#define PCI_COMMAND                0x04        /* 16 bits */
37
#define  PCI_COMMAND_IO                0x1        /* Enable response in I/O space */
38
#define  PCI_COMMAND_MEMORY        0x2        /* Enable response in Memory space */
39
#define PCI_CLASS_DEVICE        0x0a    /* Device class */
40
#define PCI_INTERRUPT_LINE        0x3c        /* 8 bits */
41
#define PCI_INTERRUPT_PIN        0x3d        /* 8 bits */
42
#define PCI_MIN_GNT                0x3e        /* 8 bits */
43
#define PCI_MAX_LAT                0x3f        /* 8 bits */
44

    
45
struct PCIDevice {
46
    /* PCI config space */
47
    uint8_t config[256];
48

    
49
    /* the following fields are read only */
50
    PCIBus *bus;
51
    int devfn;
52
    char name[64];
53
    PCIIORegion io_regions[PCI_NUM_REGIONS];
54

    
55
    /* do not access the following fields */
56
    PCIConfigReadFunc *config_read;
57
    PCIConfigWriteFunc *config_write;
58
    /* ??? This is a PC-specific hack, and should be removed.  */
59
    int irq_index;
60

    
61
    /* IRQ objects for the INTA-INTD pins.  */
62
    qemu_irq *irq;
63

    
64
    /* Current IRQ levels.  Used internally by the generic PCI code.  */
65
    int irq_state[4];
66
};
67

    
68
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
69
                               int instance_size, int devfn,
70
                               PCIConfigReadFunc *config_read,
71
                               PCIConfigWriteFunc *config_write);
72

    
73
void pci_register_io_region(PCIDevice *pci_dev, int region_num,
74
                            uint32_t size, int type,
75
                            PCIMapIORegionFunc *map_func);
76

    
77
uint32_t pci_default_read_config(PCIDevice *d,
78
                                 uint32_t address, int len);
79
void pci_default_write_config(PCIDevice *d,
80
                              uint32_t address, uint32_t val, int len);
81
void pci_device_save(PCIDevice *s, QEMUFile *f);
82
int pci_device_load(PCIDevice *s, QEMUFile *f);
83

    
84
typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
85
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
86
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
87
                         qemu_irq *pic, int devfn_min, int nirq);
88

    
89
void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
90
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
91
uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
92
int pci_bus_num(PCIBus *s);
93
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
94

    
95
void pci_info(void);
96
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
97
                        pci_map_irq_fn map_irq, const char *name);
98

    
99
/* lsi53c895a.c */
100
void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
101
void *lsi_scsi_init(PCIBus *bus, int devfn);
102

    
103
/* vmware_vga.c */
104
void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
105
                     unsigned long vga_ram_offset, int vga_ram_size);
106

    
107
/* usb-uhci.c */
108
void usb_uhci_piix3_init(PCIBus *bus, int devfn);
109
void usb_uhci_piix4_init(PCIBus *bus, int devfn);
110

    
111
/* usb-ohci.c */
112
void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);
113

    
114
/* eepro100.c */
115

    
116
void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
117
void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
118
void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
119

    
120
/* ne2000.c */
121

    
122
void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
123

    
124
/* rtl8139.c */
125

    
126
void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
127

    
128
/* pcnet.c */
129
void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
130

    
131
/* prep_pci.c */
132
PCIBus *pci_prep_init(qemu_irq *pic);
133

    
134
/* apb_pci.c */
135
PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
136
                     qemu_irq *pic);
137

    
138
#endif