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/*
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 * QEMU PowerPC 4xx embedded processors shared devices emulation
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 *
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 * Copyright (c) 2007 Jocelyn Mayer
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "hw.h"
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#include "ppc.h"
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#include "ppc4xx.h"
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#include "sysemu.h"
28

    
29
extern int loglevel;
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extern FILE *logfile;
31

    
32
//#define DEBUG_MMIO
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#define DEBUG_UIC
34

    
35
/*****************************************************************************/
36
/* Generic PowerPC 4xx processor instanciation */
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CPUState *ppc4xx_init (const unsigned char *cpu_model,
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                       clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
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                       uint32_t sysclk)
40
{
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    CPUState *env;
42

    
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    /* init CPUs */
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    env = cpu_init(cpu_model);
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    if (!env) {
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        fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
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                cpu_model);
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        exit(1);
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    }
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    cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
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    cpu_clk->opaque = env;
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    /* Set time-base frequency to sysclk */
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    tb_clk->cb = ppc_emb_timers_init(env, sysclk);
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    tb_clk->opaque = env;
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    ppc_dcr_init(env, NULL, NULL);
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    /* Register qemu callbacks */
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    qemu_register_reset(&cpu_ppc_reset, env);
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    register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
59

    
60
    return env;
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}
62

    
63
/*****************************************************************************/
64
/* Fake device used to map multiple devices in a single memory page */
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#define MMIO_AREA_BITS 8
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#define MMIO_AREA_LEN (1 << MMIO_AREA_BITS)
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#define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS))
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#define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1))
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struct ppc4xx_mmio_t {
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    target_phys_addr_t base;
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    CPUReadMemoryFunc **mem_read[MMIO_AREA_NB];
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    CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB];
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    void *opaque[MMIO_AREA_NB];
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};
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static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr)
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{
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#ifdef DEBUG_UNASSIGNED
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    ppc4xx_mmio_t *mmio;
80

    
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    mmio = opaque;
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    printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n",
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           addr, mmio->base);
84
#endif
85

    
86
    return 0;
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}
88

    
89
static void unassigned_mmio_writeb (void *opaque,
90
                                    target_phys_addr_t addr, uint32_t val)
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{
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#ifdef DEBUG_UNASSIGNED
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    ppc4xx_mmio_t *mmio;
94

    
95
    mmio = opaque;
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    printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n",
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           addr, val, mmio->base);
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#endif
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}
100

    
101
static CPUReadMemoryFunc *unassigned_mmio_read[3] = {
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    unassigned_mmio_readb,
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    unassigned_mmio_readb,
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    unassigned_mmio_readb,
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};
106

    
107
static CPUWriteMemoryFunc *unassigned_mmio_write[3] = {
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    unassigned_mmio_writeb,
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    unassigned_mmio_writeb,
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    unassigned_mmio_writeb,
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};
112

    
113
static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
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                              target_phys_addr_t addr, int len)
115
{
116
    CPUReadMemoryFunc **mem_read;
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    uint32_t ret;
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    int idx;
119

    
120
    idx = MMIO_IDX(addr - mmio->base);
121
#if defined(DEBUG_MMIO)
122
    printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__,
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           mmio, len, addr, idx);
124
#endif
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    mem_read = mmio->mem_read[idx];
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    ret = (*mem_read[len])(mmio->opaque[idx], addr - mmio->base);
127

    
128
    return ret;
129
}
130

    
131
static void mmio_writelen (ppc4xx_mmio_t *mmio,
132
                           target_phys_addr_t addr, uint32_t value, int len)
133
{
134
    CPUWriteMemoryFunc **mem_write;
135
    int idx;
136

    
137
    idx = MMIO_IDX(addr - mmio->base);
138
#if defined(DEBUG_MMIO)
139
    printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08x\n", __func__,
140
           mmio, len, addr, idx, value);
141
#endif
142
    mem_write = mmio->mem_write[idx];
143
    (*mem_write[len])(mmio->opaque[idx], addr - mmio->base, value);
144
}
145

    
146
static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr)
147
{
148
#if defined(DEBUG_MMIO)
149
    printf("%s: addr " PADDRX "\n", __func__, addr);
150
#endif
151

    
152
    return mmio_readlen(opaque, addr, 0);
153
}
154

    
155
static void mmio_writeb (void *opaque,
156
                         target_phys_addr_t addr, uint32_t value)
157
{
158
#if defined(DEBUG_MMIO)
159
    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
160
#endif
161
    mmio_writelen(opaque, addr, value, 0);
162
}
163

    
164
static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr)
165
{
166
#if defined(DEBUG_MMIO)
167
    printf("%s: addr " PADDRX "\n", __func__, addr);
168
#endif
169

    
170
    return mmio_readlen(opaque, addr, 1);
171
}
172

    
173
static void mmio_writew (void *opaque,
174
                         target_phys_addr_t addr, uint32_t value)
175
{
176
#if defined(DEBUG_MMIO)
177
    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
178
#endif
179
    mmio_writelen(opaque, addr, value, 1);
180
}
181

    
182
static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr)
183
{
184
#if defined(DEBUG_MMIO)
185
    printf("%s: addr " PADDRX "\n", __func__, addr);
186
#endif
187

    
188
    return mmio_readlen(opaque, addr, 2);
189
}
190

    
191
static void mmio_writel (void *opaque,
192
                         target_phys_addr_t addr, uint32_t value)
193
{
194
#if defined(DEBUG_MMIO)
195
    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
196
#endif
197
    mmio_writelen(opaque, addr, value, 2);
198
}
199

    
200
static CPUReadMemoryFunc *mmio_read[] = {
201
    &mmio_readb,
202
    &mmio_readw,
203
    &mmio_readl,
204
};
205

    
206
static CPUWriteMemoryFunc *mmio_write[] = {
207
    &mmio_writeb,
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    &mmio_writew,
209
    &mmio_writel,
210
};
211

    
212
int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
213
                          target_phys_addr_t offset, uint32_t len,
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                          CPUReadMemoryFunc **mem_read,
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                          CPUWriteMemoryFunc **mem_write, void *opaque)
216
{
217
    uint32_t end;
218
    int idx, eidx;
219

    
220
    if ((offset + len) > TARGET_PAGE_SIZE)
221
        return -1;
222
    idx = MMIO_IDX(offset);
223
    end = offset + len - 1;
224
    eidx = MMIO_IDX(end);
225
#if defined(DEBUG_MMIO)
226
    printf("%s: offset %08x len %08x %08x %d %d\n", __func__, offset, len,
227
           end, idx, eidx);
228
#endif
229
    for (; idx <= eidx; idx++) {
230
        mmio->mem_read[idx] = mem_read;
231
        mmio->mem_write[idx] = mem_write;
232
        mmio->opaque[idx] = opaque;
233
    }
234

    
235
    return 0;
236
}
237

    
238
ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base)
239
{
240
    ppc4xx_mmio_t *mmio;
241
    int mmio_memory;
242

    
243
    mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
244
    if (mmio != NULL) {
245
        mmio->base = base;
246
        mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
247
#if defined(DEBUG_MMIO)
248
        printf("%s: %p base %08x len %08x %d\n", __func__,
249
               mmio, base, TARGET_PAGE_SIZE, mmio_memory);
250
#endif
251
        cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);
252
        ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
253
                             unassigned_mmio_read, unassigned_mmio_write,
254
                             mmio);
255
    }
256

    
257
    return mmio;
258
}
259

    
260
/*****************************************************************************/
261
/* "Universal" Interrupt controller */
262
enum {
263
    DCR_UICSR  = 0x000,
264
    DCR_UICSRS = 0x001,
265
    DCR_UICER  = 0x002,
266
    DCR_UICCR  = 0x003,
267
    DCR_UICPR  = 0x004,
268
    DCR_UICTR  = 0x005,
269
    DCR_UICMSR = 0x006,
270
    DCR_UICVR  = 0x007,
271
    DCR_UICVCR = 0x008,
272
    DCR_UICMAX = 0x009,
273
};
274

    
275
#define UIC_MAX_IRQ 32
276
typedef struct ppcuic_t ppcuic_t;
277
struct ppcuic_t {
278
    uint32_t dcr_base;
279
    int use_vectors;
280
    uint32_t uicsr;  /* Status register */
281
    uint32_t uicer;  /* Enable register */
282
    uint32_t uiccr;  /* Critical register */
283
    uint32_t uicpr;  /* Polarity register */
284
    uint32_t uictr;  /* Triggering register */
285
    uint32_t uicvcr; /* Vector configuration register */
286
    uint32_t uicvr;
287
    qemu_irq *irqs;
288
};
289

    
290
static void ppcuic_trigger_irq (ppcuic_t *uic)
291
{
292
    uint32_t ir, cr;
293
    int start, end, inc, i;
294

    
295
    /* Trigger interrupt if any is pending */
296
    ir = uic->uicsr & uic->uicer & (~uic->uiccr);
297
    cr = uic->uicsr & uic->uicer & uic->uiccr;
298
#ifdef DEBUG_UIC
299
    if (loglevel & CPU_LOG_INT) {
300
        fprintf(logfile, "%s: uicsr %08x uicer %08x uiccr %08x\n"
301
                "   %08x ir %08x cr %08x\n", __func__,
302
                uic->uicsr, uic->uicer, uic->uiccr,
303
                uic->uicsr & uic->uicer, ir, cr);
304
    }
305
#endif
306
    if (ir != 0x0000000) {
307
#ifdef DEBUG_UIC
308
        if (loglevel & CPU_LOG_INT) {
309
            fprintf(logfile, "Raise UIC interrupt\n");
310
        }
311
#endif
312
        qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
313
    } else {
314
#ifdef DEBUG_UIC
315
        if (loglevel & CPU_LOG_INT) {
316
            fprintf(logfile, "Lower UIC interrupt\n");
317
        }
318
#endif
319
        qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
320
    }
321
    /* Trigger critical interrupt if any is pending and update vector */
322
    if (cr != 0x0000000) {
323
        qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
324
        if (uic->use_vectors) {
325
            /* Compute critical IRQ vector */
326
            if (uic->uicvcr & 1) {
327
                start = 31;
328
                end = 0;
329
                inc = -1;
330
            } else {
331
                start = 0;
332
                end = 31;
333
                inc = 1;
334
            }
335
            uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
336
            for (i = start; i <= end; i += inc) {
337
                if (cr & (1 << i)) {
338
                    uic->uicvr += (i - start) * 512 * inc;
339
                    break;
340
                }
341
            }
342
        }
343
#ifdef DEBUG_UIC
344
        if (loglevel & CPU_LOG_INT) {
345
            fprintf(logfile, "Raise UIC critical interrupt - vector %08x\n",
346
                    uic->uicvr);
347
        }
348
#endif
349
    } else {
350
#ifdef DEBUG_UIC
351
        if (loglevel & CPU_LOG_INT) {
352
            fprintf(logfile, "Lower UIC critical interrupt\n");
353
        }
354
#endif
355
        qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
356
        uic->uicvr = 0x00000000;
357
    }
358
}
359

    
360
static void ppcuic_set_irq (void *opaque, int irq_num, int level)
361
{
362
    ppcuic_t *uic;
363
    uint32_t mask, sr;
364

    
365
    uic = opaque;
366
    mask = 1 << irq_num;
367
#ifdef DEBUG_UIC
368
    if (loglevel & CPU_LOG_INT) {
369
        fprintf(logfile, "%s: irq %d level %d uicsr %08x mask %08x => %08x "
370
                "%08x\n", __func__, irq_num, level,
371
                uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
372
    }
373
#endif
374
    if (irq_num < 0 || irq_num > 31)
375
        return;
376
    sr = uic->uicsr;
377
    if (!(uic->uicpr & mask)) {
378
        /* Negatively asserted IRQ */
379
        level = level == 0 ? 1 : 0;
380
    }
381
    /* Update status register */
382
    if (uic->uictr & mask) {
383
        /* Edge sensitive interrupt */
384
        if (level == 1)
385
            uic->uicsr |= mask;
386
    } else {
387
        /* Level sensitive interrupt */
388
        if (level == 1)
389
            uic->uicsr |= mask;
390
        else
391
            uic->uicsr &= ~mask;
392
    }
393
#ifdef DEBUG_UIC
394
    if (loglevel & CPU_LOG_INT) {
395
        fprintf(logfile, "%s: irq %d level %d sr %08x => %08x\n", __func__,
396
                irq_num, level, uic->uicsr, sr);
397
    }
398
#endif
399
    if (sr != uic->uicsr)
400
        ppcuic_trigger_irq(uic);
401
}
402

    
403
static target_ulong dcr_read_uic (void *opaque, int dcrn)
404
{
405
    ppcuic_t *uic;
406
    target_ulong ret;
407

    
408
    uic = opaque;
409
    dcrn -= uic->dcr_base;
410
    switch (dcrn) {
411
    case DCR_UICSR:
412
    case DCR_UICSRS:
413
        ret = uic->uicsr;
414
        break;
415
    case DCR_UICER:
416
        ret = uic->uicer;
417
        break;
418
    case DCR_UICCR:
419
        ret = uic->uiccr;
420
        break;
421
    case DCR_UICPR:
422
        ret = uic->uicpr;
423
        break;
424
    case DCR_UICTR:
425
        ret = uic->uictr;
426
        break;
427
    case DCR_UICMSR:
428
        ret = uic->uicsr & uic->uicer;
429
        break;
430
    case DCR_UICVR:
431
        if (!uic->use_vectors)
432
            goto no_read;
433
        ret = uic->uicvr;
434
        break;
435
    case DCR_UICVCR:
436
        if (!uic->use_vectors)
437
            goto no_read;
438
        ret = uic->uicvcr;
439
        break;
440
    default:
441
    no_read:
442
        ret = 0x00000000;
443
        break;
444
    }
445

    
446
    return ret;
447
}
448

    
449
static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
450
{
451
    ppcuic_t *uic;
452

    
453
    uic = opaque;
454
    dcrn -= uic->dcr_base;
455
#ifdef DEBUG_UIC
456
    if (loglevel & CPU_LOG_INT) {
457
        fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
458
    }
459
#endif
460
    switch (dcrn) {
461
    case DCR_UICSR:
462
        uic->uicsr &= ~val;
463
        ppcuic_trigger_irq(uic);
464
        break;
465
    case DCR_UICSRS:
466
        uic->uicsr |= val;
467
        ppcuic_trigger_irq(uic);
468
        break;
469
    case DCR_UICER:
470
        uic->uicer = val;
471
        ppcuic_trigger_irq(uic);
472
        break;
473
    case DCR_UICCR:
474
        uic->uiccr = val;
475
        ppcuic_trigger_irq(uic);
476
        break;
477
    case DCR_UICPR:
478
        uic->uicpr = val;
479
        ppcuic_trigger_irq(uic);
480
        break;
481
    case DCR_UICTR:
482
        uic->uictr = val;
483
        ppcuic_trigger_irq(uic);
484
        break;
485
    case DCR_UICMSR:
486
        break;
487
    case DCR_UICVR:
488
        break;
489
    case DCR_UICVCR:
490
        uic->uicvcr = val & 0xFFFFFFFD;
491
        ppcuic_trigger_irq(uic);
492
        break;
493
    }
494
}
495

    
496
static void ppcuic_reset (void *opaque)
497
{
498
    ppcuic_t *uic;
499

    
500
    uic = opaque;
501
    uic->uiccr = 0x00000000;
502
    uic->uicer = 0x00000000;
503
    uic->uicpr = 0x00000000;
504
    uic->uicsr = 0x00000000;
505
    uic->uictr = 0x00000000;
506
    if (uic->use_vectors) {
507
        uic->uicvcr = 0x00000000;
508
        uic->uicvr = 0x0000000;
509
    }
510
}
511

    
512
qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
513
                       uint32_t dcr_base, int has_ssr, int has_vr)
514
{
515
    ppcuic_t *uic;
516
    int i;
517

    
518
    uic = qemu_mallocz(sizeof(ppcuic_t));
519
    if (uic != NULL) {
520
        uic->dcr_base = dcr_base;
521
        uic->irqs = irqs;
522
        if (has_vr)
523
            uic->use_vectors = 1;
524
        for (i = 0; i < DCR_UICMAX; i++) {
525
            ppc_dcr_register(env, dcr_base + i, uic,
526
                             &dcr_read_uic, &dcr_write_uic);
527
        }
528
        qemu_register_reset(ppcuic_reset, uic);
529
        ppcuic_reset(uic);
530
    }
531

    
532
    return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
533
}