Revision 897b4c6c

b/hw/m48t59.c
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}
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/* Direct access to NVRAM */
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void m48t59_write (m48t59_t *NVRAM, uint32_t addr, uint32_t val)
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void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
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{
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    m48t59_t *NVRAM = opaque;
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    struct tm tm;
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    int tmp;
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......
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    }
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}
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uint32_t m48t59_read (m48t59_t *NVRAM, uint32_t addr)
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uint32_t m48t59_read (void *opaque, uint32_t addr)
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{
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    m48t59_t *NVRAM = opaque;
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    struct tm tm;
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    uint32_t retval = 0xFF;
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......
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    return retval;
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}
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void m48t59_set_addr (m48t59_t *NVRAM, uint32_t addr)
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void m48t59_set_addr (void *opaque, uint32_t addr)
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{
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    m48t59_t *NVRAM = opaque;
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    NVRAM->addr = addr;
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}
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void m48t59_toggle_lock (m48t59_t *NVRAM, int lock)
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void m48t59_toggle_lock (void *opaque, int lock)
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{
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    m48t59_t *NVRAM = opaque;
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    NVRAM->lock ^= 1 << lock;
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}
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b/hw/m48t59.h
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typedef struct m48t59_t m48t59_t;
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void m48t59_write (m48t59_t *NVRAM, uint32_t addr, uint32_t val);
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uint32_t m48t59_read (m48t59_t *NVRAM, uint32_t addr);
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void m48t59_toggle_lock (m48t59_t *NVRAM, int lock);
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void m48t59_write (void *private, uint32_t addr, uint32_t val);
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uint32_t m48t59_read (void *private, uint32_t addr);
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void m48t59_toggle_lock (void *private, int lock);
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m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
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                       uint32_t io_base, uint16_t size,
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                       int type);

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