Revision 89e8b13c
b/hw/e1000.c | ||
---|---|---|
148 | 148 |
ioport_map(PCIDevice *pci_dev, int region_num, pcibus_t addr, |
149 | 149 |
pcibus_t size, int type) |
150 | 150 |
{ |
151 |
DBGOUT(IO, "e1000_ioport_map addr=0x%04x size=0x%08x\n", addr, size); |
|
151 |
DBGOUT(IO, "e1000_ioport_map addr=0x%04"FMT_PCIBUS |
|
152 |
" size=0x%08"FMT_PCIBUS"\n", addr, size); |
|
152 | 153 |
} |
153 | 154 |
|
154 | 155 |
static void |
... | ... | |
1021 | 1022 |
}; |
1022 | 1023 |
|
1023 | 1024 |
|
1024 |
DBGOUT(MMIO, "e1000_mmio_map addr=0x%08x 0x%08x\n", addr, size); |
|
1025 |
DBGOUT(MMIO, "e1000_mmio_map addr=0x%08"FMT_PCIBUS" 0x%08"FMT_PCIBUS"\n", |
|
1026 |
addr, size); |
|
1025 | 1027 |
|
1026 | 1028 |
cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index); |
1027 | 1029 |
qemu_register_coalesced_mmio(addr, excluded_regs[0]); |
b/hw/eepro100.c | ||
---|---|---|
1388 | 1388 |
{ |
1389 | 1389 |
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
1390 | 1390 |
|
1391 |
TRACE(OTHER, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n", |
|
1391 |
TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", " |
|
1392 |
"size=0x%08"FMT_PCIBUS", type=%d\n", |
|
1392 | 1393 |
region_num, addr, size, type)); |
1393 | 1394 |
|
1394 | 1395 |
assert(region_num == 1); |
... | ... | |
1467 | 1468 |
{ |
1468 | 1469 |
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
1469 | 1470 |
|
1470 |
TRACE(OTHER, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n", |
|
1471 |
TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", " |
|
1472 |
"size=0x%08"FMT_PCIBUS", type=%d\n", |
|
1471 | 1473 |
region_num, addr, size, type)); |
1472 | 1474 |
|
1473 | 1475 |
if (region_num == 0) { |
b/hw/pci.c | ||
---|---|---|
467 | 467 |
|
468 | 468 |
if (size & (size-1)) { |
469 | 469 |
fprintf(stderr, "ERROR: PCI region size must be pow2 " |
470 |
"type=0x%x, size=0x%x\n", type, size);
|
|
470 |
"type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
|
|
471 | 471 |
exit(1); |
472 | 472 |
} |
473 | 473 |
|
... | ... | |
484 | 484 |
wmask |= PCI_ROM_ADDRESS_ENABLE; |
485 | 485 |
} |
486 | 486 |
pci_set_long(pci_dev->config + addr, type); |
487 |
pci_set_long(pci_dev->wmask + addr, wmask); |
|
487 |
pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
|
|
488 | 488 |
pci_set_long(pci_dev->cmask + addr, 0xffffffff); |
489 | 489 |
} |
490 | 490 |
|
... | ... | |
762 | 762 |
if (r->size != 0) { |
763 | 763 |
monitor_printf(mon, " BAR%d: ", i); |
764 | 764 |
if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { |
765 |
monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n", |
|
765 |
monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS |
|
766 |
" [0x%04"FMT_PCIBUS"].\n", |
|
766 | 767 |
r->addr, r->addr + r->size - 1); |
767 | 768 |
} else { |
768 |
monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n", |
|
769 |
monitor_printf(mon, "32 bit memory at 0x%08"FMT_PCIBUS |
|
770 |
" [0x%08"FMT_PCIBUS"].\n", |
|
769 | 771 |
r->addr, r->addr + r->size - 1); |
770 | 772 |
} |
771 | 773 |
} |
... | ... | |
1124 | 1126 |
r = &d->io_regions[i]; |
1125 | 1127 |
if (!r->size) |
1126 | 1128 |
continue; |
1127 |
monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "", |
|
1129 |
monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS |
|
1130 |
" [0x%"FMT_PCIBUS"]\n", |
|
1131 |
indent, "", |
|
1128 | 1132 |
i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", |
1129 | 1133 |
r->addr, r->addr + r->size - 1); |
1130 | 1134 |
} |
b/hw/pci.h | ||
---|---|---|
72 | 72 |
#define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 |
73 | 73 |
|
74 | 74 |
typedef uint32_t pcibus_t; |
75 |
#define FMT_PCIBUS PRIx32 |
|
75 | 76 |
|
76 | 77 |
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
77 | 78 |
uint32_t address, uint32_t data, int len); |
b/hw/pcnet.c | ||
---|---|---|
1732 | 1732 |
PCNetState *d = &DO_UPCAST(PCIPCNetState, pci_dev, pci_dev)->state; |
1733 | 1733 |
|
1734 | 1734 |
#ifdef PCNET_DEBUG_IO |
1735 |
printf("pcnet_ioport_map addr=0x%04x size=0x%04x\n", addr, size); |
|
1735 |
printf("pcnet_ioport_map addr=0x%04"FMT_PCIBUS" size=0x%04"FMT_PCIBUS"\n", |
|
1736 |
addr, size); |
|
1736 | 1737 |
#endif |
1737 | 1738 |
|
1738 | 1739 |
register_ioport_write(addr, 16, 1, pcnet_aprom_writeb, d); |
... | ... | |
1925 | 1926 |
PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, pci_dev); |
1926 | 1927 |
|
1927 | 1928 |
#ifdef PCNET_DEBUG_IO |
1928 |
printf("pcnet_mmio_map addr=0x%08x 0x%08x\n", addr, size); |
|
1929 |
printf("pcnet_mmio_map addr=0x%08"FMT_PCIBUS" 0x%08"FMT_PCIBUS"\n", |
|
1930 |
addr, size); |
|
1929 | 1931 |
#endif |
1930 | 1932 |
|
1931 | 1933 |
cpu_register_physical_memory(addr, PCNET_PNPMMIO_SIZE, d->state.mmio_index); |
b/hw/wdt_i6300esb.c | ||
---|---|---|
358 | 358 |
I6300State *d = DO_UPCAST(I6300State, dev, dev); |
359 | 359 |
int io_mem; |
360 | 360 |
|
361 |
i6300esb_debug("addr = %x, size = %x, type = %d\n", addr, size, type); |
|
361 |
i6300esb_debug("addr = %"FMT_PCIBUS", size = %"FMT_PCIBUS", type = %d\n", |
|
362 |
addr, size, type); |
|
362 | 363 |
|
363 | 364 |
io_mem = cpu_register_io_memory(mem_read, mem_write, d); |
364 | 365 |
cpu_register_physical_memory (addr, 0x10, io_mem); |
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