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/*
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 * Intel XScale PXA255/270 processor support.
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 *
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 * Copyright (c) 2006 Openedhand Ltd.
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 * Written by Andrzej Zaborowski <balrog@zabor.org>
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 *
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 * This code is licenced under the GNU GPL v2.
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 */
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#ifndef PXA_H
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# define PXA_H                        "pxa.h"
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/* Interrupt numbers */
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# define PXA2XX_PIC_SSP3        0
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# define PXA2XX_PIC_USBH2        2
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# define PXA2XX_PIC_USBH1        3
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# define PXA2XX_PIC_KEYPAD        4
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# define PXA2XX_PIC_PWRI2C        6
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# define PXA25X_PIC_HWUART        7
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# define PXA27X_PIC_OST_4_11        7
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# define PXA2XX_PIC_GPIO_0        8
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# define PXA2XX_PIC_GPIO_1        9
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# define PXA2XX_PIC_GPIO_X        10
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# define PXA2XX_PIC_I2S         13
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# define PXA26X_PIC_ASSP        15
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# define PXA25X_PIC_NSSP        16
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# define PXA27X_PIC_SSP2        16
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# define PXA2XX_PIC_LCD                17
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# define PXA2XX_PIC_I2C                18
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# define PXA2XX_PIC_ICP                19
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# define PXA2XX_PIC_STUART        20
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# define PXA2XX_PIC_BTUART        21
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# define PXA2XX_PIC_FFUART        22
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# define PXA2XX_PIC_MMC                23
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# define PXA2XX_PIC_SSP                24
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# define PXA2XX_PIC_DMA                25
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# define PXA2XX_PIC_OST_0        26
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# define PXA2XX_PIC_RTC1HZ        30
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# define PXA2XX_PIC_RTCALARM        31
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/* DMA requests */
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# define PXA2XX_RX_RQ_I2S        2
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# define PXA2XX_TX_RQ_I2S        3
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# define PXA2XX_RX_RQ_BTUART        4
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# define PXA2XX_TX_RQ_BTUART        5
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# define PXA2XX_RX_RQ_FFUART        6
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# define PXA2XX_TX_RQ_FFUART        7
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# define PXA2XX_RX_RQ_SSP1        13
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# define PXA2XX_TX_RQ_SSP1        14
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# define PXA2XX_RX_RQ_SSP2        15
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# define PXA2XX_TX_RQ_SSP2        16
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# define PXA2XX_RX_RQ_ICP        17
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# define PXA2XX_TX_RQ_ICP        18
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# define PXA2XX_RX_RQ_STUART        19
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# define PXA2XX_TX_RQ_STUART        20
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# define PXA2XX_RX_RQ_MMCI        21
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# define PXA2XX_TX_RQ_MMCI        22
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# define PXA2XX_USB_RQ(x)        ((x) + 24)
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# define PXA2XX_RX_RQ_SSP3        66
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# define PXA2XX_TX_RQ_SSP3        67
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# define PXA2XX_SDRAM_BASE        0xa0000000
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# define PXA2XX_INTERNAL_BASE        0x5c000000
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# define PXA2XX_INTERNAL_SIZE        0x40000
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/* pxa2xx_pic.c */
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DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
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/* pxa2xx_gpio.c */
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DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
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                CPUState *env, DeviceState *pic, int lines);
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void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
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/* pxa2xx_dma.c */
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DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq);
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DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq);
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/* pxa2xx_lcd.c */
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typedef struct PXA2xxLCDState PXA2xxLCDState;
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PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base,
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                qemu_irq irq);
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void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
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void pxa2xx_lcdc_oritentation(void *opaque, int angle);
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/* pxa2xx_mmci.c */
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typedef struct PXA2xxMMCIState PXA2xxMMCIState;
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PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
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                BlockDriverState *bd, qemu_irq irq,
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                qemu_irq rx_dma, qemu_irq tx_dma);
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void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
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                qemu_irq coverswitch);
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/* pxa2xx_pcmcia.c */
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typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
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PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base);
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int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
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int pxa2xx_pcmcia_dettach(void *opaque);
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void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
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/* pxa2xx_keypad.c */
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struct  keymap {
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    int column;
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    int row;
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};
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typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
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PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base,
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                qemu_irq irq);
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void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map,
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                int size);
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/* pxa2xx.c */
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typedef struct PXA2xxI2CState PXA2xxI2CState;
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PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
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                qemu_irq irq, uint32_t page_size);
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i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
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typedef struct PXA2xxI2SState PXA2xxI2SState;
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typedef struct PXA2xxFIrState PXA2xxFIrState;
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typedef struct {
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    CPUState *env;
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    DeviceState *pic;
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    qemu_irq reset;
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    DeviceState *dma;
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    DeviceState *gpio;
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    PXA2xxLCDState *lcd;
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    SSIBus **ssp;
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    PXA2xxI2CState *i2c[2];
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    PXA2xxMMCIState *mmc;
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    PXA2xxPCMCIAState *pcmcia[2];
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    PXA2xxI2SState *i2s;
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    PXA2xxFIrState *fir;
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    PXA2xxKeyPadState *kp;
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    /* Power management */
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    target_phys_addr_t pm_base;
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    uint32_t pm_regs[0x40];
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    /* Clock management */
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    target_phys_addr_t cm_base;
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    uint32_t cm_regs[4];
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    uint32_t clkcfg;
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    /* Memory management */
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    target_phys_addr_t mm_base;
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    uint32_t mm_regs[0x1a];
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    /* Performance monitoring */
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    uint32_t pmnc;
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} PXA2xxState;
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struct PXA2xxI2SState {
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    qemu_irq irq;
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    qemu_irq rx_dma;
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    qemu_irq tx_dma;
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    void (*data_req)(void *, int, int);
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    uint32_t control[2];
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    uint32_t status;
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    uint32_t mask;
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    uint32_t clk;
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    int enable;
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    int rx_len;
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    int tx_len;
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    void (*codec_out)(void *, uint32_t);
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    uint32_t (*codec_in)(void *);
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    void *opaque;
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    int fifo_len;
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    uint32_t fifo[16];
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};
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# define PA_FMT                        "0x%08lx"
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# define REG_FMT                "0x" TARGET_FMT_plx
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PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision);
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PXA2xxState *pxa255_init(unsigned int sdram_size);
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#endif        /* PXA_H */