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/*
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 * QEMU Cirrus CLGD 54xx VGA Emulator.
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 *
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 * Copyright (c) 2004 Fabrice Bellard
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 * Copyright (c) 2004 Makoto Suzuki (suzu)
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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/*
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 * Reference: Finn Thogersons' VGADOC4b
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 *   available at http://home.worldonline.dk/~finth/
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 */
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#include "hw.h"
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#include "pc.h"
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#include "pci.h"
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#include "console.h"
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#include "vga_int.h"
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#include "kvm.h"
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/*
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 * TODO:
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 *    - destination write mask support not complete (bits 5..7)
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 *    - optimize linear mappings
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 *    - optimize bitblt functions
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 */
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//#define DEBUG_CIRRUS
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//#define DEBUG_BITBLT
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/***************************************
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 *
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 *  definitions
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 *
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 ***************************************/
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// ID
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#define CIRRUS_ID_CLGD5422  (0x23<<2)
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#define CIRRUS_ID_CLGD5426  (0x24<<2)
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#define CIRRUS_ID_CLGD5424  (0x25<<2)
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#define CIRRUS_ID_CLGD5428  (0x26<<2)
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#define CIRRUS_ID_CLGD5430  (0x28<<2)
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#define CIRRUS_ID_CLGD5434  (0x2A<<2)
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#define CIRRUS_ID_CLGD5436  (0x2B<<2)
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#define CIRRUS_ID_CLGD5446  (0x2E<<2)
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// sequencer 0x07
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#define CIRRUS_SR7_BPP_VGA            0x00
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#define CIRRUS_SR7_BPP_SVGA           0x01
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#define CIRRUS_SR7_BPP_MASK           0x0e
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#define CIRRUS_SR7_BPP_8              0x00
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#define CIRRUS_SR7_BPP_16_DOUBLEVCLK  0x02
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#define CIRRUS_SR7_BPP_24             0x04
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#define CIRRUS_SR7_BPP_16             0x06
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#define CIRRUS_SR7_BPP_32             0x08
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#define CIRRUS_SR7_ISAADDR_MASK       0xe0
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// sequencer 0x0f
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#define CIRRUS_MEMSIZE_512k        0x08
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#define CIRRUS_MEMSIZE_1M          0x10
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#define CIRRUS_MEMSIZE_2M          0x18
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#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80        // bank switching is enabled.
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// sequencer 0x12
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#define CIRRUS_CURSOR_SHOW         0x01
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#define CIRRUS_CURSOR_HIDDENPEL    0x02
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#define CIRRUS_CURSOR_LARGE        0x04        // 64x64 if set, 32x32 if clear
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// sequencer 0x17
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#define CIRRUS_BUSTYPE_VLBFAST   0x10
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#define CIRRUS_BUSTYPE_PCI       0x20
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#define CIRRUS_BUSTYPE_VLBSLOW   0x30
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#define CIRRUS_BUSTYPE_ISA       0x38
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#define CIRRUS_MMIO_ENABLE       0x04
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#define CIRRUS_MMIO_USE_PCIADDR  0x40        // 0xb8000 if cleared.
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#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
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// control 0x0b
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#define CIRRUS_BANKING_DUAL             0x01
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#define CIRRUS_BANKING_GRANULARITY_16K  0x20        // set:16k, clear:4k
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// control 0x30
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#define CIRRUS_BLTMODE_BACKWARDS        0x01
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#define CIRRUS_BLTMODE_MEMSYSDEST       0x02
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#define CIRRUS_BLTMODE_MEMSYSSRC        0x04
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#define CIRRUS_BLTMODE_TRANSPARENTCOMP  0x08
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#define CIRRUS_BLTMODE_PATTERNCOPY      0x40
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#define CIRRUS_BLTMODE_COLOREXPAND      0x80
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#define CIRRUS_BLTMODE_PIXELWIDTHMASK   0x30
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#define CIRRUS_BLTMODE_PIXELWIDTH8      0x00
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#define CIRRUS_BLTMODE_PIXELWIDTH16     0x10
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#define CIRRUS_BLTMODE_PIXELWIDTH24     0x20
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#define CIRRUS_BLTMODE_PIXELWIDTH32     0x30
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// control 0x31
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#define CIRRUS_BLT_BUSY                 0x01
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#define CIRRUS_BLT_START                0x02
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#define CIRRUS_BLT_RESET                0x04
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#define CIRRUS_BLT_FIFOUSED             0x10
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#define CIRRUS_BLT_AUTOSTART            0x80
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// control 0x32
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#define CIRRUS_ROP_0                    0x00
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#define CIRRUS_ROP_SRC_AND_DST          0x05
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#define CIRRUS_ROP_NOP                  0x06
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#define CIRRUS_ROP_SRC_AND_NOTDST       0x09
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#define CIRRUS_ROP_NOTDST               0x0b
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#define CIRRUS_ROP_SRC                  0x0d
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#define CIRRUS_ROP_1                    0x0e
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#define CIRRUS_ROP_NOTSRC_AND_DST       0x50
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#define CIRRUS_ROP_SRC_XOR_DST          0x59
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#define CIRRUS_ROP_SRC_OR_DST           0x6d
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#define CIRRUS_ROP_NOTSRC_OR_NOTDST     0x90
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#define CIRRUS_ROP_SRC_NOTXOR_DST       0x95
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#define CIRRUS_ROP_SRC_OR_NOTDST        0xad
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#define CIRRUS_ROP_NOTSRC               0xd0
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#define CIRRUS_ROP_NOTSRC_OR_DST        0xd6
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#define CIRRUS_ROP_NOTSRC_AND_NOTDST    0xda
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#define CIRRUS_ROP_NOP_INDEX 2
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#define CIRRUS_ROP_SRC_INDEX 5
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// control 0x33
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#define CIRRUS_BLTMODEEXT_SOLIDFILL        0x04
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#define CIRRUS_BLTMODEEXT_COLOREXPINV      0x02
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#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
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// memory-mapped IO
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#define CIRRUS_MMIO_BLTBGCOLOR        0x00        // dword
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#define CIRRUS_MMIO_BLTFGCOLOR        0x04        // dword
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#define CIRRUS_MMIO_BLTWIDTH          0x08        // word
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#define CIRRUS_MMIO_BLTHEIGHT         0x0a        // word
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#define CIRRUS_MMIO_BLTDESTPITCH      0x0c        // word
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#define CIRRUS_MMIO_BLTSRCPITCH       0x0e        // word
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#define CIRRUS_MMIO_BLTDESTADDR       0x10        // dword
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#define CIRRUS_MMIO_BLTSRCADDR        0x14        // dword
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#define CIRRUS_MMIO_BLTWRITEMASK      0x17        // byte
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#define CIRRUS_MMIO_BLTMODE           0x18        // byte
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#define CIRRUS_MMIO_BLTROP            0x1a        // byte
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#define CIRRUS_MMIO_BLTMODEEXT        0x1b        // byte
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#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c        // word?
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#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20        // word?
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#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24        // word
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#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26        // word
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#define CIRRUS_MMIO_LINEARDRAW_END_X  0x28        // word
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#define CIRRUS_MMIO_LINEARDRAW_END_Y  0x2a        // word
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c        // byte
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d        // byte
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e        // byte
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f        // byte
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#define CIRRUS_MMIO_BRESENHAM_K1      0x30        // word
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#define CIRRUS_MMIO_BRESENHAM_K3      0x32        // word
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#define CIRRUS_MMIO_BRESENHAM_ERROR   0x34        // word
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#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36        // word
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#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38        // byte
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#define CIRRUS_MMIO_LINEDRAW_MODE     0x39        // byte
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#define CIRRUS_MMIO_BLTSTATUS         0x40        // byte
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// PCI 0x04: command(word), 0x06(word): status
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#define PCI_COMMAND_IOACCESS                0x0001
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#define PCI_COMMAND_MEMACCESS               0x0002
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#define PCI_COMMAND_BUSMASTER               0x0004
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#define PCI_COMMAND_SPECIALCYCLE            0x0008
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#define PCI_COMMAND_MEMWRITEINVALID         0x0010
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#define PCI_COMMAND_PALETTESNOOPING         0x0020
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#define PCI_COMMAND_PARITYDETECTION         0x0040
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#define PCI_COMMAND_ADDRESSDATASTEPPING     0x0080
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#define PCI_COMMAND_SERR                    0x0100
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#define PCI_COMMAND_BACKTOBACKTRANS         0x0200
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// PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
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#define PCI_CLASS_BASE_DISPLAY        0x03
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// PCI 0x08, 0x00ff0000
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#define PCI_CLASS_SUB_VGA             0x00
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// PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
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// 0x10-0x3f (headertype 00h)
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// PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
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//   0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
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#define PCI_MAP_MEM                 0x0
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#define PCI_MAP_IO                  0x1
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#define PCI_MAP_MEM_ADDR_MASK       (~0xf)
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#define PCI_MAP_IO_ADDR_MASK        (~0x3)
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#define PCI_MAP_MEMFLAGS_32BIT      0x0
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#define PCI_MAP_MEMFLAGS_32BIT_1M   0x1
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#define PCI_MAP_MEMFLAGS_64BIT      0x4
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#define PCI_MAP_MEMFLAGS_CACHEABLE  0x8
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// PCI 0x28: cardbus CIS pointer
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// PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
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// PCI 0x30: expansion ROM base address
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#define PCI_ROMBIOS_ENABLED         0x1
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// PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
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// PCI 0x38: reserved
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// PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
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209
#define CIRRUS_PNPMMIO_SIZE         0x1000
210

    
211

    
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/* I/O and memory hook */
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#define CIRRUS_HOOK_NOT_HANDLED 0
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#define CIRRUS_HOOK_HANDLED 1
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#define ABS(a) ((signed)(a) > 0 ? a : -a)
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#define BLTUNSAFE(s) \
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    ( \
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        ( /* check dst is within bounds */ \
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            (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
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                + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
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                    (s)->vga.vram_size \
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        ) || \
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        ( /* check src is within bounds */ \
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            (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
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                + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
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                    (s)->vga.vram_size \
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        ) \
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    )
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struct CirrusVGAState;
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typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
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                                     uint8_t * dst, const uint8_t * src,
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                                     int dstpitch, int srcpitch,
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                                     int bltwidth, int bltheight);
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typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
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                              uint8_t *dst, int dst_pitch, int width, int height);
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240
typedef struct CirrusVGAState {
241
    VGACommonState vga;
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    int cirrus_linear_io_addr;
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    int cirrus_linear_bitblt_io_addr;
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    int cirrus_mmio_io_addr;
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    uint32_t cirrus_addr_mask;
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    uint32_t linear_mmio_mask;
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    uint8_t cirrus_shadow_gr0;
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    uint8_t cirrus_shadow_gr1;
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    uint8_t cirrus_hidden_dac_lockindex;
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    uint8_t cirrus_hidden_dac_data;
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    uint32_t cirrus_bank_base[2];
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    uint32_t cirrus_bank_limit[2];
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    uint8_t cirrus_hidden_palette[48];
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    uint32_t hw_cursor_x;
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    uint32_t hw_cursor_y;
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    int cirrus_blt_pixelwidth;
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    int cirrus_blt_width;
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    int cirrus_blt_height;
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    int cirrus_blt_dstpitch;
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    int cirrus_blt_srcpitch;
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    uint32_t cirrus_blt_fgcol;
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    uint32_t cirrus_blt_bgcol;
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    uint32_t cirrus_blt_dstaddr;
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    uint32_t cirrus_blt_srcaddr;
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    uint8_t cirrus_blt_mode;
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    uint8_t cirrus_blt_modeext;
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    cirrus_bitblt_rop_t cirrus_rop;
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#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
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    uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
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    uint8_t *cirrus_srcptr;
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    uint8_t *cirrus_srcptr_end;
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    uint32_t cirrus_srccounter;
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    /* hwcursor display state */
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    int last_hw_cursor_size;
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    int last_hw_cursor_x;
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    int last_hw_cursor_y;
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    int last_hw_cursor_y_start;
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    int last_hw_cursor_y_end;
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    int real_vram_size; /* XXX: suppress that */
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    int device_id;
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    int bustype;
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} CirrusVGAState;
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285
typedef struct PCICirrusVGAState {
286
    PCIDevice dev;
287
    CirrusVGAState cirrus_vga;
288
} PCICirrusVGAState;
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static uint8_t rop_to_index[256];
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/***************************************
293
 *
294
 *  prototypes.
295
 *
296
 ***************************************/
297

    
298

    
299
static void cirrus_bitblt_reset(CirrusVGAState *s);
300
static void cirrus_update_memory_access(CirrusVGAState *s);
301

    
302
/***************************************
303
 *
304
 *  raster operations
305
 *
306
 ***************************************/
307

    
308
static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
309
                                  uint8_t *dst,const uint8_t *src,
310
                                  int dstpitch,int srcpitch,
311
                                  int bltwidth,int bltheight)
312
{
313
}
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315
static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
316
                                   uint8_t *dst,
317
                                   int dstpitch, int bltwidth,int bltheight)
318
{
319
}
320

    
321
#define ROP_NAME 0
322
#define ROP_OP(d, s) d = 0
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#include "cirrus_vga_rop.h"
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#define ROP_NAME src_and_dst
326
#define ROP_OP(d, s) d = (s) & (d)
327
#include "cirrus_vga_rop.h"
328

    
329
#define ROP_NAME src_and_notdst
330
#define ROP_OP(d, s) d = (s) & (~(d))
331
#include "cirrus_vga_rop.h"
332

    
333
#define ROP_NAME notdst
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#define ROP_OP(d, s) d = ~(d)
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#include "cirrus_vga_rop.h"
336

    
337
#define ROP_NAME src
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#define ROP_OP(d, s) d = s
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#include "cirrus_vga_rop.h"
340

    
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#define ROP_NAME 1
342
#define ROP_OP(d, s) d = ~0
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#include "cirrus_vga_rop.h"
344

    
345
#define ROP_NAME notsrc_and_dst
346
#define ROP_OP(d, s) d = (~(s)) & (d)
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#include "cirrus_vga_rop.h"
348

    
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#define ROP_NAME src_xor_dst
350
#define ROP_OP(d, s) d = (s) ^ (d)
351
#include "cirrus_vga_rop.h"
352

    
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#define ROP_NAME src_or_dst
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#define ROP_OP(d, s) d = (s) | (d)
355
#include "cirrus_vga_rop.h"
356

    
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#define ROP_NAME notsrc_or_notdst
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#define ROP_OP(d, s) d = (~(s)) | (~(d))
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#include "cirrus_vga_rop.h"
360

    
361
#define ROP_NAME src_notxor_dst
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#define ROP_OP(d, s) d = ~((s) ^ (d))
363
#include "cirrus_vga_rop.h"
364

    
365
#define ROP_NAME src_or_notdst
366
#define ROP_OP(d, s) d = (s) | (~(d))
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#include "cirrus_vga_rop.h"
368

    
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#define ROP_NAME notsrc
370
#define ROP_OP(d, s) d = (~(s))
371
#include "cirrus_vga_rop.h"
372

    
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#define ROP_NAME notsrc_or_dst
374
#define ROP_OP(d, s) d = (~(s)) | (d)
375
#include "cirrus_vga_rop.h"
376

    
377
#define ROP_NAME notsrc_and_notdst
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#define ROP_OP(d, s) d = (~(s)) & (~(d))
379
#include "cirrus_vga_rop.h"
380

    
381
static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
382
    cirrus_bitblt_rop_fwd_0,
383
    cirrus_bitblt_rop_fwd_src_and_dst,
384
    cirrus_bitblt_rop_nop,
385
    cirrus_bitblt_rop_fwd_src_and_notdst,
386
    cirrus_bitblt_rop_fwd_notdst,
387
    cirrus_bitblt_rop_fwd_src,
388
    cirrus_bitblt_rop_fwd_1,
389
    cirrus_bitblt_rop_fwd_notsrc_and_dst,
390
    cirrus_bitblt_rop_fwd_src_xor_dst,
391
    cirrus_bitblt_rop_fwd_src_or_dst,
392
    cirrus_bitblt_rop_fwd_notsrc_or_notdst,
393
    cirrus_bitblt_rop_fwd_src_notxor_dst,
394
    cirrus_bitblt_rop_fwd_src_or_notdst,
395
    cirrus_bitblt_rop_fwd_notsrc,
396
    cirrus_bitblt_rop_fwd_notsrc_or_dst,
397
    cirrus_bitblt_rop_fwd_notsrc_and_notdst,
398
};
399

    
400
static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
401
    cirrus_bitblt_rop_bkwd_0,
402
    cirrus_bitblt_rop_bkwd_src_and_dst,
403
    cirrus_bitblt_rop_nop,
404
    cirrus_bitblt_rop_bkwd_src_and_notdst,
405
    cirrus_bitblt_rop_bkwd_notdst,
406
    cirrus_bitblt_rop_bkwd_src,
407
    cirrus_bitblt_rop_bkwd_1,
408
    cirrus_bitblt_rop_bkwd_notsrc_and_dst,
409
    cirrus_bitblt_rop_bkwd_src_xor_dst,
410
    cirrus_bitblt_rop_bkwd_src_or_dst,
411
    cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
412
    cirrus_bitblt_rop_bkwd_src_notxor_dst,
413
    cirrus_bitblt_rop_bkwd_src_or_notdst,
414
    cirrus_bitblt_rop_bkwd_notsrc,
415
    cirrus_bitblt_rop_bkwd_notsrc_or_dst,
416
    cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
417
};
418

    
419
#define TRANSP_ROP(name) {\
420
    name ## _8,\
421
    name ## _16,\
422
        }
423
#define TRANSP_NOP(func) {\
424
    func,\
425
    func,\
426
        }
427

    
428
static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
429
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
430
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
431
    TRANSP_NOP(cirrus_bitblt_rop_nop),
432
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
433
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
434
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
435
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
436
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
437
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
438
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
439
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
440
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
441
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
442
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
443
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
444
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
445
};
446

    
447
static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
448
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
449
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
450
    TRANSP_NOP(cirrus_bitblt_rop_nop),
451
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
452
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
453
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
454
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
455
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
456
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
457
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
458
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
459
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
460
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
461
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
462
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
463
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
464
};
465

    
466
#define ROP2(name) {\
467
    name ## _8,\
468
    name ## _16,\
469
    name ## _24,\
470
    name ## _32,\
471
        }
472

    
473
#define ROP_NOP2(func) {\
474
    func,\
475
    func,\
476
    func,\
477
    func,\
478
        }
479

    
480
static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
481
    ROP2(cirrus_patternfill_0),
482
    ROP2(cirrus_patternfill_src_and_dst),
483
    ROP_NOP2(cirrus_bitblt_rop_nop),
484
    ROP2(cirrus_patternfill_src_and_notdst),
485
    ROP2(cirrus_patternfill_notdst),
486
    ROP2(cirrus_patternfill_src),
487
    ROP2(cirrus_patternfill_1),
488
    ROP2(cirrus_patternfill_notsrc_and_dst),
489
    ROP2(cirrus_patternfill_src_xor_dst),
490
    ROP2(cirrus_patternfill_src_or_dst),
491
    ROP2(cirrus_patternfill_notsrc_or_notdst),
492
    ROP2(cirrus_patternfill_src_notxor_dst),
493
    ROP2(cirrus_patternfill_src_or_notdst),
494
    ROP2(cirrus_patternfill_notsrc),
495
    ROP2(cirrus_patternfill_notsrc_or_dst),
496
    ROP2(cirrus_patternfill_notsrc_and_notdst),
497
};
498

    
499
static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
500
    ROP2(cirrus_colorexpand_transp_0),
501
    ROP2(cirrus_colorexpand_transp_src_and_dst),
502
    ROP_NOP2(cirrus_bitblt_rop_nop),
503
    ROP2(cirrus_colorexpand_transp_src_and_notdst),
504
    ROP2(cirrus_colorexpand_transp_notdst),
505
    ROP2(cirrus_colorexpand_transp_src),
506
    ROP2(cirrus_colorexpand_transp_1),
507
    ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
508
    ROP2(cirrus_colorexpand_transp_src_xor_dst),
509
    ROP2(cirrus_colorexpand_transp_src_or_dst),
510
    ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
511
    ROP2(cirrus_colorexpand_transp_src_notxor_dst),
512
    ROP2(cirrus_colorexpand_transp_src_or_notdst),
513
    ROP2(cirrus_colorexpand_transp_notsrc),
514
    ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
515
    ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
516
};
517

    
518
static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
519
    ROP2(cirrus_colorexpand_0),
520
    ROP2(cirrus_colorexpand_src_and_dst),
521
    ROP_NOP2(cirrus_bitblt_rop_nop),
522
    ROP2(cirrus_colorexpand_src_and_notdst),
523
    ROP2(cirrus_colorexpand_notdst),
524
    ROP2(cirrus_colorexpand_src),
525
    ROP2(cirrus_colorexpand_1),
526
    ROP2(cirrus_colorexpand_notsrc_and_dst),
527
    ROP2(cirrus_colorexpand_src_xor_dst),
528
    ROP2(cirrus_colorexpand_src_or_dst),
529
    ROP2(cirrus_colorexpand_notsrc_or_notdst),
530
    ROP2(cirrus_colorexpand_src_notxor_dst),
531
    ROP2(cirrus_colorexpand_src_or_notdst),
532
    ROP2(cirrus_colorexpand_notsrc),
533
    ROP2(cirrus_colorexpand_notsrc_or_dst),
534
    ROP2(cirrus_colorexpand_notsrc_and_notdst),
535
};
536

    
537
static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
538
    ROP2(cirrus_colorexpand_pattern_transp_0),
539
    ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
540
    ROP_NOP2(cirrus_bitblt_rop_nop),
541
    ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
542
    ROP2(cirrus_colorexpand_pattern_transp_notdst),
543
    ROP2(cirrus_colorexpand_pattern_transp_src),
544
    ROP2(cirrus_colorexpand_pattern_transp_1),
545
    ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
546
    ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
547
    ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
548
    ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
549
    ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
550
    ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
551
    ROP2(cirrus_colorexpand_pattern_transp_notsrc),
552
    ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
553
    ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
554
};
555

    
556
static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
557
    ROP2(cirrus_colorexpand_pattern_0),
558
    ROP2(cirrus_colorexpand_pattern_src_and_dst),
559
    ROP_NOP2(cirrus_bitblt_rop_nop),
560
    ROP2(cirrus_colorexpand_pattern_src_and_notdst),
561
    ROP2(cirrus_colorexpand_pattern_notdst),
562
    ROP2(cirrus_colorexpand_pattern_src),
563
    ROP2(cirrus_colorexpand_pattern_1),
564
    ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
565
    ROP2(cirrus_colorexpand_pattern_src_xor_dst),
566
    ROP2(cirrus_colorexpand_pattern_src_or_dst),
567
    ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
568
    ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
569
    ROP2(cirrus_colorexpand_pattern_src_or_notdst),
570
    ROP2(cirrus_colorexpand_pattern_notsrc),
571
    ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
572
    ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
573
};
574

    
575
static const cirrus_fill_t cirrus_fill[16][4] = {
576
    ROP2(cirrus_fill_0),
577
    ROP2(cirrus_fill_src_and_dst),
578
    ROP_NOP2(cirrus_bitblt_fill_nop),
579
    ROP2(cirrus_fill_src_and_notdst),
580
    ROP2(cirrus_fill_notdst),
581
    ROP2(cirrus_fill_src),
582
    ROP2(cirrus_fill_1),
583
    ROP2(cirrus_fill_notsrc_and_dst),
584
    ROP2(cirrus_fill_src_xor_dst),
585
    ROP2(cirrus_fill_src_or_dst),
586
    ROP2(cirrus_fill_notsrc_or_notdst),
587
    ROP2(cirrus_fill_src_notxor_dst),
588
    ROP2(cirrus_fill_src_or_notdst),
589
    ROP2(cirrus_fill_notsrc),
590
    ROP2(cirrus_fill_notsrc_or_dst),
591
    ROP2(cirrus_fill_notsrc_and_notdst),
592
};
593

    
594
static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
595
{
596
    unsigned int color;
597
    switch (s->cirrus_blt_pixelwidth) {
598
    case 1:
599
        s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
600
        break;
601
    case 2:
602
        color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
603
        s->cirrus_blt_fgcol = le16_to_cpu(color);
604
        break;
605
    case 3:
606
        s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
607
            (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
608
        break;
609
    default:
610
    case 4:
611
        color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
612
            (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
613
        s->cirrus_blt_fgcol = le32_to_cpu(color);
614
        break;
615
    }
616
}
617

    
618
static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
619
{
620
    unsigned int color;
621
    switch (s->cirrus_blt_pixelwidth) {
622
    case 1:
623
        s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
624
        break;
625
    case 2:
626
        color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
627
        s->cirrus_blt_bgcol = le16_to_cpu(color);
628
        break;
629
    case 3:
630
        s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
631
            (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
632
        break;
633
    default:
634
    case 4:
635
        color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
636
            (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
637
        s->cirrus_blt_bgcol = le32_to_cpu(color);
638
        break;
639
    }
640
}
641

    
642
static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
643
                                     int off_pitch, int bytesperline,
644
                                     int lines)
645
{
646
    int y;
647
    int off_cur;
648
    int off_cur_end;
649

    
650
    for (y = 0; y < lines; y++) {
651
        off_cur = off_begin;
652
        off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
653
        off_cur &= TARGET_PAGE_MASK;
654
        while (off_cur < off_cur_end) {
655
            cpu_physical_memory_set_dirty(s->vga.vram_offset + off_cur);
656
            off_cur += TARGET_PAGE_SIZE;
657
        }
658
        off_begin += off_pitch;
659
    }
660
}
661

    
662
static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
663
                                            const uint8_t * src)
664
{
665
    uint8_t *dst;
666

    
667
    dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
668

    
669
    if (BLTUNSAFE(s))
670
        return 0;
671

    
672
    (*s->cirrus_rop) (s, dst, src,
673
                      s->cirrus_blt_dstpitch, 0,
674
                      s->cirrus_blt_width, s->cirrus_blt_height);
675
    cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
676
                             s->cirrus_blt_dstpitch, s->cirrus_blt_width,
677
                             s->cirrus_blt_height);
678
    return 1;
679
}
680

    
681
/* fill */
682

    
683
static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
684
{
685
    cirrus_fill_t rop_func;
686

    
687
    if (BLTUNSAFE(s))
688
        return 0;
689
    rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
690
    rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
691
             s->cirrus_blt_dstpitch,
692
             s->cirrus_blt_width, s->cirrus_blt_height);
693
    cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
694
                             s->cirrus_blt_dstpitch, s->cirrus_blt_width,
695
                             s->cirrus_blt_height);
696
    cirrus_bitblt_reset(s);
697
    return 1;
698
}
699

    
700
/***************************************
701
 *
702
 *  bitblt (video-to-video)
703
 *
704
 ***************************************/
705

    
706
static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
707
{
708
    return cirrus_bitblt_common_patterncopy(s,
709
                                            s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
710
                                            s->cirrus_addr_mask));
711
}
712

    
713
static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
714
{
715
    int sx, sy;
716
    int dx, dy;
717
    int width, height;
718
    int depth;
719
    int notify = 0;
720

    
721
    depth = s->vga.get_bpp(&s->vga) / 8;
722
    s->vga.get_resolution(&s->vga, &width, &height);
723

    
724
    /* extra x, y */
725
    sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
726
    sy = (src / ABS(s->cirrus_blt_srcpitch));
727
    dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
728
    dy = (dst / ABS(s->cirrus_blt_dstpitch));
729

    
730
    /* normalize width */
731
    w /= depth;
732

    
733
    /* if we're doing a backward copy, we have to adjust
734
       our x/y to be the upper left corner (instead of the lower
735
       right corner) */
736
    if (s->cirrus_blt_dstpitch < 0) {
737
        sx -= (s->cirrus_blt_width / depth) - 1;
738
        dx -= (s->cirrus_blt_width / depth) - 1;
739
        sy -= s->cirrus_blt_height - 1;
740
        dy -= s->cirrus_blt_height - 1;
741
    }
742

    
743
    /* are we in the visible portion of memory? */
744
    if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
745
        (sx + w) <= width && (sy + h) <= height &&
746
        (dx + w) <= width && (dy + h) <= height) {
747
        notify = 1;
748
    }
749

    
750
    /* make to sure only copy if it's a plain copy ROP */
751
    if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
752
        *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
753
        notify = 0;
754

    
755
    /* we have to flush all pending changes so that the copy
756
       is generated at the appropriate moment in time */
757
    if (notify)
758
        vga_hw_update();
759

    
760
    (*s->cirrus_rop) (s, s->vga.vram_ptr +
761
                      (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
762
                      s->vga.vram_ptr +
763
                      (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
764
                      s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
765
                      s->cirrus_blt_width, s->cirrus_blt_height);
766

    
767
    if (notify)
768
        qemu_console_copy(s->vga.ds,
769
                          sx, sy, dx, dy,
770
                          s->cirrus_blt_width / depth,
771
                          s->cirrus_blt_height);
772

    
773
    /* we don't have to notify the display that this portion has
774
       changed since qemu_console_copy implies this */
775

    
776
    cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
777
                                s->cirrus_blt_dstpitch, s->cirrus_blt_width,
778
                                s->cirrus_blt_height);
779
}
780

    
781
static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
782
{
783
    if (BLTUNSAFE(s))
784
        return 0;
785

    
786
    cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
787
            s->cirrus_blt_srcaddr - s->vga.start_addr,
788
            s->cirrus_blt_width, s->cirrus_blt_height);
789

    
790
    return 1;
791
}
792

    
793
/***************************************
794
 *
795
 *  bitblt (cpu-to-video)
796
 *
797
 ***************************************/
798

    
799
static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
800
{
801
    int copy_count;
802
    uint8_t *end_ptr;
803

    
804
    if (s->cirrus_srccounter > 0) {
805
        if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
806
            cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
807
        the_end:
808
            s->cirrus_srccounter = 0;
809
            cirrus_bitblt_reset(s);
810
        } else {
811
            /* at least one scan line */
812
            do {
813
                (*s->cirrus_rop)(s, s->vga.vram_ptr +
814
                                 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
815
                                  s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
816
                cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
817
                                         s->cirrus_blt_width, 1);
818
                s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
819
                s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
820
                if (s->cirrus_srccounter <= 0)
821
                    goto the_end;
822
                /* more bytes than needed can be transfered because of
823
                   word alignment, so we keep them for the next line */
824
                /* XXX: keep alignment to speed up transfer */
825
                end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
826
                copy_count = s->cirrus_srcptr_end - end_ptr;
827
                memmove(s->cirrus_bltbuf, end_ptr, copy_count);
828
                s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
829
                s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
830
            } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
831
        }
832
    }
833
}
834

    
835
/***************************************
836
 *
837
 *  bitblt wrapper
838
 *
839
 ***************************************/
840

    
841
static void cirrus_bitblt_reset(CirrusVGAState * s)
842
{
843
    int need_update;
844

    
845
    s->vga.gr[0x31] &=
846
        ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
847
    need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
848
        || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
849
    s->cirrus_srcptr = &s->cirrus_bltbuf[0];
850
    s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
851
    s->cirrus_srccounter = 0;
852
    if (!need_update)
853
        return;
854
    cirrus_update_memory_access(s);
855
}
856

    
857
static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
858
{
859
    int w;
860

    
861
    s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
862
    s->cirrus_srcptr = &s->cirrus_bltbuf[0];
863
    s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
864

    
865
    if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
866
        if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
867
            s->cirrus_blt_srcpitch = 8;
868
        } else {
869
            /* XXX: check for 24 bpp */
870
            s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
871
        }
872
        s->cirrus_srccounter = s->cirrus_blt_srcpitch;
873
    } else {
874
        if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
875
            w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
876
            if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
877
                s->cirrus_blt_srcpitch = ((w + 31) >> 5);
878
            else
879
                s->cirrus_blt_srcpitch = ((w + 7) >> 3);
880
        } else {
881
            /* always align input size to 32 bits */
882
            s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
883
        }
884
        s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
885
    }
886
    s->cirrus_srcptr = s->cirrus_bltbuf;
887
    s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
888
    cirrus_update_memory_access(s);
889
    return 1;
890
}
891

    
892
static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
893
{
894
    /* XXX */
895
#ifdef DEBUG_BITBLT
896
    printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
897
#endif
898
    return 0;
899
}
900

    
901
static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
902
{
903
    int ret;
904

    
905
    if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
906
        ret = cirrus_bitblt_videotovideo_patterncopy(s);
907
    } else {
908
        ret = cirrus_bitblt_videotovideo_copy(s);
909
    }
910
    if (ret)
911
        cirrus_bitblt_reset(s);
912
    return ret;
913
}
914

    
915
static void cirrus_bitblt_start(CirrusVGAState * s)
916
{
917
    uint8_t blt_rop;
918

    
919
    s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
920

    
921
    s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
922
    s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
923
    s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
924
    s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
925
    s->cirrus_blt_dstaddr =
926
        (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
927
    s->cirrus_blt_srcaddr =
928
        (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
929
    s->cirrus_blt_mode = s->vga.gr[0x30];
930
    s->cirrus_blt_modeext = s->vga.gr[0x33];
931
    blt_rop = s->vga.gr[0x32];
932

    
933
#ifdef DEBUG_BITBLT
934
    printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
935
           blt_rop,
936
           s->cirrus_blt_mode,
937
           s->cirrus_blt_modeext,
938
           s->cirrus_blt_width,
939
           s->cirrus_blt_height,
940
           s->cirrus_blt_dstpitch,
941
           s->cirrus_blt_srcpitch,
942
           s->cirrus_blt_dstaddr,
943
           s->cirrus_blt_srcaddr,
944
           s->vga.gr[0x2f]);
945
#endif
946

    
947
    switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
948
    case CIRRUS_BLTMODE_PIXELWIDTH8:
949
        s->cirrus_blt_pixelwidth = 1;
950
        break;
951
    case CIRRUS_BLTMODE_PIXELWIDTH16:
952
        s->cirrus_blt_pixelwidth = 2;
953
        break;
954
    case CIRRUS_BLTMODE_PIXELWIDTH24:
955
        s->cirrus_blt_pixelwidth = 3;
956
        break;
957
    case CIRRUS_BLTMODE_PIXELWIDTH32:
958
        s->cirrus_blt_pixelwidth = 4;
959
        break;
960
    default:
961
#ifdef DEBUG_BITBLT
962
        printf("cirrus: bitblt - pixel width is unknown\n");
963
#endif
964
        goto bitblt_ignore;
965
    }
966
    s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
967

    
968
    if ((s->
969
         cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
970
                            CIRRUS_BLTMODE_MEMSYSDEST))
971
        == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
972
#ifdef DEBUG_BITBLT
973
        printf("cirrus: bitblt - memory-to-memory copy is requested\n");
974
#endif
975
        goto bitblt_ignore;
976
    }
977

    
978
    if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
979
        (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
980
                               CIRRUS_BLTMODE_TRANSPARENTCOMP |
981
                               CIRRUS_BLTMODE_PATTERNCOPY |
982
                               CIRRUS_BLTMODE_COLOREXPAND)) ==
983
         (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
984
        cirrus_bitblt_fgcol(s);
985
        cirrus_bitblt_solidfill(s, blt_rop);
986
    } else {
987
        if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
988
                                   CIRRUS_BLTMODE_PATTERNCOPY)) ==
989
            CIRRUS_BLTMODE_COLOREXPAND) {
990

    
991
            if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
992
                if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
993
                    cirrus_bitblt_bgcol(s);
994
                else
995
                    cirrus_bitblt_fgcol(s);
996
                s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
997
            } else {
998
                cirrus_bitblt_fgcol(s);
999
                cirrus_bitblt_bgcol(s);
1000
                s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1001
            }
1002
        } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
1003
            if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1004
                if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1005
                    if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1006
                        cirrus_bitblt_bgcol(s);
1007
                    else
1008
                        cirrus_bitblt_fgcol(s);
1009
                    s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1010
                } else {
1011
                    cirrus_bitblt_fgcol(s);
1012
                    cirrus_bitblt_bgcol(s);
1013
                    s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1014
                }
1015
            } else {
1016
                s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1017
            }
1018
        } else {
1019
            if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1020
                if (s->cirrus_blt_pixelwidth > 2) {
1021
                    printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1022
                    goto bitblt_ignore;
1023
                }
1024
                if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1025
                    s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1026
                    s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1027
                    s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1028
                } else {
1029
                    s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1030
                }
1031
            } else {
1032
                if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1033
                    s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1034
                    s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1035
                    s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1036
                } else {
1037
                    s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1038
                }
1039
            }
1040
        }
1041
        // setup bitblt engine.
1042
        if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1043
            if (!cirrus_bitblt_cputovideo(s))
1044
                goto bitblt_ignore;
1045
        } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1046
            if (!cirrus_bitblt_videotocpu(s))
1047
                goto bitblt_ignore;
1048
        } else {
1049
            if (!cirrus_bitblt_videotovideo(s))
1050
                goto bitblt_ignore;
1051
        }
1052
    }
1053
    return;
1054
  bitblt_ignore:;
1055
    cirrus_bitblt_reset(s);
1056
}
1057

    
1058
static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1059
{
1060
    unsigned old_value;
1061

    
1062
    old_value = s->vga.gr[0x31];
1063
    s->vga.gr[0x31] = reg_value;
1064

    
1065
    if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1066
        ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1067
        cirrus_bitblt_reset(s);
1068
    } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1069
               ((reg_value & CIRRUS_BLT_START) != 0)) {
1070
        cirrus_bitblt_start(s);
1071
    }
1072
}
1073

    
1074

    
1075
/***************************************
1076
 *
1077
 *  basic parameters
1078
 *
1079
 ***************************************/
1080

    
1081
static void cirrus_get_offsets(VGACommonState *s1,
1082
                               uint32_t *pline_offset,
1083
                               uint32_t *pstart_addr,
1084
                               uint32_t *pline_compare)
1085
{
1086
    CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1087
    uint32_t start_addr, line_offset, line_compare;
1088

    
1089
    line_offset = s->vga.cr[0x13]
1090
        | ((s->vga.cr[0x1b] & 0x10) << 4);
1091
    line_offset <<= 3;
1092
    *pline_offset = line_offset;
1093

    
1094
    start_addr = (s->vga.cr[0x0c] << 8)
1095
        | s->vga.cr[0x0d]
1096
        | ((s->vga.cr[0x1b] & 0x01) << 16)
1097
        | ((s->vga.cr[0x1b] & 0x0c) << 15)
1098
        | ((s->vga.cr[0x1d] & 0x80) << 12);
1099
    *pstart_addr = start_addr;
1100

    
1101
    line_compare = s->vga.cr[0x18] |
1102
        ((s->vga.cr[0x07] & 0x10) << 4) |
1103
        ((s->vga.cr[0x09] & 0x40) << 3);
1104
    *pline_compare = line_compare;
1105
}
1106

    
1107
static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1108
{
1109
    uint32_t ret = 16;
1110

    
1111
    switch (s->cirrus_hidden_dac_data & 0xf) {
1112
    case 0:
1113
        ret = 15;
1114
        break;                        /* Sierra HiColor */
1115
    case 1:
1116
        ret = 16;
1117
        break;                        /* XGA HiColor */
1118
    default:
1119
#ifdef DEBUG_CIRRUS
1120
        printf("cirrus: invalid DAC value %x in 16bpp\n",
1121
               (s->cirrus_hidden_dac_data & 0xf));
1122
#endif
1123
        ret = 15;                /* XXX */
1124
        break;
1125
    }
1126
    return ret;
1127
}
1128

    
1129
static int cirrus_get_bpp(VGACommonState *s1)
1130
{
1131
    CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1132
    uint32_t ret = 8;
1133

    
1134
    if ((s->vga.sr[0x07] & 0x01) != 0) {
1135
        /* Cirrus SVGA */
1136
        switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1137
        case CIRRUS_SR7_BPP_8:
1138
            ret = 8;
1139
            break;
1140
        case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1141
            ret = cirrus_get_bpp16_depth(s);
1142
            break;
1143
        case CIRRUS_SR7_BPP_24:
1144
            ret = 24;
1145
            break;
1146
        case CIRRUS_SR7_BPP_16:
1147
            ret = cirrus_get_bpp16_depth(s);
1148
            break;
1149
        case CIRRUS_SR7_BPP_32:
1150
            ret = 32;
1151
            break;
1152
        default:
1153
#ifdef DEBUG_CIRRUS
1154
            printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
1155
#endif
1156
            ret = 8;
1157
            break;
1158
        }
1159
    } else {
1160
        /* VGA */
1161
        ret = 0;
1162
    }
1163

    
1164
    return ret;
1165
}
1166

    
1167
static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1168
{
1169
    int width, height;
1170

    
1171
    width = (s->cr[0x01] + 1) * 8;
1172
    height = s->cr[0x12] |
1173
        ((s->cr[0x07] & 0x02) << 7) |
1174
        ((s->cr[0x07] & 0x40) << 3);
1175
    height = (height + 1);
1176
    /* interlace support */
1177
    if (s->cr[0x1a] & 0x01)
1178
        height = height * 2;
1179
    *pwidth = width;
1180
    *pheight = height;
1181
}
1182

    
1183
/***************************************
1184
 *
1185
 * bank memory
1186
 *
1187
 ***************************************/
1188

    
1189
static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1190
{
1191
    unsigned offset;
1192
    unsigned limit;
1193

    
1194
    if ((s->vga.gr[0x0b] & 0x01) != 0)        /* dual bank */
1195
        offset = s->vga.gr[0x09 + bank_index];
1196
    else                        /* single bank */
1197
        offset = s->vga.gr[0x09];
1198

    
1199
    if ((s->vga.gr[0x0b] & 0x20) != 0)
1200
        offset <<= 14;
1201
    else
1202
        offset <<= 12;
1203

    
1204
    if (s->real_vram_size <= offset)
1205
        limit = 0;
1206
    else
1207
        limit = s->real_vram_size - offset;
1208

    
1209
    if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1210
        if (limit > 0x8000) {
1211
            offset += 0x8000;
1212
            limit -= 0x8000;
1213
        } else {
1214
            limit = 0;
1215
        }
1216
    }
1217

    
1218
    if (limit > 0) {
1219
        /* Thinking about changing bank base? First, drop the dirty bitmap information
1220
         * on the current location, otherwise we lose this pointer forever */
1221
        if (s->vga.lfb_vram_mapped) {
1222
            target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
1223
            cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
1224
        }
1225
        s->cirrus_bank_base[bank_index] = offset;
1226
        s->cirrus_bank_limit[bank_index] = limit;
1227
    } else {
1228
        s->cirrus_bank_base[bank_index] = 0;
1229
        s->cirrus_bank_limit[bank_index] = 0;
1230
    }
1231
}
1232

    
1233
/***************************************
1234
 *
1235
 *  I/O access between 0x3c4-0x3c5
1236
 *
1237
 ***************************************/
1238

    
1239
static int cirrus_vga_read_sr(CirrusVGAState * s)
1240
{
1241
    switch (s->vga.sr_index) {
1242
    case 0x00:                        // Standard VGA
1243
    case 0x01:                        // Standard VGA
1244
    case 0x02:                        // Standard VGA
1245
    case 0x03:                        // Standard VGA
1246
    case 0x04:                        // Standard VGA
1247
        return s->vga.sr[s->vga.sr_index];
1248
    case 0x06:                        // Unlock Cirrus extensions
1249
        return s->vga.sr[s->vga.sr_index];
1250
    case 0x10:
1251
    case 0x30:
1252
    case 0x50:
1253
    case 0x70:                        // Graphics Cursor X
1254
    case 0x90:
1255
    case 0xb0:
1256
    case 0xd0:
1257
    case 0xf0:                        // Graphics Cursor X
1258
        return s->vga.sr[0x10];
1259
    case 0x11:
1260
    case 0x31:
1261
    case 0x51:
1262
    case 0x71:                        // Graphics Cursor Y
1263
    case 0x91:
1264
    case 0xb1:
1265
    case 0xd1:
1266
    case 0xf1:                        // Graphics Cursor Y
1267
        return s->vga.sr[0x11];
1268
    case 0x05:                        // ???
1269
    case 0x07:                        // Extended Sequencer Mode
1270
    case 0x08:                        // EEPROM Control
1271
    case 0x09:                        // Scratch Register 0
1272
    case 0x0a:                        // Scratch Register 1
1273
    case 0x0b:                        // VCLK 0
1274
    case 0x0c:                        // VCLK 1
1275
    case 0x0d:                        // VCLK 2
1276
    case 0x0e:                        // VCLK 3
1277
    case 0x0f:                        // DRAM Control
1278
    case 0x12:                        // Graphics Cursor Attribute
1279
    case 0x13:                        // Graphics Cursor Pattern Address
1280
    case 0x14:                        // Scratch Register 2
1281
    case 0x15:                        // Scratch Register 3
1282
    case 0x16:                        // Performance Tuning Register
1283
    case 0x17:                        // Configuration Readback and Extended Control
1284
    case 0x18:                        // Signature Generator Control
1285
    case 0x19:                        // Signal Generator Result
1286
    case 0x1a:                        // Signal Generator Result
1287
    case 0x1b:                        // VCLK 0 Denominator & Post
1288
    case 0x1c:                        // VCLK 1 Denominator & Post
1289
    case 0x1d:                        // VCLK 2 Denominator & Post
1290
    case 0x1e:                        // VCLK 3 Denominator & Post
1291
    case 0x1f:                        // BIOS Write Enable and MCLK select
1292
#ifdef DEBUG_CIRRUS
1293
        printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
1294
#endif
1295
        return s->vga.sr[s->vga.sr_index];
1296
    default:
1297
#ifdef DEBUG_CIRRUS
1298
        printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
1299
#endif
1300
        return 0xff;
1301
        break;
1302
    }
1303
}
1304

    
1305
static int
1306
cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1307
{
1308
    switch (reg_index) {
1309
    case 0x00:                        // Standard VGA
1310
    case 0x01:                        // Standard VGA
1311
    case 0x02:                        // Standard VGA
1312
    case 0x03:                        // Standard VGA
1313
    case 0x04:                        // Standard VGA
1314
        return CIRRUS_HOOK_NOT_HANDLED;
1315
    case 0x06:                        // Unlock Cirrus extensions
1316
        reg_value &= 0x17;
1317
        if (reg_value == 0x12) {
1318
            s->vga.sr[reg_index] = 0x12;
1319
        } else {
1320
            s->vga.sr[reg_index] = 0x0f;
1321
        }
1322
        break;
1323
    case 0x10:
1324
    case 0x30:
1325
    case 0x50:
1326
    case 0x70:                        // Graphics Cursor X
1327
    case 0x90:
1328
    case 0xb0:
1329
    case 0xd0:
1330
    case 0xf0:                        // Graphics Cursor X
1331
        s->vga.sr[0x10] = reg_value;
1332
        s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
1333
        break;
1334
    case 0x11:
1335
    case 0x31:
1336
    case 0x51:
1337
    case 0x71:                        // Graphics Cursor Y
1338
    case 0x91:
1339
    case 0xb1:
1340
    case 0xd1:
1341
    case 0xf1:                        // Graphics Cursor Y
1342
        s->vga.sr[0x11] = reg_value;
1343
        s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
1344
        break;
1345
    case 0x07:                        // Extended Sequencer Mode
1346
    cirrus_update_memory_access(s);
1347
    case 0x08:                        // EEPROM Control
1348
    case 0x09:                        // Scratch Register 0
1349
    case 0x0a:                        // Scratch Register 1
1350
    case 0x0b:                        // VCLK 0
1351
    case 0x0c:                        // VCLK 1
1352
    case 0x0d:                        // VCLK 2
1353
    case 0x0e:                        // VCLK 3
1354
    case 0x0f:                        // DRAM Control
1355
    case 0x12:                        // Graphics Cursor Attribute
1356
    case 0x13:                        // Graphics Cursor Pattern Address
1357
    case 0x14:                        // Scratch Register 2
1358
    case 0x15:                        // Scratch Register 3
1359
    case 0x16:                        // Performance Tuning Register
1360
    case 0x18:                        // Signature Generator Control
1361
    case 0x19:                        // Signature Generator Result
1362
    case 0x1a:                        // Signature Generator Result
1363
    case 0x1b:                        // VCLK 0 Denominator & Post
1364
    case 0x1c:                        // VCLK 1 Denominator & Post
1365
    case 0x1d:                        // VCLK 2 Denominator & Post
1366
    case 0x1e:                        // VCLK 3 Denominator & Post
1367
    case 0x1f:                        // BIOS Write Enable and MCLK select
1368
        s->vga.sr[reg_index] = reg_value;
1369
#ifdef DEBUG_CIRRUS
1370
        printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1371
               reg_index, reg_value);
1372
#endif
1373
        break;
1374
    case 0x17:                        // Configuration Readback and Extended Control
1375
        s->vga.sr[reg_index] = (s->vga.sr[reg_index] & 0x38) | (reg_value & 0xc7);
1376
        cirrus_update_memory_access(s);
1377
        break;
1378
    default:
1379
#ifdef DEBUG_CIRRUS
1380
        printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1381
               reg_value);
1382
#endif
1383
        break;
1384
    }
1385

    
1386
    return CIRRUS_HOOK_HANDLED;
1387
}
1388

    
1389
/***************************************
1390
 *
1391
 *  I/O access at 0x3c6
1392
 *
1393
 ***************************************/
1394

    
1395
static int cirrus_read_hidden_dac(CirrusVGAState * s)
1396
{
1397
    if (++s->cirrus_hidden_dac_lockindex == 5) {
1398
        s->cirrus_hidden_dac_lockindex = 0;
1399
        return s->cirrus_hidden_dac_data;
1400
    }
1401
    return 0xff;
1402
}
1403

    
1404
static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1405
{
1406
    if (s->cirrus_hidden_dac_lockindex == 4) {
1407
        s->cirrus_hidden_dac_data = reg_value;
1408
#if defined(DEBUG_CIRRUS)
1409
        printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1410
#endif
1411
    }
1412
    s->cirrus_hidden_dac_lockindex = 0;
1413
}
1414

    
1415
/***************************************
1416
 *
1417
 *  I/O access at 0x3c9
1418
 *
1419
 ***************************************/
1420

    
1421
static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1422
{
1423
    if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1424
        return CIRRUS_HOOK_NOT_HANDLED;
1425
    *reg_value =
1426
        s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1427
                                 s->vga.dac_sub_index];
1428
    if (++s->vga.dac_sub_index == 3) {
1429
        s->vga.dac_sub_index = 0;
1430
        s->vga.dac_read_index++;
1431
    }
1432
    return CIRRUS_HOOK_HANDLED;
1433
}
1434

    
1435
static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1436
{
1437
    if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1438
        return CIRRUS_HOOK_NOT_HANDLED;
1439
    s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1440
    if (++s->vga.dac_sub_index == 3) {
1441
        memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1442
               s->vga.dac_cache, 3);
1443
        /* XXX update cursor */
1444
        s->vga.dac_sub_index = 0;
1445
        s->vga.dac_write_index++;
1446
    }
1447
    return CIRRUS_HOOK_HANDLED;
1448
}
1449

    
1450
/***************************************
1451
 *
1452
 *  I/O access between 0x3ce-0x3cf
1453
 *
1454
 ***************************************/
1455

    
1456
static int
1457
cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1458
{
1459
    switch (reg_index) {
1460
    case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1461
      *reg_value = s->cirrus_shadow_gr0;
1462
      return CIRRUS_HOOK_HANDLED;
1463
    case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1464
      *reg_value = s->cirrus_shadow_gr1;
1465
      return CIRRUS_HOOK_HANDLED;
1466
    case 0x02:                        // Standard VGA
1467
    case 0x03:                        // Standard VGA
1468
    case 0x04:                        // Standard VGA
1469
    case 0x06:                        // Standard VGA
1470
    case 0x07:                        // Standard VGA
1471
    case 0x08:                        // Standard VGA
1472
        return CIRRUS_HOOK_NOT_HANDLED;
1473
    case 0x05:                        // Standard VGA, Cirrus extended mode
1474
    default:
1475
        break;
1476
    }
1477

    
1478
    if (reg_index < 0x3a) {
1479
        *reg_value = s->vga.gr[reg_index];
1480
    } else {
1481
#ifdef DEBUG_CIRRUS
1482
        printf("cirrus: inport gr_index %02x\n", reg_index);
1483
#endif
1484
        *reg_value = 0xff;
1485
    }
1486

    
1487
    return CIRRUS_HOOK_HANDLED;
1488
}
1489

    
1490
static int
1491
cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1492
{
1493
#if defined(DEBUG_BITBLT) && 0
1494
    printf("gr%02x: %02x\n", reg_index, reg_value);
1495
#endif
1496
    switch (reg_index) {
1497
    case 0x00:                        // Standard VGA, BGCOLOR 0x000000ff
1498
        s->cirrus_shadow_gr0 = reg_value;
1499
        return CIRRUS_HOOK_NOT_HANDLED;
1500
    case 0x01:                        // Standard VGA, FGCOLOR 0x000000ff
1501
        s->cirrus_shadow_gr1 = reg_value;
1502
        return CIRRUS_HOOK_NOT_HANDLED;
1503
    case 0x02:                        // Standard VGA
1504
    case 0x03:                        // Standard VGA
1505
    case 0x04:                        // Standard VGA
1506
    case 0x06:                        // Standard VGA
1507
    case 0x07:                        // Standard VGA
1508
    case 0x08:                        // Standard VGA
1509
        return CIRRUS_HOOK_NOT_HANDLED;
1510
    case 0x05:                        // Standard VGA, Cirrus extended mode
1511
        s->vga.gr[reg_index] = reg_value & 0x7f;
1512
        cirrus_update_memory_access(s);
1513
        break;
1514
    case 0x09:                        // bank offset #0
1515
    case 0x0A:                        // bank offset #1
1516
        s->vga.gr[reg_index] = reg_value;
1517
        cirrus_update_bank_ptr(s, 0);
1518
        cirrus_update_bank_ptr(s, 1);
1519
        cirrus_update_memory_access(s);
1520
        break;
1521
    case 0x0B:
1522
        s->vga.gr[reg_index] = reg_value;
1523
        cirrus_update_bank_ptr(s, 0);
1524
        cirrus_update_bank_ptr(s, 1);
1525
        cirrus_update_memory_access(s);
1526
        break;
1527
    case 0x10:                        // BGCOLOR 0x0000ff00
1528
    case 0x11:                        // FGCOLOR 0x0000ff00
1529
    case 0x12:                        // BGCOLOR 0x00ff0000
1530
    case 0x13:                        // FGCOLOR 0x00ff0000
1531
    case 0x14:                        // BGCOLOR 0xff000000
1532
    case 0x15:                        // FGCOLOR 0xff000000
1533
    case 0x20:                        // BLT WIDTH 0x0000ff
1534
    case 0x22:                        // BLT HEIGHT 0x0000ff
1535
    case 0x24:                        // BLT DEST PITCH 0x0000ff
1536
    case 0x26:                        // BLT SRC PITCH 0x0000ff
1537
    case 0x28:                        // BLT DEST ADDR 0x0000ff
1538
    case 0x29:                        // BLT DEST ADDR 0x00ff00
1539
    case 0x2c:                        // BLT SRC ADDR 0x0000ff
1540
    case 0x2d:                        // BLT SRC ADDR 0x00ff00
1541
    case 0x2f:                  // BLT WRITEMASK
1542
    case 0x30:                        // BLT MODE
1543
    case 0x32:                        // RASTER OP
1544
    case 0x33:                        // BLT MODEEXT
1545
    case 0x34:                        // BLT TRANSPARENT COLOR 0x00ff
1546
    case 0x35:                        // BLT TRANSPARENT COLOR 0xff00
1547
    case 0x38:                        // BLT TRANSPARENT COLOR MASK 0x00ff
1548
    case 0x39:                        // BLT TRANSPARENT COLOR MASK 0xff00
1549
        s->vga.gr[reg_index] = reg_value;
1550
        break;
1551
    case 0x21:                        // BLT WIDTH 0x001f00
1552
    case 0x23:                        // BLT HEIGHT 0x001f00
1553
    case 0x25:                        // BLT DEST PITCH 0x001f00
1554
    case 0x27:                        // BLT SRC PITCH 0x001f00
1555
        s->vga.gr[reg_index] = reg_value & 0x1f;
1556
        break;
1557
    case 0x2a:                        // BLT DEST ADDR 0x3f0000
1558
        s->vga.gr[reg_index] = reg_value & 0x3f;
1559
        /* if auto start mode, starts bit blt now */
1560
        if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1561
            cirrus_bitblt_start(s);
1562
        }
1563
        break;
1564
    case 0x2e:                        // BLT SRC ADDR 0x3f0000
1565
        s->vga.gr[reg_index] = reg_value & 0x3f;
1566
        break;
1567
    case 0x31:                        // BLT STATUS/START
1568
        cirrus_write_bitblt(s, reg_value);
1569
        break;
1570
    default:
1571
#ifdef DEBUG_CIRRUS
1572
        printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1573
               reg_value);
1574
#endif
1575
        break;
1576
    }
1577

    
1578
    return CIRRUS_HOOK_HANDLED;
1579
}
1580

    
1581
/***************************************
1582
 *
1583
 *  I/O access between 0x3d4-0x3d5
1584
 *
1585
 ***************************************/
1586

    
1587
static int
1588
cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1589
{
1590
    switch (reg_index) {
1591
    case 0x00:                        // Standard VGA
1592
    case 0x01:                        // Standard VGA
1593
    case 0x02:                        // Standard VGA
1594
    case 0x03:                        // Standard VGA
1595
    case 0x04:                        // Standard VGA
1596
    case 0x05:                        // Standard VGA
1597
    case 0x06:                        // Standard VGA
1598
    case 0x07:                        // Standard VGA
1599
    case 0x08:                        // Standard VGA
1600
    case 0x09:                        // Standard VGA
1601
    case 0x0a:                        // Standard VGA
1602
    case 0x0b:                        // Standard VGA
1603
    case 0x0c:                        // Standard VGA
1604
    case 0x0d:                        // Standard VGA
1605
    case 0x0e:                        // Standard VGA
1606
    case 0x0f:                        // Standard VGA
1607
    case 0x10:                        // Standard VGA
1608
    case 0x11:                        // Standard VGA
1609
    case 0x12:                        // Standard VGA
1610
    case 0x13:                        // Standard VGA
1611
    case 0x14:                        // Standard VGA
1612
    case 0x15:                        // Standard VGA
1613
    case 0x16:                        // Standard VGA
1614
    case 0x17:                        // Standard VGA
1615
    case 0x18:                        // Standard VGA
1616
        return CIRRUS_HOOK_NOT_HANDLED;
1617
    case 0x24:                        // Attribute Controller Toggle Readback (R)
1618
        *reg_value = (s->vga.ar_flip_flop << 7);
1619
        break;
1620
    case 0x19:                        // Interlace End
1621
    case 0x1a:                        // Miscellaneous Control
1622
    case 0x1b:                        // Extended Display Control
1623
    case 0x1c:                        // Sync Adjust and Genlock
1624
    case 0x1d:                        // Overlay Extended Control
1625
    case 0x22:                        // Graphics Data Latches Readback (R)
1626
    case 0x25:                        // Part Status
1627
    case 0x27:                        // Part ID (R)
1628
        *reg_value = s->vga.cr[reg_index];
1629
        break;
1630
    case 0x26:                        // Attribute Controller Index Readback (R)
1631
        *reg_value = s->vga.ar_index & 0x3f;
1632
        break;
1633
    default:
1634
#ifdef DEBUG_CIRRUS
1635
        printf("cirrus: inport cr_index %02x\n", reg_index);
1636
        *reg_value = 0xff;
1637
#endif
1638
        break;
1639
    }
1640

    
1641
    return CIRRUS_HOOK_HANDLED;
1642
}
1643

    
1644
static int
1645
cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1646
{
1647
    switch (reg_index) {
1648
    case 0x00:                        // Standard VGA
1649
    case 0x01:                        // Standard VGA
1650
    case 0x02:                        // Standard VGA
1651
    case 0x03:                        // Standard VGA
1652
    case 0x04:                        // Standard VGA
1653
    case 0x05:                        // Standard VGA
1654
    case 0x06:                        // Standard VGA
1655
    case 0x07:                        // Standard VGA
1656
    case 0x08:                        // Standard VGA
1657
    case 0x09:                        // Standard VGA
1658
    case 0x0a:                        // Standard VGA
1659
    case 0x0b:                        // Standard VGA
1660
    case 0x0c:                        // Standard VGA
1661
    case 0x0d:                        // Standard VGA
1662
    case 0x0e:                        // Standard VGA
1663
    case 0x0f:                        // Standard VGA
1664
    case 0x10:                        // Standard VGA
1665
    case 0x11:                        // Standard VGA
1666
    case 0x12:                        // Standard VGA
1667
    case 0x13:                        // Standard VGA
1668
    case 0x14:                        // Standard VGA
1669
    case 0x15:                        // Standard VGA
1670
    case 0x16:                        // Standard VGA
1671
    case 0x17:                        // Standard VGA
1672
    case 0x18:                        // Standard VGA
1673
        return CIRRUS_HOOK_NOT_HANDLED;
1674
    case 0x19:                        // Interlace End
1675
    case 0x1a:                        // Miscellaneous Control
1676
    case 0x1b:                        // Extended Display Control
1677
    case 0x1c:                        // Sync Adjust and Genlock
1678
    case 0x1d:                        // Overlay Extended Control
1679
        s->vga.cr[reg_index] = reg_value;
1680
#ifdef DEBUG_CIRRUS
1681
        printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1682
               reg_index, reg_value);
1683
#endif
1684
        break;
1685
    case 0x22:                        // Graphics Data Latches Readback (R)
1686
    case 0x24:                        // Attribute Controller Toggle Readback (R)
1687
    case 0x26:                        // Attribute Controller Index Readback (R)
1688
    case 0x27:                        // Part ID (R)
1689
        break;
1690
    case 0x25:                        // Part Status
1691
    default:
1692
#ifdef DEBUG_CIRRUS
1693
        printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1694
               reg_value);
1695
#endif
1696
        break;
1697
    }
1698

    
1699
    return CIRRUS_HOOK_HANDLED;
1700
}
1701

    
1702
/***************************************
1703
 *
1704
 *  memory-mapped I/O (bitblt)
1705
 *
1706
 ***************************************/
1707

    
1708
static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1709
{
1710
    int value = 0xff;
1711

    
1712
    switch (address) {
1713
    case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1714
        cirrus_hook_read_gr(s, 0x00, &value);
1715
        break;
1716
    case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1717
        cirrus_hook_read_gr(s, 0x10, &value);
1718
        break;
1719
    case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1720
        cirrus_hook_read_gr(s, 0x12, &value);
1721
        break;
1722
    case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1723
        cirrus_hook_read_gr(s, 0x14, &value);
1724
        break;
1725
    case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1726
        cirrus_hook_read_gr(s, 0x01, &value);
1727
        break;
1728
    case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1729
        cirrus_hook_read_gr(s, 0x11, &value);
1730
        break;
1731
    case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1732
        cirrus_hook_read_gr(s, 0x13, &value);
1733
        break;
1734
    case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1735
        cirrus_hook_read_gr(s, 0x15, &value);
1736
        break;
1737
    case (CIRRUS_MMIO_BLTWIDTH + 0):
1738
        cirrus_hook_read_gr(s, 0x20, &value);
1739
        break;
1740
    case (CIRRUS_MMIO_BLTWIDTH + 1):
1741
        cirrus_hook_read_gr(s, 0x21, &value);
1742
        break;
1743
    case (CIRRUS_MMIO_BLTHEIGHT + 0):
1744
        cirrus_hook_read_gr(s, 0x22, &value);
1745
        break;
1746
    case (CIRRUS_MMIO_BLTHEIGHT + 1):
1747
        cirrus_hook_read_gr(s, 0x23, &value);
1748
        break;
1749
    case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1750
        cirrus_hook_read_gr(s, 0x24, &value);
1751
        break;
1752
    case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1753
        cirrus_hook_read_gr(s, 0x25, &value);
1754
        break;
1755
    case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1756
        cirrus_hook_read_gr(s, 0x26, &value);
1757
        break;
1758
    case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1759
        cirrus_hook_read_gr(s, 0x27, &value);
1760
        break;
1761
    case (CIRRUS_MMIO_BLTDESTADDR + 0):
1762
        cirrus_hook_read_gr(s, 0x28, &value);
1763
        break;
1764
    case (CIRRUS_MMIO_BLTDESTADDR + 1):
1765
        cirrus_hook_read_gr(s, 0x29, &value);
1766
        break;
1767
    case (CIRRUS_MMIO_BLTDESTADDR + 2):
1768
        cirrus_hook_read_gr(s, 0x2a, &value);
1769
        break;
1770
    case (CIRRUS_MMIO_BLTSRCADDR + 0):
1771
        cirrus_hook_read_gr(s, 0x2c, &value);
1772
        break;
1773
    case (CIRRUS_MMIO_BLTSRCADDR + 1):
1774
        cirrus_hook_read_gr(s, 0x2d, &value);
1775
        break;
1776
    case (CIRRUS_MMIO_BLTSRCADDR + 2):
1777
        cirrus_hook_read_gr(s, 0x2e, &value);
1778
        break;
1779
    case CIRRUS_MMIO_BLTWRITEMASK:
1780
        cirrus_hook_read_gr(s, 0x2f, &value);
1781
        break;
1782
    case CIRRUS_MMIO_BLTMODE:
1783
        cirrus_hook_read_gr(s, 0x30, &value);
1784
        break;
1785
    case CIRRUS_MMIO_BLTROP:
1786
        cirrus_hook_read_gr(s, 0x32, &value);
1787
        break;
1788
    case CIRRUS_MMIO_BLTMODEEXT:
1789
        cirrus_hook_read_gr(s, 0x33, &value);
1790
        break;
1791
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1792
        cirrus_hook_read_gr(s, 0x34, &value);
1793
        break;
1794
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1795
        cirrus_hook_read_gr(s, 0x35, &value);
1796
        break;
1797
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1798
        cirrus_hook_read_gr(s, 0x38, &value);
1799
        break;
1800
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1801
        cirrus_hook_read_gr(s, 0x39, &value);
1802
        break;
1803
    case CIRRUS_MMIO_BLTSTATUS:
1804
        cirrus_hook_read_gr(s, 0x31, &value);
1805
        break;
1806
    default:
1807
#ifdef DEBUG_CIRRUS
1808
        printf("cirrus: mmio read - address 0x%04x\n", address);
1809
#endif
1810
        break;
1811
    }
1812

    
1813
    return (uint8_t) value;
1814
}
1815

    
1816
static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1817
                                  uint8_t value)
1818
{
1819
    switch (address) {
1820
    case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1821
        cirrus_hook_write_gr(s, 0x00, value);
1822
        break;
1823
    case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1824
        cirrus_hook_write_gr(s, 0x10, value);
1825
        break;
1826
    case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1827
        cirrus_hook_write_gr(s, 0x12, value);
1828
        break;
1829
    case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1830
        cirrus_hook_write_gr(s, 0x14, value);
1831
        break;
1832
    case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1833
        cirrus_hook_write_gr(s, 0x01, value);
1834
        break;
1835
    case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1836
        cirrus_hook_write_gr(s, 0x11, value);
1837
        break;
1838
    case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1839
        cirrus_hook_write_gr(s, 0x13, value);
1840
        break;
1841
    case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1842
        cirrus_hook_write_gr(s, 0x15, value);
1843
        break;
1844
    case (CIRRUS_MMIO_BLTWIDTH + 0):
1845
        cirrus_hook_write_gr(s, 0x20, value);
1846
        break;
1847
    case (CIRRUS_MMIO_BLTWIDTH + 1):
1848
        cirrus_hook_write_gr(s, 0x21, value);
1849
        break;
1850
    case (CIRRUS_MMIO_BLTHEIGHT + 0):
1851
        cirrus_hook_write_gr(s, 0x22, value);
1852
        break;
1853
    case (CIRRUS_MMIO_BLTHEIGHT + 1):
1854
        cirrus_hook_write_gr(s, 0x23, value);
1855
        break;
1856
    case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1857
        cirrus_hook_write_gr(s, 0x24, value);
1858
        break;
1859
    case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1860
        cirrus_hook_write_gr(s, 0x25, value);
1861
        break;
1862
    case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1863
        cirrus_hook_write_gr(s, 0x26, value);
1864
        break;
1865
    case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1866
        cirrus_hook_write_gr(s, 0x27, value);
1867
        break;
1868
    case (CIRRUS_MMIO_BLTDESTADDR + 0):
1869
        cirrus_hook_write_gr(s, 0x28, value);
1870
        break;
1871
    case (CIRRUS_MMIO_BLTDESTADDR + 1):
1872
        cirrus_hook_write_gr(s, 0x29, value);
1873
        break;
1874
    case (CIRRUS_MMIO_BLTDESTADDR + 2):
1875
        cirrus_hook_write_gr(s, 0x2a, value);
1876
        break;
1877
    case (CIRRUS_MMIO_BLTDESTADDR + 3):
1878
        /* ignored */
1879
        break;
1880
    case (CIRRUS_MMIO_BLTSRCADDR + 0):
1881
        cirrus_hook_write_gr(s, 0x2c, value);
1882
        break;
1883
    case (CIRRUS_MMIO_BLTSRCADDR + 1):
1884
        cirrus_hook_write_gr(s, 0x2d, value);
1885
        break;
1886
    case (CIRRUS_MMIO_BLTSRCADDR + 2):
1887
        cirrus_hook_write_gr(s, 0x2e, value);
1888
        break;
1889
    case CIRRUS_MMIO_BLTWRITEMASK:
1890
        cirrus_hook_write_gr(s, 0x2f, value);
1891
        break;
1892
    case CIRRUS_MMIO_BLTMODE:
1893
        cirrus_hook_write_gr(s, 0x30, value);
1894
        break;
1895
    case CIRRUS_MMIO_BLTROP:
1896
        cirrus_hook_write_gr(s, 0x32, value);
1897
        break;
1898
    case CIRRUS_MMIO_BLTMODEEXT:
1899
        cirrus_hook_write_gr(s, 0x33, value);
1900
        break;
1901
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1902
        cirrus_hook_write_gr(s, 0x34, value);
1903
        break;
1904
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1905
        cirrus_hook_write_gr(s, 0x35, value);
1906
        break;
1907
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1908
        cirrus_hook_write_gr(s, 0x38, value);
1909
        break;
1910
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1911
        cirrus_hook_write_gr(s, 0x39, value);
1912
        break;
1913
    case CIRRUS_MMIO_BLTSTATUS:
1914
        cirrus_hook_write_gr(s, 0x31, value);
1915
        break;
1916
    default:
1917
#ifdef DEBUG_CIRRUS
1918
        printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1919
               address, value);
1920
#endif
1921
        break;
1922
    }
1923
}
1924

    
1925
/***************************************
1926
 *
1927
 *  write mode 4/5
1928
 *
1929
 * assume TARGET_PAGE_SIZE >= 16
1930
 *
1931
 ***************************************/
1932

    
1933
static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1934
                                             unsigned mode,
1935
                                             unsigned offset,
1936
                                             uint32_t mem_value)
1937
{
1938
    int x;
1939
    unsigned val = mem_value;
1940
    uint8_t *dst;
1941

    
1942
    dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
1943
    for (x = 0; x < 8; x++) {
1944
        if (val & 0x80) {
1945
            *dst = s->cirrus_shadow_gr1;
1946
        } else if (mode == 5) {
1947
            *dst = s->cirrus_shadow_gr0;
1948
        }
1949
        val <<= 1;
1950
        dst++;
1951
    }
1952
    cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
1953
    cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 7);
1954
}
1955

    
1956
static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1957
                                              unsigned mode,
1958
                                              unsigned offset,
1959
                                              uint32_t mem_value)
1960
{
1961
    int x;
1962
    unsigned val = mem_value;
1963
    uint8_t *dst;
1964

    
1965
    dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
1966
    for (x = 0; x < 8; x++) {
1967
        if (val & 0x80) {
1968
            *dst = s->cirrus_shadow_gr1;
1969
            *(dst + 1) = s->vga.gr[0x11];
1970
        } else if (mode == 5) {
1971
            *dst = s->cirrus_shadow_gr0;
1972
            *(dst + 1) = s->vga.gr[0x10];
1973
        }
1974
        val <<= 1;
1975
        dst += 2;
1976
    }
1977
    cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
1978
    cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 15);
1979
}
1980

    
1981
/***************************************
1982
 *
1983
 *  memory access between 0xa0000-0xbffff
1984
 *
1985
 ***************************************/
1986

    
1987
static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
1988
{
1989
    CirrusVGAState *s = opaque;
1990
    unsigned bank_index;
1991
    unsigned bank_offset;
1992
    uint32_t val;
1993

    
1994
    if ((s->vga.sr[0x07] & 0x01) == 0) {
1995
        return vga_mem_readb(s, addr);
1996
    }
1997

    
1998
    addr &= 0x1ffff;
1999

    
2000
    if (addr < 0x10000) {
2001
        /* XXX handle bitblt */
2002
        /* video memory */
2003
        bank_index = addr >> 15;
2004
        bank_offset = addr & 0x7fff;
2005
        if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2006
            bank_offset += s->cirrus_bank_base[bank_index];
2007
            if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2008
                bank_offset <<= 4;
2009
            } else if (s->vga.gr[0x0B] & 0x02) {
2010
                bank_offset <<= 3;
2011
            }
2012
            bank_offset &= s->cirrus_addr_mask;
2013
            val = *(s->vga.vram_ptr + bank_offset);
2014
        } else
2015
            val = 0xff;
2016
    } else if (addr >= 0x18000 && addr < 0x18100) {
2017
        /* memory-mapped I/O */
2018
        val = 0xff;
2019
        if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2020
            val = cirrus_mmio_blt_read(s, addr & 0xff);
2021
        }
2022
    } else {
2023
        val = 0xff;
2024
#ifdef DEBUG_CIRRUS
2025
        printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
2026
#endif
2027
    }
2028
    return val;
2029
}
2030

    
2031
static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
2032
{
2033
    uint32_t v;
2034
#ifdef TARGET_WORDS_BIGENDIAN
2035
    v = cirrus_vga_mem_readb(opaque, addr) << 8;
2036
    v |= cirrus_vga_mem_readb(opaque, addr + 1);
2037
#else
2038
    v = cirrus_vga_mem_readb(opaque, addr);
2039
    v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2040
#endif
2041
    return v;
2042
}
2043

    
2044
static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
2045
{
2046
    uint32_t v;
2047
#ifdef TARGET_WORDS_BIGENDIAN
2048
    v = cirrus_vga_mem_readb(opaque, addr) << 24;
2049
    v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2050
    v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2051
    v |= cirrus_vga_mem_readb(opaque, addr + 3);
2052
#else
2053
    v = cirrus_vga_mem_readb(opaque, addr);
2054
    v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2055
    v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2056
    v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2057
#endif
2058
    return v;
2059
}
2060

    
2061
static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
2062
                                  uint32_t mem_value)
2063
{
2064
    CirrusVGAState *s = opaque;
2065
    unsigned bank_index;
2066
    unsigned bank_offset;
2067
    unsigned mode;
2068

    
2069
    if ((s->vga.sr[0x07] & 0x01) == 0) {
2070
        vga_mem_writeb(s, addr, mem_value);
2071
        return;
2072
    }
2073

    
2074
    addr &= 0x1ffff;
2075

    
2076
    if (addr < 0x10000) {
2077
        if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2078
            /* bitblt */
2079
            *s->cirrus_srcptr++ = (uint8_t) mem_value;
2080
            if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2081
                cirrus_bitblt_cputovideo_next(s);
2082
            }
2083
        } else {
2084
            /* video memory */
2085
            bank_index = addr >> 15;
2086
            bank_offset = addr & 0x7fff;
2087
            if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2088
                bank_offset += s->cirrus_bank_base[bank_index];
2089
                if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2090
                    bank_offset <<= 4;
2091
                } else if (s->vga.gr[0x0B] & 0x02) {
2092
                    bank_offset <<= 3;
2093
                }
2094
                bank_offset &= s->cirrus_addr_mask;
2095
                mode = s->vga.gr[0x05] & 0x7;
2096
                if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2097
                    *(s->vga.vram_ptr + bank_offset) = mem_value;
2098
                    cpu_physical_memory_set_dirty(s->vga.vram_offset +
2099
                                                  bank_offset);
2100
                } else {
2101
                    if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2102
                        cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2103
                                                         bank_offset,
2104
                                                         mem_value);
2105
                    } else {
2106
                        cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2107
                                                          bank_offset,
2108
                                                          mem_value);
2109
                    }
2110
                }
2111
            }
2112
        }
2113
    } else if (addr >= 0x18000 && addr < 0x18100) {
2114
        /* memory-mapped I/O */
2115
        if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2116
            cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2117
        }
2118
    } else {
2119
#ifdef DEBUG_CIRRUS
2120
        printf("cirrus: mem_writeb " TARGET_FMT_plx " value %02x\n", addr,
2121
               mem_value);
2122
#endif
2123
    }
2124
}
2125

    
2126
static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2127
{
2128
#ifdef TARGET_WORDS_BIGENDIAN
2129
    cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2130
    cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2131
#else
2132
    cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2133
    cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2134
#endif
2135
}
2136

    
2137
static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2138
{
2139
#ifdef TARGET_WORDS_BIGENDIAN
2140
    cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2141
    cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2142
    cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2143
    cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2144
#else
2145
    cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2146
    cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2147
    cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2148
    cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2149
#endif
2150
}
2151

    
2152
static CPUReadMemoryFunc * const cirrus_vga_mem_read[3] = {
2153
    cirrus_vga_mem_readb,
2154
    cirrus_vga_mem_readw,
2155
    cirrus_vga_mem_readl,
2156
};
2157

    
2158
static CPUWriteMemoryFunc * const cirrus_vga_mem_write[3] = {
2159
    cirrus_vga_mem_writeb,
2160
    cirrus_vga_mem_writew,
2161
    cirrus_vga_mem_writel,
2162
};
2163

    
2164
/***************************************
2165
 *
2166
 *  hardware cursor
2167
 *
2168
 ***************************************/
2169

    
2170
static inline void invalidate_cursor1(CirrusVGAState *s)
2171
{
2172
    if (s->last_hw_cursor_size) {
2173
        vga_invalidate_scanlines(&s->vga,
2174
                                 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2175
                                 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2176
    }
2177
}
2178

    
2179
static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2180
{
2181
    const uint8_t *src;
2182
    uint32_t content;
2183
    int y, y_min, y_max;
2184

    
2185
    src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2186
    if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2187
        src += (s->vga.sr[0x13] & 0x3c) * 256;
2188
        y_min = 64;
2189
        y_max = -1;
2190
        for(y = 0; y < 64; y++) {
2191
            content = ((uint32_t *)src)[0] |
2192
                ((uint32_t *)src)[1] |
2193
                ((uint32_t *)src)[2] |
2194
                ((uint32_t *)src)[3];
2195
            if (content) {
2196
                if (y < y_min)
2197
                    y_min = y;
2198
                if (y > y_max)
2199
                    y_max = y;
2200
            }
2201
            src += 16;
2202
        }
2203
    } else {
2204
        src += (s->vga.sr[0x13] & 0x3f) * 256;
2205
        y_min = 32;
2206
        y_max = -1;
2207
        for(y = 0; y < 32; y++) {
2208
            content = ((uint32_t *)src)[0] |
2209
                ((uint32_t *)(src + 128))[0];
2210
            if (content) {
2211
                if (y < y_min)
2212
                    y_min = y;
2213
                if (y > y_max)
2214
                    y_max = y;
2215
            }
2216
            src += 4;
2217
        }
2218
    }
2219
    if (y_min > y_max) {
2220
        s->last_hw_cursor_y_start = 0;
2221
        s->last_hw_cursor_y_end = 0;
2222
    } else {
2223
        s->last_hw_cursor_y_start = y_min;
2224
        s->last_hw_cursor_y_end = y_max + 1;
2225
    }
2226
}
2227

    
2228
/* NOTE: we do not currently handle the cursor bitmap change, so we
2229
   update the cursor only if it moves. */
2230
static void cirrus_cursor_invalidate(VGACommonState *s1)
2231
{
2232
    CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2233
    int size;
2234

    
2235
    if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
2236
        size = 0;
2237
    } else {
2238
        if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
2239
            size = 64;
2240
        else
2241
            size = 32;
2242
    }
2243
    /* invalidate last cursor and new cursor if any change */
2244
    if (s->last_hw_cursor_size != size ||
2245
        s->last_hw_cursor_x != s->hw_cursor_x ||
2246
        s->last_hw_cursor_y != s->hw_cursor_y) {
2247

    
2248
        invalidate_cursor1(s);
2249

    
2250
        s->last_hw_cursor_size = size;
2251
        s->last_hw_cursor_x = s->hw_cursor_x;
2252
        s->last_hw_cursor_y = s->hw_cursor_y;
2253
        /* compute the real cursor min and max y */
2254
        cirrus_cursor_compute_yrange(s);
2255
        invalidate_cursor1(s);
2256
    }
2257
}
2258

    
2259
static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
2260
{
2261
    CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2262
    int w, h, bpp, x1, x2, poffset;
2263
    unsigned int color0, color1;
2264
    const uint8_t *palette, *src;
2265
    uint32_t content;
2266

    
2267
    if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
2268
        return;
2269
    /* fast test to see if the cursor intersects with the scan line */
2270
    if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2271
        h = 64;
2272
    } else {
2273
        h = 32;
2274
    }
2275
    if (scr_y < s->hw_cursor_y ||
2276
        scr_y >= (s->hw_cursor_y + h))
2277
        return;
2278

    
2279
    src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2280
    if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2281
        src += (s->vga.sr[0x13] & 0x3c) * 256;
2282
        src += (scr_y - s->hw_cursor_y) * 16;
2283
        poffset = 8;
2284
        content = ((uint32_t *)src)[0] |
2285
            ((uint32_t *)src)[1] |
2286
            ((uint32_t *)src)[2] |
2287
            ((uint32_t *)src)[3];
2288
    } else {
2289
        src += (s->vga.sr[0x13] & 0x3f) * 256;
2290
        src += (scr_y - s->hw_cursor_y) * 4;
2291
        poffset = 128;
2292
        content = ((uint32_t *)src)[0] |
2293
            ((uint32_t *)(src + 128))[0];
2294
    }
2295
    /* if nothing to draw, no need to continue */
2296
    if (!content)
2297
        return;
2298
    w = h;
2299

    
2300
    x1 = s->hw_cursor_x;
2301
    if (x1 >= s->vga.last_scr_width)
2302
        return;
2303
    x2 = s->hw_cursor_x + w;
2304
    if (x2 > s->vga.last_scr_width)
2305
        x2 = s->vga.last_scr_width;
2306
    w = x2 - x1;
2307
    palette = s->cirrus_hidden_palette;
2308
    color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2309
                                 c6_to_8(palette[0x0 * 3 + 1]),
2310
                                 c6_to_8(palette[0x0 * 3 + 2]));
2311
    color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2312
                                 c6_to_8(palette[0xf * 3 + 1]),
2313
                                 c6_to_8(palette[0xf * 3 + 2]));
2314
    bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3);
2315
    d1 += x1 * bpp;
2316
    switch(ds_get_bits_per_pixel(s->vga.ds)) {
2317
    default:
2318
        break;
2319
    case 8:
2320
        vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2321
        break;
2322
    case 15:
2323
        vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2324
        break;
2325
    case 16:
2326
        vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2327
        break;
2328
    case 32:
2329
        vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2330
        break;
2331
    }
2332
}
2333

    
2334
/***************************************
2335
 *
2336
 *  LFB memory access
2337
 *
2338
 ***************************************/
2339

    
2340
static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2341
{
2342
    CirrusVGAState *s = opaque;
2343
    uint32_t ret;
2344

    
2345
    addr &= s->cirrus_addr_mask;
2346

    
2347
    if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2348
        ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2349
        /* memory-mapped I/O */
2350
        ret = cirrus_mmio_blt_read(s, addr & 0xff);
2351
    } else if (0) {
2352
        /* XXX handle bitblt */
2353
        ret = 0xff;
2354
    } else {
2355
        /* video memory */
2356
        if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2357
            addr <<= 4;
2358
        } else if (s->vga.gr[0x0B] & 0x02) {
2359
            addr <<= 3;
2360
        }
2361
        addr &= s->cirrus_addr_mask;
2362
        ret = *(s->vga.vram_ptr + addr);
2363
    }
2364

    
2365
    return ret;
2366
}
2367

    
2368
static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2369
{
2370
    uint32_t v;
2371
#ifdef TARGET_WORDS_BIGENDIAN
2372
    v = cirrus_linear_readb(opaque, addr) << 8;
2373
    v |= cirrus_linear_readb(opaque, addr + 1);
2374
#else
2375
    v = cirrus_linear_readb(opaque, addr);
2376
    v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2377
#endif
2378
    return v;
2379
}
2380

    
2381
static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2382
{
2383
    uint32_t v;
2384
#ifdef TARGET_WORDS_BIGENDIAN
2385
    v = cirrus_linear_readb(opaque, addr) << 24;
2386
    v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2387
    v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2388
    v |= cirrus_linear_readb(opaque, addr + 3);
2389
#else
2390
    v = cirrus_linear_readb(opaque, addr);
2391
    v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2392
    v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2393
    v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2394
#endif
2395
    return v;
2396
}
2397

    
2398
static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2399
                                 uint32_t val)
2400
{
2401
    CirrusVGAState *s = opaque;
2402
    unsigned mode;
2403

    
2404
    addr &= s->cirrus_addr_mask;
2405

    
2406
    if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2407
        ((addr & s->linear_mmio_mask) ==  s->linear_mmio_mask)) {
2408
        /* memory-mapped I/O */
2409
        cirrus_mmio_blt_write(s, addr & 0xff, val);
2410
    } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2411
        /* bitblt */
2412
        *s->cirrus_srcptr++ = (uint8_t) val;
2413
        if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2414
            cirrus_bitblt_cputovideo_next(s);
2415
        }
2416
    } else {
2417
        /* video memory */
2418
        if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2419
            addr <<= 4;
2420
        } else if (s->vga.gr[0x0B] & 0x02) {
2421
            addr <<= 3;
2422
        }
2423
        addr &= s->cirrus_addr_mask;
2424

    
2425
        mode = s->vga.gr[0x05] & 0x7;
2426
        if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2427
            *(s->vga.vram_ptr + addr) = (uint8_t) val;
2428
            cpu_physical_memory_set_dirty(s->vga.vram_offset + addr);
2429
        } else {
2430
            if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2431
                cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2432
            } else {
2433
                cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2434
            }
2435
        }
2436
    }
2437
}
2438

    
2439
static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2440
                                 uint32_t val)
2441
{
2442
#ifdef TARGET_WORDS_BIGENDIAN
2443
    cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2444
    cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2445
#else
2446
    cirrus_linear_writeb(opaque, addr, val & 0xff);
2447
    cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2448
#endif
2449
}
2450

    
2451
static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2452
                                 uint32_t val)
2453
{
2454
#ifdef TARGET_WORDS_BIGENDIAN
2455
    cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2456
    cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2457
    cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2458
    cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2459
#else
2460
    cirrus_linear_writeb(opaque, addr, val & 0xff);
2461
    cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2462
    cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2463
    cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2464
#endif
2465
}
2466

    
2467

    
2468
static CPUReadMemoryFunc * const cirrus_linear_read[3] = {
2469
    cirrus_linear_readb,
2470
    cirrus_linear_readw,
2471
    cirrus_linear_readl,
2472
};
2473

    
2474
static CPUWriteMemoryFunc * const cirrus_linear_write[3] = {
2475
    cirrus_linear_writeb,
2476
    cirrus_linear_writew,
2477
    cirrus_linear_writel,
2478
};
2479

    
2480
/***************************************
2481
 *
2482
 *  system to screen memory access
2483
 *
2484
 ***************************************/
2485

    
2486

    
2487
static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2488
{
2489
    uint32_t ret;
2490

    
2491
    /* XXX handle bitblt */
2492
    ret = 0xff;
2493
    return ret;
2494
}
2495

    
2496
static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2497
{
2498
    uint32_t v;
2499
#ifdef TARGET_WORDS_BIGENDIAN
2500
    v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2501
    v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2502
#else
2503
    v = cirrus_linear_bitblt_readb(opaque, addr);
2504
    v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2505
#endif
2506
    return v;
2507
}
2508

    
2509
static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2510
{
2511
    uint32_t v;
2512
#ifdef TARGET_WORDS_BIGENDIAN
2513
    v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2514
    v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2515
    v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2516
    v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2517
#else
2518
    v = cirrus_linear_bitblt_readb(opaque, addr);
2519
    v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2520
    v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2521
    v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2522
#endif
2523
    return v;
2524
}
2525

    
2526
static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2527
                                 uint32_t val)
2528
{
2529
    CirrusVGAState *s = opaque;
2530

    
2531
    if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2532
        /* bitblt */
2533
        *s->cirrus_srcptr++ = (uint8_t) val;
2534
        if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2535
            cirrus_bitblt_cputovideo_next(s);
2536
        }
2537
    }
2538
}
2539

    
2540
static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2541
                                 uint32_t val)
2542
{
2543
#ifdef TARGET_WORDS_BIGENDIAN
2544
    cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2545
    cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2546
#else
2547
    cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2548
    cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2549
#endif
2550
}
2551

    
2552
static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2553
                                 uint32_t val)
2554
{
2555
#ifdef TARGET_WORDS_BIGENDIAN
2556
    cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2557
    cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2558
    cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2559
    cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2560
#else
2561
    cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2562
    cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2563
    cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2564
    cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2565
#endif
2566
}
2567

    
2568

    
2569
static CPUReadMemoryFunc * const cirrus_linear_bitblt_read[3] = {
2570
    cirrus_linear_bitblt_readb,
2571
    cirrus_linear_bitblt_readw,
2572
    cirrus_linear_bitblt_readl,
2573
};
2574

    
2575
static CPUWriteMemoryFunc * const cirrus_linear_bitblt_write[3] = {
2576
    cirrus_linear_bitblt_writeb,
2577
    cirrus_linear_bitblt_writew,
2578
    cirrus_linear_bitblt_writel,
2579
};
2580

    
2581
static void map_linear_vram(CirrusVGAState *s)
2582
{
2583
    if (!s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) {
2584
        s->vga.map_addr = s->vga.lfb_addr;
2585
        s->vga.map_end = s->vga.lfb_end;
2586
        cpu_register_physical_memory(s->vga.map_addr, s->vga.map_end - s->vga.map_addr, s->vga.vram_offset);
2587
    }
2588

    
2589
    if (!s->vga.map_addr)
2590
        return;
2591

    
2592
    s->vga.lfb_vram_mapped = 0;
2593

    
2594
    if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
2595
        && !((s->vga.sr[0x07] & 0x01) == 0)
2596
        && !((s->vga.gr[0x0B] & 0x14) == 0x14)
2597
        && !(s->vga.gr[0x0B] & 0x02)) {
2598

    
2599
        cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2600
                                    (s->vga.vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
2601
        cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2602
                                    (s->vga.vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
2603

    
2604
        s->vga.lfb_vram_mapped = 1;
2605
    }
2606
    else {
2607
        cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2608
                                     s->vga.vga_io_memory);
2609
    }
2610

    
2611
    vga_dirty_log_start(&s->vga);
2612
}
2613

    
2614
static void unmap_linear_vram(CirrusVGAState *s)
2615
{
2616
    if (s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end)
2617
        s->vga.map_addr = s->vga.map_end = 0;
2618

    
2619
    cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2620
                                 s->vga.vga_io_memory);
2621
}
2622

    
2623
/* Compute the memory access functions */
2624
static void cirrus_update_memory_access(CirrusVGAState *s)
2625
{
2626
    unsigned mode;
2627

    
2628
    if ((s->vga.sr[0x17] & 0x44) == 0x44) {
2629
        goto generic_io;
2630
    } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2631
        goto generic_io;
2632
    } else {
2633
        if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2634
            goto generic_io;
2635
        } else if (s->vga.gr[0x0B] & 0x02) {
2636
            goto generic_io;
2637
        }
2638

    
2639
        mode = s->vga.gr[0x05] & 0x7;
2640
        if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2641
            map_linear_vram(s);
2642
        } else {
2643
        generic_io:
2644
            unmap_linear_vram(s);
2645
        }
2646
    }
2647
}
2648

    
2649

    
2650
/* I/O ports */
2651

    
2652
static uint32_t cirrus_vga_ioport_read(void *opaque, uint32_t addr)
2653
{
2654
    CirrusVGAState *c = opaque;
2655
    VGACommonState *s = &c->vga;
2656
    int val, index;
2657

    
2658
    if (vga_ioport_invalid(s, addr)) {
2659
        val = 0xff;
2660
    } else {
2661
        switch (addr) {
2662
        case 0x3c0:
2663
            if (s->ar_flip_flop == 0) {
2664
                val = s->ar_index;
2665
            } else {
2666
                val = 0;
2667
            }
2668
            break;
2669
        case 0x3c1:
2670
            index = s->ar_index & 0x1f;
2671
            if (index < 21)
2672
                val = s->ar[index];
2673
            else
2674
                val = 0;
2675
            break;
2676
        case 0x3c2:
2677
            val = s->st00;
2678
            break;
2679
        case 0x3c4:
2680
            val = s->sr_index;
2681
            break;
2682
        case 0x3c5:
2683
            val = cirrus_vga_read_sr(c);
2684
            break;
2685
#ifdef DEBUG_VGA_REG
2686
            printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2687
#endif
2688
            break;
2689
        case 0x3c6:
2690
            val = cirrus_read_hidden_dac(c);
2691
            break;
2692
        case 0x3c7:
2693
            val = s->dac_state;
2694
            break;
2695
        case 0x3c8:
2696
            val = s->dac_write_index;
2697
            c->cirrus_hidden_dac_lockindex = 0;
2698
            break;
2699
        case 0x3c9:
2700
            if (cirrus_hook_read_palette(c, &val))
2701
                break;
2702
            val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2703
            if (++s->dac_sub_index == 3) {
2704
                s->dac_sub_index = 0;
2705
                s->dac_read_index++;
2706
            }
2707
            break;
2708
        case 0x3ca:
2709
            val = s->fcr;
2710
            break;
2711
        case 0x3cc:
2712
            val = s->msr;
2713
            break;
2714
        case 0x3ce:
2715
            val = s->gr_index;
2716
            break;
2717
        case 0x3cf:
2718
            if (cirrus_hook_read_gr(c, s->gr_index, &val))
2719
                break;
2720
            val = s->gr[s->gr_index];
2721
#ifdef DEBUG_VGA_REG
2722
            printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2723
#endif
2724
            break;
2725
        case 0x3b4:
2726
        case 0x3d4:
2727
            val = s->cr_index;
2728
            break;
2729
        case 0x3b5:
2730
        case 0x3d5:
2731
            if (cirrus_hook_read_cr(c, s->cr_index, &val))
2732
                break;
2733
            val = s->cr[s->cr_index];
2734
#ifdef DEBUG_VGA_REG
2735
            printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2736
#endif
2737
            break;
2738
        case 0x3ba:
2739
        case 0x3da:
2740
            /* just toggle to fool polling */
2741
            val = s->st01 = s->retrace(s);
2742
            s->ar_flip_flop = 0;
2743
            break;
2744
        default:
2745
            val = 0x00;
2746
            break;
2747
        }
2748
    }
2749
#if defined(DEBUG_VGA)
2750
    printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2751
#endif
2752
    return val;
2753
}
2754

    
2755
static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2756
{
2757
    CirrusVGAState *c = opaque;
2758
    VGACommonState *s = &c->vga;
2759
    int index;
2760

    
2761
    /* check port range access depending on color/monochrome mode */
2762
    if (vga_ioport_invalid(s, addr)) {
2763
        return;
2764
    }
2765
#ifdef DEBUG_VGA
2766
    printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2767
#endif
2768

    
2769
    switch (addr) {
2770
    case 0x3c0:
2771
        if (s->ar_flip_flop == 0) {
2772
            val &= 0x3f;
2773
            s->ar_index = val;
2774
        } else {
2775
            index = s->ar_index & 0x1f;
2776
            switch (index) {
2777
            case 0x00 ... 0x0f:
2778
                s->ar[index] = val & 0x3f;
2779
                break;
2780
            case 0x10:
2781
                s->ar[index] = val & ~0x10;
2782
                break;
2783
            case 0x11:
2784
                s->ar[index] = val;
2785
                break;
2786
            case 0x12:
2787
                s->ar[index] = val & ~0xc0;
2788
                break;
2789
            case 0x13:
2790
                s->ar[index] = val & ~0xf0;
2791
                break;
2792
            case 0x14:
2793
                s->ar[index] = val & ~0xf0;
2794
                break;
2795
            default:
2796
                break;
2797
            }
2798
        }
2799
        s->ar_flip_flop ^= 1;
2800
        break;
2801
    case 0x3c2:
2802
        s->msr = val & ~0x10;
2803
        s->update_retrace_info(s);
2804
        break;
2805
    case 0x3c4:
2806
        s->sr_index = val;
2807
        break;
2808
    case 0x3c5:
2809
        if (cirrus_hook_write_sr(c, s->sr_index, val))
2810
            break;
2811
#ifdef DEBUG_VGA_REG
2812
        printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2813
#endif
2814
        s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2815
        if (s->sr_index == 1) s->update_retrace_info(s);
2816
        break;
2817
    case 0x3c6:
2818
        cirrus_write_hidden_dac(c, val);
2819
        break;
2820
    case 0x3c7:
2821
        s->dac_read_index = val;
2822
        s->dac_sub_index = 0;
2823
        s->dac_state = 3;
2824
        break;
2825
    case 0x3c8:
2826
        s->dac_write_index = val;
2827
        s->dac_sub_index = 0;
2828
        s->dac_state = 0;
2829
        break;
2830
    case 0x3c9:
2831
        if (cirrus_hook_write_palette(c, val))
2832
            break;
2833
        s->dac_cache[s->dac_sub_index] = val;
2834
        if (++s->dac_sub_index == 3) {
2835
            memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2836
            s->dac_sub_index = 0;
2837
            s->dac_write_index++;
2838
        }
2839
        break;
2840
    case 0x3ce:
2841
        s->gr_index = val;
2842
        break;
2843
    case 0x3cf:
2844
        if (cirrus_hook_write_gr(c, s->gr_index, val))
2845
            break;
2846
#ifdef DEBUG_VGA_REG
2847
        printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2848
#endif
2849
        s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2850
        break;
2851
    case 0x3b4:
2852
    case 0x3d4:
2853
        s->cr_index = val;
2854
        break;
2855
    case 0x3b5:
2856
    case 0x3d5:
2857
        if (cirrus_hook_write_cr(c, s->cr_index, val))
2858
            break;
2859
#ifdef DEBUG_VGA_REG
2860
        printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2861
#endif
2862
        /* handle CR0-7 protection */
2863
        if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
2864
            /* can always write bit 4 of CR7 */
2865
            if (s->cr_index == 7)
2866
                s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2867
            return;
2868
        }
2869
        s->cr[s->cr_index] = val;
2870

    
2871
        switch(s->cr_index) {
2872
        case 0x00:
2873
        case 0x04:
2874
        case 0x05:
2875
        case 0x06:
2876
        case 0x07:
2877
        case 0x11:
2878
        case 0x17:
2879
            s->update_retrace_info(s);
2880
            break;
2881
        }
2882
        break;
2883
    case 0x3ba:
2884
    case 0x3da:
2885
        s->fcr = val & 0x10;
2886
        break;
2887
    }
2888
}
2889

    
2890
/***************************************
2891
 *
2892
 *  memory-mapped I/O access
2893
 *
2894
 ***************************************/
2895

    
2896
static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2897
{
2898
    CirrusVGAState *s = opaque;
2899

    
2900
    addr &= CIRRUS_PNPMMIO_SIZE - 1;
2901

    
2902
    if (addr >= 0x100) {
2903
        return cirrus_mmio_blt_read(s, addr - 0x100);
2904
    } else {
2905
        return cirrus_vga_ioport_read(s, addr + 0x3c0);
2906
    }
2907
}
2908

    
2909
static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2910
{
2911
    uint32_t v;
2912
#ifdef TARGET_WORDS_BIGENDIAN
2913
    v = cirrus_mmio_readb(opaque, addr) << 8;
2914
    v |= cirrus_mmio_readb(opaque, addr + 1);
2915
#else
2916
    v = cirrus_mmio_readb(opaque, addr);
2917
    v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2918
#endif
2919
    return v;
2920
}
2921

    
2922
static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
2923
{
2924
    uint32_t v;
2925
#ifdef TARGET_WORDS_BIGENDIAN
2926
    v = cirrus_mmio_readb(opaque, addr) << 24;
2927
    v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
2928
    v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
2929
    v |= cirrus_mmio_readb(opaque, addr + 3);
2930
#else
2931
    v = cirrus_mmio_readb(opaque, addr);
2932
    v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2933
    v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
2934
    v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
2935
#endif
2936
    return v;
2937
}
2938

    
2939
static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
2940
                               uint32_t val)
2941
{
2942
    CirrusVGAState *s = opaque;
2943

    
2944
    addr &= CIRRUS_PNPMMIO_SIZE - 1;
2945

    
2946
    if (addr >= 0x100) {
2947
        cirrus_mmio_blt_write(s, addr - 0x100, val);
2948
    } else {
2949
        cirrus_vga_ioport_write(s, addr + 0x3c0, val);
2950
    }
2951
}
2952

    
2953
static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
2954
                               uint32_t val)
2955
{
2956
#ifdef TARGET_WORDS_BIGENDIAN
2957
    cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
2958
    cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
2959
#else
2960
    cirrus_mmio_writeb(opaque, addr, val & 0xff);
2961
    cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2962
#endif
2963
}
2964

    
2965
static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
2966
                               uint32_t val)
2967
{
2968
#ifdef TARGET_WORDS_BIGENDIAN
2969
    cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
2970
    cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2971
    cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2972
    cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
2973
#else
2974
    cirrus_mmio_writeb(opaque, addr, val & 0xff);
2975
    cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2976
    cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2977
    cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2978
#endif
2979
}
2980

    
2981

    
2982
static CPUReadMemoryFunc * const cirrus_mmio_read[3] = {
2983
    cirrus_mmio_readb,
2984
    cirrus_mmio_readw,
2985
    cirrus_mmio_readl,
2986
};
2987

    
2988
static CPUWriteMemoryFunc * const cirrus_mmio_write[3] = {
2989
    cirrus_mmio_writeb,
2990
    cirrus_mmio_writew,
2991
    cirrus_mmio_writel,
2992
};
2993

    
2994
/* load/save state */
2995

    
2996
static void cirrus_vga_save(QEMUFile *f, void *opaque)
2997
{
2998
    CirrusVGAState *s = opaque;
2999

    
3000
    qemu_put_be32s(f, &s->vga.latch);
3001
    qemu_put_8s(f, &s->vga.sr_index);
3002
    qemu_put_buffer(f, s->vga.sr, 256);
3003
    qemu_put_8s(f, &s->vga.gr_index);
3004
    qemu_put_8s(f, &s->cirrus_shadow_gr0);
3005
    qemu_put_8s(f, &s->cirrus_shadow_gr1);
3006
    qemu_put_buffer(f, s->vga.gr + 2, 254);
3007
    qemu_put_8s(f, &s->vga.ar_index);
3008
    qemu_put_buffer(f, s->vga.ar, 21);
3009
    qemu_put_be32(f, s->vga.ar_flip_flop);
3010
    qemu_put_8s(f, &s->vga.cr_index);
3011
    qemu_put_buffer(f, s->vga.cr, 256);
3012
    qemu_put_8s(f, &s->vga.msr);
3013
    qemu_put_8s(f, &s->vga.fcr);
3014
    qemu_put_8s(f, &s->vga.st00);
3015
    qemu_put_8s(f, &s->vga.st01);
3016

    
3017
    qemu_put_8s(f, &s->vga.dac_state);
3018
    qemu_put_8s(f, &s->vga.dac_sub_index);
3019
    qemu_put_8s(f, &s->vga.dac_read_index);
3020
    qemu_put_8s(f, &s->vga.dac_write_index);
3021
    qemu_put_buffer(f, s->vga.dac_cache, 3);
3022
    qemu_put_buffer(f, s->vga.palette, 768);
3023

    
3024
    qemu_put_be32(f, s->vga.bank_offset);
3025

    
3026
    qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3027
    qemu_put_8s(f, &s->cirrus_hidden_dac_data);
3028

    
3029
    qemu_put_be32s(f, &s->hw_cursor_x);
3030
    qemu_put_be32s(f, &s->hw_cursor_y);
3031
    /* XXX: we do not save the bitblt state - we assume we do not save
3032
       the state when the blitter is active */
3033
}
3034

    
3035
static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3036
{
3037
    CirrusVGAState *s = opaque;
3038

    
3039
    if (version_id > 2)
3040
        return -EINVAL;
3041

    
3042
    qemu_get_be32s(f, &s->vga.latch);
3043
    qemu_get_8s(f, &s->vga.sr_index);
3044
    qemu_get_buffer(f, s->vga.sr, 256);
3045
    qemu_get_8s(f, &s->vga.gr_index);
3046
    qemu_get_8s(f, &s->cirrus_shadow_gr0);
3047
    qemu_get_8s(f, &s->cirrus_shadow_gr1);
3048
    s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3049
    s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3050
    qemu_get_buffer(f, s->vga.gr + 2, 254);
3051
    qemu_get_8s(f, &s->vga.ar_index);
3052
    qemu_get_buffer(f, s->vga.ar, 21);
3053
    s->vga.ar_flip_flop=qemu_get_be32(f);
3054
    qemu_get_8s(f, &s->vga.cr_index);
3055
    qemu_get_buffer(f, s->vga.cr, 256);
3056
    qemu_get_8s(f, &s->vga.msr);
3057
    qemu_get_8s(f, &s->vga.fcr);
3058
    qemu_get_8s(f, &s->vga.st00);
3059
    qemu_get_8s(f, &s->vga.st01);
3060

    
3061
    qemu_get_8s(f, &s->vga.dac_state);
3062
    qemu_get_8s(f, &s->vga.dac_sub_index);
3063
    qemu_get_8s(f, &s->vga.dac_read_index);
3064
    qemu_get_8s(f, &s->vga.dac_write_index);
3065
    qemu_get_buffer(f, s->vga.dac_cache, 3);
3066
    qemu_get_buffer(f, s->vga.palette, 768);
3067

    
3068
    s->vga.bank_offset = qemu_get_be32(f);
3069

    
3070
    qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3071
    qemu_get_8s(f, &s->cirrus_hidden_dac_data);
3072

    
3073
    qemu_get_be32s(f, &s->hw_cursor_x);
3074
    qemu_get_be32s(f, &s->hw_cursor_y);
3075

    
3076
    cirrus_update_memory_access(s);
3077
    /* force refresh */
3078
    s->vga.graphic_mode = -1;
3079
    cirrus_update_bank_ptr(s, 0);
3080
    cirrus_update_bank_ptr(s, 1);
3081
    return 0;
3082
}
3083

    
3084
static void pci_cirrus_vga_save(QEMUFile *f, void *opaque)
3085
{
3086
    PCICirrusVGAState *s = opaque;
3087

    
3088
    pci_device_save(&s->dev, f);
3089
    cirrus_vga_save(f, &s->cirrus_vga);
3090
}
3091

    
3092
static int pci_cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3093
{
3094
    PCICirrusVGAState *s = opaque;
3095
    int ret;
3096

    
3097
    if (version_id > 2)
3098
        return -EINVAL;
3099

    
3100
    if (version_id >= 2) {
3101
        ret = pci_device_load(&s->dev, f);
3102
        if (ret < 0)
3103
            return ret;
3104
    }
3105

    
3106
    return cirrus_vga_load(f, &s->cirrus_vga, version_id);
3107
}
3108

    
3109
/***************************************
3110
 *
3111
 *  initialize
3112
 *
3113
 ***************************************/
3114

    
3115
static void cirrus_reset(void *opaque)
3116
{
3117
    CirrusVGAState *s = opaque;
3118

    
3119
    vga_common_reset(&s->vga);
3120
    unmap_linear_vram(s);
3121
    s->vga.sr[0x06] = 0x0f;
3122
    if (s->device_id == CIRRUS_ID_CLGD5446) {
3123
        /* 4MB 64 bit memory config, always PCI */
3124
        s->vga.sr[0x1F] = 0x2d;                // MemClock
3125
        s->vga.gr[0x18] = 0x0f;             // fastest memory configuration
3126
        s->vga.sr[0x0f] = 0x98;
3127
        s->vga.sr[0x17] = 0x20;
3128
        s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3129
    } else {
3130
        s->vga.sr[0x1F] = 0x22;                // MemClock
3131
        s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
3132
        s->vga.sr[0x17] = s->bustype;
3133
        s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3134
    }
3135
    s->vga.cr[0x27] = s->device_id;
3136

    
3137
    /* Win2K seems to assume that the pattern buffer is at 0xff
3138
       initially ! */
3139
    memset(s->vga.vram_ptr, 0xff, s->real_vram_size);
3140

    
3141
    s->cirrus_hidden_dac_lockindex = 5;
3142
    s->cirrus_hidden_dac_data = 0;
3143
}
3144

    
3145
static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3146
{
3147
    int i;
3148
    static int inited;
3149

    
3150
    if (!inited) {
3151
        inited = 1;
3152
        for(i = 0;i < 256; i++)
3153
            rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3154
        rop_to_index[CIRRUS_ROP_0] = 0;
3155
        rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3156
        rop_to_index[CIRRUS_ROP_NOP] = 2;
3157
        rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3158
        rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3159
        rop_to_index[CIRRUS_ROP_SRC] = 5;
3160
        rop_to_index[CIRRUS_ROP_1] = 6;
3161
        rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3162
        rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3163
        rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3164
        rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3165
        rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3166
        rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3167
        rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3168
        rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3169
        rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3170
        s->device_id = device_id;
3171
        if (is_pci)
3172
            s->bustype = CIRRUS_BUSTYPE_PCI;
3173
        else
3174
            s->bustype = CIRRUS_BUSTYPE_ISA;
3175
    }
3176

    
3177
    register_ioport_write(0x3c0, 16, 1, cirrus_vga_ioport_write, s);
3178

    
3179
    register_ioport_write(0x3b4, 2, 1, cirrus_vga_ioport_write, s);
3180
    register_ioport_write(0x3d4, 2, 1, cirrus_vga_ioport_write, s);
3181
    register_ioport_write(0x3ba, 1, 1, cirrus_vga_ioport_write, s);
3182
    register_ioport_write(0x3da, 1, 1, cirrus_vga_ioport_write, s);
3183

    
3184
    register_ioport_read(0x3c0, 16, 1, cirrus_vga_ioport_read, s);
3185

    
3186
    register_ioport_read(0x3b4, 2, 1, cirrus_vga_ioport_read, s);
3187
    register_ioport_read(0x3d4, 2, 1, cirrus_vga_ioport_read, s);
3188
    register_ioport_read(0x3ba, 1, 1, cirrus_vga_ioport_read, s);
3189
    register_ioport_read(0x3da, 1, 1, cirrus_vga_ioport_read, s);
3190

    
3191
    s->vga.vga_io_memory = cpu_register_io_memory(cirrus_vga_mem_read,
3192
                                                  cirrus_vga_mem_write, s);
3193
    cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3194
                                 s->vga.vga_io_memory);
3195
    qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
3196

    
3197
    /* I/O handler for LFB */
3198
    s->cirrus_linear_io_addr =
3199
        cpu_register_io_memory(cirrus_linear_read, cirrus_linear_write, s);
3200

    
3201
    /* I/O handler for LFB */
3202
    s->cirrus_linear_bitblt_io_addr =
3203
        cpu_register_io_memory(cirrus_linear_bitblt_read,
3204
                               cirrus_linear_bitblt_write, s);
3205

    
3206
    /* I/O handler for memory-mapped I/O */
3207
    s->cirrus_mmio_io_addr =
3208
        cpu_register_io_memory(cirrus_mmio_read, cirrus_mmio_write, s);
3209

    
3210
    s->real_vram_size =
3211
        (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
3212

    
3213
    /* XXX: s->vga.vram_size must be a power of two */
3214
    s->cirrus_addr_mask = s->real_vram_size - 1;
3215
    s->linear_mmio_mask = s->real_vram_size - 256;
3216

    
3217
    s->vga.get_bpp = cirrus_get_bpp;
3218
    s->vga.get_offsets = cirrus_get_offsets;
3219
    s->vga.get_resolution = cirrus_get_resolution;
3220
    s->vga.cursor_invalidate = cirrus_cursor_invalidate;
3221
    s->vga.cursor_draw_line = cirrus_cursor_draw_line;
3222

    
3223
    qemu_register_reset(cirrus_reset, s);
3224
    cirrus_reset(s);
3225
}
3226

    
3227
/***************************************
3228
 *
3229
 *  ISA bus support
3230
 *
3231
 ***************************************/
3232

    
3233
void isa_cirrus_vga_init(void)
3234
{
3235
    CirrusVGAState *s;
3236

    
3237
    s = qemu_mallocz(sizeof(CirrusVGAState));
3238

    
3239
    vga_common_init(&s->vga, VGA_RAM_SIZE);
3240
    cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3241
    s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
3242
                                     s->vga.screen_dump, s->vga.text_update,
3243
                                     &s->vga);
3244
    register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
3245
    /* XXX ISA-LFB support */
3246
}
3247

    
3248
/***************************************
3249
 *
3250
 *  PCI bus support
3251
 *
3252
 ***************************************/
3253

    
3254
static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3255
                               uint32_t addr, uint32_t size, int type)
3256
{
3257
    CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga;
3258

    
3259
    /* XXX: add byte swapping apertures */
3260
    cpu_register_physical_memory(addr, s->vga.vram_size,
3261
                                 s->cirrus_linear_io_addr);
3262
    cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3263
                                 s->cirrus_linear_bitblt_io_addr);
3264

    
3265
    s->vga.map_addr = s->vga.map_end = 0;
3266
    s->vga.lfb_addr = addr & TARGET_PAGE_MASK;
3267
    s->vga.lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
3268
    /* account for overflow */
3269
    if (s->vga.lfb_end < addr + VGA_RAM_SIZE)
3270
        s->vga.lfb_end = addr + VGA_RAM_SIZE;
3271

    
3272
    vga_dirty_log_start(&s->vga);
3273
}
3274

    
3275
static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3276
                                uint32_t addr, uint32_t size, int type)
3277
{
3278
    CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga;
3279

    
3280
    cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3281
                                 s->cirrus_mmio_io_addr);
3282
}
3283

    
3284
static void pci_cirrus_write_config(PCIDevice *d,
3285
                                    uint32_t address, uint32_t val, int len)
3286
{
3287
    PCICirrusVGAState *pvs = DO_UPCAST(PCICirrusVGAState, dev, d);
3288
    CirrusVGAState *s = &pvs->cirrus_vga;
3289

    
3290
    pci_default_write_config(d, address, val, len);
3291
    if (s->vga.map_addr && d->io_regions[0].addr == -1)
3292
        s->vga.map_addr = 0;
3293
    cirrus_update_memory_access(s);
3294
}
3295

    
3296
static int pci_cirrus_vga_initfn(PCIDevice *dev)
3297
{
3298
     PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
3299
     CirrusVGAState *s = &d->cirrus_vga;
3300
     uint8_t *pci_conf = d->dev.config;
3301
     int device_id = CIRRUS_ID_CLGD5446;
3302

    
3303
     /* setup VGA */
3304
     vga_common_init(&s->vga, VGA_RAM_SIZE);
3305
     cirrus_init_common(s, device_id, 1);
3306
     s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
3307
                                      s->vga.screen_dump, s->vga.text_update,
3308
                                      &s->vga);
3309

    
3310
     /* setup PCI */
3311
     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS);
3312
     pci_config_set_device_id(pci_conf, device_id);
3313
     pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3314
     pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
3315
     pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
3316

    
3317
     /* setup memory space */
3318
     /* memory #0 LFB */
3319
     /* memory #1 memory-mapped I/O */
3320
     /* XXX: s->vga.vram_size must be a power of two */
3321
     pci_register_bar((PCIDevice *)d, 0, 0x2000000,
3322
                      PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
3323
     if (device_id == CIRRUS_ID_CLGD5446) {
3324
         pci_register_bar((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3325
                          PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3326
     }
3327
     register_savevm("cirrus_vga", 0, 2, pci_cirrus_vga_save, pci_cirrus_vga_load, d);
3328
     /* XXX: ROM BIOS */
3329
     return 0;
3330
}
3331

    
3332
void pci_cirrus_vga_init(PCIBus *bus)
3333
{
3334
    pci_create_simple(bus, -1, "Cirrus VGA");
3335
}
3336

    
3337
static PCIDeviceInfo cirrus_vga_info = {
3338
    .qdev.name    = "Cirrus VGA",
3339
    .qdev.size    = sizeof(PCICirrusVGAState),
3340
    .init         = pci_cirrus_vga_initfn,
3341
    .config_write = pci_cirrus_write_config,
3342
};
3343

    
3344
static void cirrus_vga_register(void)
3345
{
3346
    pci_qdev_register(&cirrus_vga_info);
3347
}
3348
device_init(cirrus_vga_register);