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/*
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* QEMU PC System Emulator
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "fdc.h" |
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#include "pci.h" |
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#include "vmware_vga.h" |
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#include "usb-uhci.h" |
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#include "usb-ohci.h" |
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#include "prep_pci.h" |
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#include "apb_pci.h" |
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#include "block.h" |
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#include "sysemu.h" |
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#include "audio/audio.h" |
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#include "net.h" |
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#include "smbus.h" |
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#include "boards.h" |
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#include "monitor.h" |
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#include "fw_cfg.h" |
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#include "hpet_emul.h" |
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#include "watchdog.h" |
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#include "smbios.h" |
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#include "ide.h" |
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#include "loader.h" |
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#include "elf.h" |
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#include "multiboot.h" |
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|
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/* output Bochs bios info messages */
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//#define DEBUG_BIOS
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|
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#define BIOS_FILENAME "bios.bin" |
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|
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#define PC_MAX_BIOS_SIZE (4 * 1024 * 1024) |
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|
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/* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
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#define ACPI_DATA_SIZE 0x10000 |
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#define BIOS_CFG_IOPORT 0x510 |
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#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
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#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
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#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
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#define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) |
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#define MAX_IDE_BUS 2 |
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|
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static FDCtrl *floppy_controller;
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static RTCState *rtc_state;
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static PITState *pit;
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static PCII440FXState *i440fx_state;
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|
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#define E820_NR_ENTRIES 16 |
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|
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struct e820_entry {
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uint64_t address; |
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uint64_t length; |
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uint32_t type; |
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}; |
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|
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struct e820_table {
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uint32_t count; |
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struct e820_entry entry[E820_NR_ENTRIES];
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}; |
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static struct e820_table e820_table; |
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|
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typedef struct isa_irq_state { |
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qemu_irq *i8259; |
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qemu_irq *ioapic; |
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} IsaIrqState; |
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|
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static void isa_irq_handler(void *opaque, int n, int level) |
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{ |
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IsaIrqState *isa = (IsaIrqState *)opaque; |
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if (n < 16) { |
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qemu_set_irq(isa->i8259[n], level); |
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} |
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if (isa->ioapic)
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qemu_set_irq(isa->ioapic[n], level); |
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}; |
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|
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static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
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{ |
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} |
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|
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/* MSDOS compatibility mode FPU exception support */
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static qemu_irq ferr_irq;
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/* XXX: add IGNNE support */
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void cpu_set_ferr(CPUX86State *s)
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{ |
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qemu_irq_raise(ferr_irq); |
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} |
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static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) |
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{ |
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qemu_irq_lower(ferr_irq); |
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} |
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|
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/* TSC handling */
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uint64_t cpu_get_tsc(CPUX86State *env) |
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{ |
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return cpu_get_ticks();
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} |
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|
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/* SMM support */
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void cpu_smm_update(CPUState *env)
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{ |
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if (i440fx_state && env == first_cpu)
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i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
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} |
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/* IRQ handling */
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int cpu_get_pic_interrupt(CPUState *env)
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{ |
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int intno;
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intno = apic_get_interrupt(env); |
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if (intno >= 0) { |
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/* set irq request if a PIC irq is still pending */
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/* XXX: improve that */
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pic_update_irq(isa_pic); |
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return intno;
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} |
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/* read the irq from the PIC */
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if (!apic_accept_pic_intr(env))
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return -1; |
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intno = pic_read_irq(isa_pic); |
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return intno;
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} |
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static void pic_irq_request(void *opaque, int irq, int level) |
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{ |
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CPUState *env = first_cpu; |
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if (env->apic_state) {
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while (env) {
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if (apic_accept_pic_intr(env))
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apic_deliver_pic_intr(env, level); |
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env = env->next_cpu; |
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} |
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} else {
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if (level)
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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else
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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} |
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/* PC cmos mappings */
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#define REG_EQUIPMENT_BYTE 0x14 |
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static int cmos_get_fd_drive_type(int fd0) |
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{ |
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int val;
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switch (fd0) {
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case 0: |
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/* 1.44 Mb 3"5 drive */
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val = 4;
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break;
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case 1: |
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/* 2.88 Mb 3"5 drive */
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val = 5;
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break;
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case 2: |
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/* 1.2 Mb 5"5 drive */
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val = 2;
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break;
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default:
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val = 0;
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break;
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} |
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return val;
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} |
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static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd) |
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{ |
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RTCState *s = rtc_state; |
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int cylinders, heads, sectors;
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bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors); |
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rtc_set_memory(s, type_ofs, 47);
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rtc_set_memory(s, info_ofs, cylinders); |
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rtc_set_memory(s, info_ofs + 1, cylinders >> 8); |
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rtc_set_memory(s, info_ofs + 2, heads);
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rtc_set_memory(s, info_ofs + 3, 0xff); |
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rtc_set_memory(s, info_ofs + 4, 0xff); |
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rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); |
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rtc_set_memory(s, info_ofs + 6, cylinders);
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rtc_set_memory(s, info_ofs + 7, cylinders >> 8); |
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rtc_set_memory(s, info_ofs + 8, sectors);
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} |
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/* convert boot_device letter to something recognizable by the bios */
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static int boot_device2nibble(char boot_device) |
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{ |
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switch(boot_device) {
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case 'a': |
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case 'b': |
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return 0x01; /* floppy boot */ |
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case 'c': |
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return 0x02; /* hard drive boot */ |
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case 'd': |
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return 0x03; /* CD-ROM boot */ |
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case 'n': |
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return 0x04; /* Network boot */ |
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} |
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return 0; |
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} |
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/* copy/pasted from cmos_init, should be made a general function
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and used there as well */
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static int pc_boot_set(void *opaque, const char *boot_device) |
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{ |
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#define PC_MAX_BOOT_DEVICES 3 |
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RTCState *s = (RTCState *)opaque; |
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int nbds, bds[3] = { 0, }; |
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int i;
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nbds = strlen(boot_device); |
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if (nbds > PC_MAX_BOOT_DEVICES) {
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qemu_error("Too many boot devices for PC\n");
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return(1); |
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} |
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for (i = 0; i < nbds; i++) { |
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bds[i] = boot_device2nibble(boot_device[i]); |
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if (bds[i] == 0) { |
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qemu_error("Invalid boot device for PC: '%c'\n",
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boot_device[i]); |
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return(1); |
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} |
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} |
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rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); |
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rtc_set_memory(s, 0x38, (bds[2] << 4)); |
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return(0); |
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} |
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|
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/* hd_table must contain 4 block drivers */
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static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, |
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const char *boot_device, DriveInfo **hd_table) |
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{ |
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RTCState *s = rtc_state; |
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int nbds, bds[3] = { 0, }; |
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int val;
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int fd0, fd1, nb;
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int i;
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/* various important CMOS locations needed by PC/Bochs bios */
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/* memory size */
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val = 640; /* base memory in K */ |
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rtc_set_memory(s, 0x15, val);
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rtc_set_memory(s, 0x16, val >> 8); |
276 |
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val = (ram_size / 1024) - 1024; |
278 |
if (val > 65535) |
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val = 65535;
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rtc_set_memory(s, 0x17, val);
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rtc_set_memory(s, 0x18, val >> 8); |
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rtc_set_memory(s, 0x30, val);
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rtc_set_memory(s, 0x31, val >> 8); |
284 |
|
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if (above_4g_mem_size) {
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rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); |
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rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); |
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rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); |
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} |
290 |
|
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if (ram_size > (16 * 1024 * 1024)) |
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val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); |
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else
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val = 0;
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if (val > 65535) |
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val = 65535;
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rtc_set_memory(s, 0x34, val);
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rtc_set_memory(s, 0x35, val >> 8); |
299 |
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/* set the number of CPU */
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rtc_set_memory(s, 0x5f, smp_cpus - 1); |
302 |
|
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/* set boot devices, and disable floppy signature check if requested */
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#define PC_MAX_BOOT_DEVICES 3 |
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nbds = strlen(boot_device); |
306 |
if (nbds > PC_MAX_BOOT_DEVICES) {
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fprintf(stderr, "Too many boot devices for PC\n");
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exit(1);
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} |
310 |
for (i = 0; i < nbds; i++) { |
311 |
bds[i] = boot_device2nibble(boot_device[i]); |
312 |
if (bds[i] == 0) { |
313 |
fprintf(stderr, "Invalid boot device for PC: '%c'\n",
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boot_device[i]); |
315 |
exit(1);
|
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} |
317 |
} |
318 |
rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); |
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rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
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|
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/* floppy type */
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fd0 = fdctrl_get_drive_type(floppy_controller, 0);
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fd1 = fdctrl_get_drive_type(floppy_controller, 1);
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|
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val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
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rtc_set_memory(s, 0x10, val);
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|
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val = 0;
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nb = 0;
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if (fd0 < 3) |
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nb++; |
333 |
if (fd1 < 3) |
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nb++; |
335 |
switch (nb) {
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case 0: |
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break;
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case 1: |
339 |
val |= 0x01; /* 1 drive, ready for boot */ |
340 |
break;
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case 2: |
342 |
val |= 0x41; /* 2 drives, ready for boot */ |
343 |
break;
|
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} |
345 |
val |= 0x02; /* FPU is there */ |
346 |
val |= 0x04; /* PS/2 mouse installed */ |
347 |
rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); |
348 |
|
349 |
/* hard drives */
|
350 |
|
351 |
rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0)); |
352 |
if (hd_table[0]) |
353 |
cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv); |
354 |
if (hd_table[1]) |
355 |
cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv); |
356 |
|
357 |
val = 0;
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358 |
for (i = 0; i < 4; i++) { |
359 |
if (hd_table[i]) {
|
360 |
int cylinders, heads, sectors, translation;
|
361 |
/* NOTE: bdrv_get_geometry_hint() returns the physical
|
362 |
geometry. It is always such that: 1 <= sects <= 63, 1
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363 |
<= heads <= 16, 1 <= cylinders <= 16383. The BIOS
|
364 |
geometry can be different if a translation is done. */
|
365 |
translation = bdrv_get_translation_hint(hd_table[i]->bdrv); |
366 |
if (translation == BIOS_ATA_TRANSLATION_AUTO) {
|
367 |
bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, §ors); |
368 |
if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { |
369 |
/* No translation. */
|
370 |
translation = 0;
|
371 |
} else {
|
372 |
/* LBA translation. */
|
373 |
translation = 1;
|
374 |
} |
375 |
} else {
|
376 |
translation--; |
377 |
} |
378 |
val |= translation << (i * 2);
|
379 |
} |
380 |
} |
381 |
rtc_set_memory(s, 0x39, val);
|
382 |
} |
383 |
|
384 |
void ioport_set_a20(int enable) |
385 |
{ |
386 |
/* XXX: send to all CPUs ? */
|
387 |
cpu_x86_set_a20(first_cpu, enable); |
388 |
} |
389 |
|
390 |
int ioport_get_a20(void) |
391 |
{ |
392 |
return ((first_cpu->a20_mask >> 20) & 1); |
393 |
} |
394 |
|
395 |
static void ioport92_write(void *opaque, uint32_t addr, uint32_t val) |
396 |
{ |
397 |
ioport_set_a20((val >> 1) & 1); |
398 |
/* XXX: bit 0 is fast reset */
|
399 |
} |
400 |
|
401 |
static uint32_t ioport92_read(void *opaque, uint32_t addr) |
402 |
{ |
403 |
return ioport_get_a20() << 1; |
404 |
} |
405 |
|
406 |
/***********************************************************/
|
407 |
/* Bochs BIOS debug ports */
|
408 |
|
409 |
static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) |
410 |
{ |
411 |
static const char shutdown_str[8] = "Shutdown"; |
412 |
static int shutdown_index = 0; |
413 |
|
414 |
switch(addr) {
|
415 |
/* Bochs BIOS messages */
|
416 |
case 0x400: |
417 |
case 0x401: |
418 |
fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
|
419 |
exit(1);
|
420 |
case 0x402: |
421 |
case 0x403: |
422 |
#ifdef DEBUG_BIOS
|
423 |
fprintf(stderr, "%c", val);
|
424 |
#endif
|
425 |
break;
|
426 |
case 0x8900: |
427 |
/* same as Bochs power off */
|
428 |
if (val == shutdown_str[shutdown_index]) {
|
429 |
shutdown_index++; |
430 |
if (shutdown_index == 8) { |
431 |
shutdown_index = 0;
|
432 |
qemu_system_shutdown_request(); |
433 |
} |
434 |
} else {
|
435 |
shutdown_index = 0;
|
436 |
} |
437 |
break;
|
438 |
|
439 |
/* LGPL'ed VGA BIOS messages */
|
440 |
case 0x501: |
441 |
case 0x502: |
442 |
fprintf(stderr, "VGA BIOS panic, line %d\n", val);
|
443 |
exit(1);
|
444 |
case 0x500: |
445 |
case 0x503: |
446 |
#ifdef DEBUG_BIOS
|
447 |
fprintf(stderr, "%c", val);
|
448 |
#endif
|
449 |
break;
|
450 |
} |
451 |
} |
452 |
|
453 |
int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
|
454 |
{ |
455 |
int index = e820_table.count;
|
456 |
struct e820_entry *entry;
|
457 |
|
458 |
if (index >= E820_NR_ENTRIES)
|
459 |
return -EBUSY;
|
460 |
entry = &e820_table.entry[index]; |
461 |
|
462 |
entry->address = address; |
463 |
entry->length = length; |
464 |
entry->type = type; |
465 |
|
466 |
e820_table.count++; |
467 |
return e820_table.count;
|
468 |
} |
469 |
|
470 |
static void *bochs_bios_init(void) |
471 |
{ |
472 |
void *fw_cfg;
|
473 |
uint8_t *smbios_table; |
474 |
size_t smbios_len; |
475 |
uint64_t *numa_fw_cfg; |
476 |
int i, j;
|
477 |
|
478 |
register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); |
479 |
register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); |
480 |
register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); |
481 |
register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); |
482 |
register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); |
483 |
|
484 |
register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); |
485 |
register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); |
486 |
register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); |
487 |
register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); |
488 |
|
489 |
fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
490 |
|
491 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
492 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
493 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, |
494 |
acpi_tables_len); |
495 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
|
496 |
|
497 |
smbios_table = smbios_get_table(&smbios_len); |
498 |
if (smbios_table)
|
499 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, |
500 |
smbios_table, smbios_len); |
501 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table, |
502 |
sizeof(struct e820_table)); |
503 |
|
504 |
/* allocate memory for the NUMA channel: one (64bit) word for the number
|
505 |
* of nodes, one word for each VCPU->node and one word for each node to
|
506 |
* hold the amount of memory.
|
507 |
*/
|
508 |
numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8); |
509 |
numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
|
510 |
for (i = 0; i < smp_cpus; i++) { |
511 |
for (j = 0; j < nb_numa_nodes; j++) { |
512 |
if (node_cpumask[j] & (1 << i)) { |
513 |
numa_fw_cfg[i + 1] = cpu_to_le64(j);
|
514 |
break;
|
515 |
} |
516 |
} |
517 |
} |
518 |
for (i = 0; i < nb_numa_nodes; i++) { |
519 |
numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
|
520 |
} |
521 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, |
522 |
(1 + smp_cpus + nb_numa_nodes) * 8); |
523 |
|
524 |
return fw_cfg;
|
525 |
} |
526 |
|
527 |
static long get_file_size(FILE *f) |
528 |
{ |
529 |
long where, size;
|
530 |
|
531 |
/* XXX: on Unix systems, using fstat() probably makes more sense */
|
532 |
|
533 |
where = ftell(f); |
534 |
fseek(f, 0, SEEK_END);
|
535 |
size = ftell(f); |
536 |
fseek(f, where, SEEK_SET); |
537 |
|
538 |
return size;
|
539 |
} |
540 |
|
541 |
static void load_linux(void *fw_cfg, |
542 |
const char *kernel_filename, |
543 |
const char *initrd_filename, |
544 |
const char *kernel_cmdline, |
545 |
target_phys_addr_t max_ram_size) |
546 |
{ |
547 |
uint16_t protocol; |
548 |
int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
549 |
uint32_t initrd_max; |
550 |
uint8_t header[8192], *setup, *kernel, *initrd_data;
|
551 |
target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
|
552 |
FILE *f; |
553 |
char *vmode;
|
554 |
|
555 |
/* Align to 16 bytes as a paranoia measure */
|
556 |
cmdline_size = (strlen(kernel_cmdline)+16) & ~15; |
557 |
|
558 |
/* load the kernel header */
|
559 |
f = fopen(kernel_filename, "rb");
|
560 |
if (!f || !(kernel_size = get_file_size(f)) ||
|
561 |
fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
|
562 |
MIN(ARRAY_SIZE(header), kernel_size)) { |
563 |
fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
|
564 |
kernel_filename, strerror(errno)); |
565 |
exit(1);
|
566 |
} |
567 |
|
568 |
/* kernel protocol version */
|
569 |
#if 0
|
570 |
fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
|
571 |
#endif
|
572 |
if (ldl_p(header+0x202) == 0x53726448) |
573 |
protocol = lduw_p(header+0x206);
|
574 |
else {
|
575 |
/* This looks like a multiboot kernel. If it is, let's stop
|
576 |
treating it like a Linux kernel. */
|
577 |
if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
|
578 |
kernel_cmdline, kernel_size, header)) |
579 |
return;
|
580 |
protocol = 0;
|
581 |
} |
582 |
|
583 |
if (protocol < 0x200 || !(header[0x211] & 0x01)) { |
584 |
/* Low kernel */
|
585 |
real_addr = 0x90000;
|
586 |
cmdline_addr = 0x9a000 - cmdline_size;
|
587 |
prot_addr = 0x10000;
|
588 |
} else if (protocol < 0x202) { |
589 |
/* High but ancient kernel */
|
590 |
real_addr = 0x90000;
|
591 |
cmdline_addr = 0x9a000 - cmdline_size;
|
592 |
prot_addr = 0x100000;
|
593 |
} else {
|
594 |
/* High and recent kernel */
|
595 |
real_addr = 0x10000;
|
596 |
cmdline_addr = 0x20000;
|
597 |
prot_addr = 0x100000;
|
598 |
} |
599 |
|
600 |
#if 0
|
601 |
fprintf(stderr,
|
602 |
"qemu: real_addr = 0x" TARGET_FMT_plx "\n"
|
603 |
"qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
|
604 |
"qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
|
605 |
real_addr,
|
606 |
cmdline_addr,
|
607 |
prot_addr);
|
608 |
#endif
|
609 |
|
610 |
/* highest address for loading the initrd */
|
611 |
if (protocol >= 0x203) |
612 |
initrd_max = ldl_p(header+0x22c);
|
613 |
else
|
614 |
initrd_max = 0x37ffffff;
|
615 |
|
616 |
if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
|
617 |
initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
|
618 |
|
619 |
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); |
620 |
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
|
621 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
622 |
(uint8_t*)strdup(kernel_cmdline), |
623 |
strlen(kernel_cmdline)+1);
|
624 |
|
625 |
if (protocol >= 0x202) { |
626 |
stl_p(header+0x228, cmdline_addr);
|
627 |
} else {
|
628 |
stw_p(header+0x20, 0xA33F); |
629 |
stw_p(header+0x22, cmdline_addr-real_addr);
|
630 |
} |
631 |
|
632 |
/* handle vga= parameter */
|
633 |
vmode = strstr(kernel_cmdline, "vga=");
|
634 |
if (vmode) {
|
635 |
unsigned int video_mode; |
636 |
/* skip "vga=" */
|
637 |
vmode += 4;
|
638 |
if (!strncmp(vmode, "normal", 6)) { |
639 |
video_mode = 0xffff;
|
640 |
} else if (!strncmp(vmode, "ext", 3)) { |
641 |
video_mode = 0xfffe;
|
642 |
} else if (!strncmp(vmode, "ask", 3)) { |
643 |
video_mode = 0xfffd;
|
644 |
} else {
|
645 |
video_mode = strtol(vmode, NULL, 0); |
646 |
} |
647 |
stw_p(header+0x1fa, video_mode);
|
648 |
} |
649 |
|
650 |
/* loader type */
|
651 |
/* High nybble = B reserved for Qemu; low nybble is revision number.
|
652 |
If this code is substantially changed, you may want to consider
|
653 |
incrementing the revision. */
|
654 |
if (protocol >= 0x200) |
655 |
header[0x210] = 0xB0; |
656 |
|
657 |
/* heap */
|
658 |
if (protocol >= 0x201) { |
659 |
header[0x211] |= 0x80; /* CAN_USE_HEAP */ |
660 |
stw_p(header+0x224, cmdline_addr-real_addr-0x200); |
661 |
} |
662 |
|
663 |
/* load initrd */
|
664 |
if (initrd_filename) {
|
665 |
if (protocol < 0x200) { |
666 |
fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
|
667 |
exit(1);
|
668 |
} |
669 |
|
670 |
initrd_size = get_image_size(initrd_filename); |
671 |
initrd_addr = (initrd_max-initrd_size) & ~4095;
|
672 |
|
673 |
initrd_data = qemu_malloc(initrd_size); |
674 |
load_image(initrd_filename, initrd_data); |
675 |
|
676 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); |
677 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
678 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); |
679 |
|
680 |
stl_p(header+0x218, initrd_addr);
|
681 |
stl_p(header+0x21c, initrd_size);
|
682 |
} |
683 |
|
684 |
/* load kernel and setup */
|
685 |
setup_size = header[0x1f1];
|
686 |
if (setup_size == 0) |
687 |
setup_size = 4;
|
688 |
setup_size = (setup_size+1)*512; |
689 |
kernel_size -= setup_size; |
690 |
|
691 |
setup = qemu_malloc(setup_size); |
692 |
kernel = qemu_malloc(kernel_size); |
693 |
fseek(f, 0, SEEK_SET);
|
694 |
if (fread(setup, 1, setup_size, f) != setup_size) { |
695 |
fprintf(stderr, "fread() failed\n");
|
696 |
exit(1);
|
697 |
} |
698 |
if (fread(kernel, 1, kernel_size, f) != kernel_size) { |
699 |
fprintf(stderr, "fread() failed\n");
|
700 |
exit(1);
|
701 |
} |
702 |
fclose(f); |
703 |
memcpy(setup, header, MIN(sizeof(header), setup_size));
|
704 |
|
705 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); |
706 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
707 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); |
708 |
|
709 |
fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); |
710 |
fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); |
711 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); |
712 |
|
713 |
option_rom[nb_option_roms] = "linuxboot.bin";
|
714 |
nb_option_roms++; |
715 |
} |
716 |
|
717 |
static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
718 |
static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
719 |
static const int ide_irq[2] = { 14, 15 }; |
720 |
|
721 |
#define NE2000_NB_MAX 6 |
722 |
|
723 |
static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
724 |
0x280, 0x380 }; |
725 |
static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
726 |
|
727 |
static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
728 |
static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; |
729 |
|
730 |
#ifdef HAS_AUDIO
|
731 |
static void audio_init (PCIBus *pci_bus, qemu_irq *pic) |
732 |
{ |
733 |
struct soundhw *c;
|
734 |
|
735 |
for (c = soundhw; c->name; ++c) {
|
736 |
if (c->enabled) {
|
737 |
if (c->isa) {
|
738 |
c->init.init_isa(pic); |
739 |
} else {
|
740 |
if (pci_bus) {
|
741 |
c->init.init_pci(pci_bus); |
742 |
} |
743 |
} |
744 |
} |
745 |
} |
746 |
} |
747 |
#endif
|
748 |
|
749 |
static void pc_init_ne2k_isa(NICInfo *nd) |
750 |
{ |
751 |
static int nb_ne2k = 0; |
752 |
|
753 |
if (nb_ne2k == NE2000_NB_MAX)
|
754 |
return;
|
755 |
isa_ne2000_init(ne2000_io[nb_ne2k], |
756 |
ne2000_irq[nb_ne2k], nd); |
757 |
nb_ne2k++; |
758 |
} |
759 |
|
760 |
int cpu_is_bsp(CPUState *env)
|
761 |
{ |
762 |
/* We hard-wire the BSP to the first CPU. */
|
763 |
return env->cpu_index == 0; |
764 |
} |
765 |
|
766 |
static CPUState *pc_new_cpu(const char *cpu_model) |
767 |
{ |
768 |
CPUState *env; |
769 |
|
770 |
env = cpu_init(cpu_model); |
771 |
if (!env) {
|
772 |
fprintf(stderr, "Unable to find x86 CPU definition\n");
|
773 |
exit(1);
|
774 |
} |
775 |
if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) { |
776 |
env->cpuid_apic_id = env->cpu_index; |
777 |
/* APIC reset callback resets cpu */
|
778 |
apic_init(env); |
779 |
} else {
|
780 |
qemu_register_reset((QEMUResetHandler*)cpu_reset, env); |
781 |
} |
782 |
return env;
|
783 |
} |
784 |
|
785 |
/* PC hardware initialisation */
|
786 |
static void pc_init1(ram_addr_t ram_size, |
787 |
const char *boot_device, |
788 |
const char *kernel_filename, |
789 |
const char *kernel_cmdline, |
790 |
const char *initrd_filename, |
791 |
const char *cpu_model, |
792 |
int pci_enabled)
|
793 |
{ |
794 |
char *filename;
|
795 |
int ret, linux_boot, i;
|
796 |
ram_addr_t ram_addr, bios_offset, option_rom_offset; |
797 |
ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
|
798 |
int bios_size, isa_bios_size;
|
799 |
PCIBus *pci_bus; |
800 |
ISADevice *isa_dev; |
801 |
int piix3_devfn = -1; |
802 |
CPUState *env; |
803 |
qemu_irq *cpu_irq; |
804 |
qemu_irq *isa_irq; |
805 |
qemu_irq *i8259; |
806 |
IsaIrqState *isa_irq_state; |
807 |
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
808 |
DriveInfo *fd[MAX_FD]; |
809 |
void *fw_cfg;
|
810 |
|
811 |
if (ram_size >= 0xe0000000 ) { |
812 |
above_4g_mem_size = ram_size - 0xe0000000;
|
813 |
below_4g_mem_size = 0xe0000000;
|
814 |
} else {
|
815 |
below_4g_mem_size = ram_size; |
816 |
} |
817 |
|
818 |
linux_boot = (kernel_filename != NULL);
|
819 |
|
820 |
/* init CPUs */
|
821 |
if (cpu_model == NULL) { |
822 |
#ifdef TARGET_X86_64
|
823 |
cpu_model = "qemu64";
|
824 |
#else
|
825 |
cpu_model = "qemu32";
|
826 |
#endif
|
827 |
} |
828 |
|
829 |
for (i = 0; i < smp_cpus; i++) { |
830 |
env = pc_new_cpu(cpu_model); |
831 |
} |
832 |
|
833 |
vmport_init(); |
834 |
|
835 |
/* allocate RAM */
|
836 |
ram_addr = qemu_ram_alloc(below_4g_mem_size); |
837 |
cpu_register_physical_memory(0, 0xa0000, ram_addr); |
838 |
cpu_register_physical_memory(0x100000,
|
839 |
below_4g_mem_size - 0x100000,
|
840 |
ram_addr + 0x100000);
|
841 |
|
842 |
/* above 4giga memory allocation */
|
843 |
if (above_4g_mem_size > 0) { |
844 |
#if TARGET_PHYS_ADDR_BITS == 32 |
845 |
hw_error("To much RAM for 32-bit physical address");
|
846 |
#else
|
847 |
ram_addr = qemu_ram_alloc(above_4g_mem_size); |
848 |
cpu_register_physical_memory(0x100000000ULL,
|
849 |
above_4g_mem_size, |
850 |
ram_addr); |
851 |
#endif
|
852 |
} |
853 |
|
854 |
|
855 |
/* BIOS load */
|
856 |
if (bios_name == NULL) |
857 |
bios_name = BIOS_FILENAME; |
858 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
859 |
if (filename) {
|
860 |
bios_size = get_image_size(filename); |
861 |
} else {
|
862 |
bios_size = -1;
|
863 |
} |
864 |
if (bios_size <= 0 || |
865 |
(bios_size % 65536) != 0) { |
866 |
goto bios_error;
|
867 |
} |
868 |
bios_offset = qemu_ram_alloc(bios_size); |
869 |
ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size)); |
870 |
if (ret != 0) { |
871 |
bios_error:
|
872 |
fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
|
873 |
exit(1);
|
874 |
} |
875 |
if (filename) {
|
876 |
qemu_free(filename); |
877 |
} |
878 |
/* map the last 128KB of the BIOS in ISA space */
|
879 |
isa_bios_size = bios_size; |
880 |
if (isa_bios_size > (128 * 1024)) |
881 |
isa_bios_size = 128 * 1024; |
882 |
cpu_register_physical_memory(0x100000 - isa_bios_size,
|
883 |
isa_bios_size, |
884 |
(bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); |
885 |
|
886 |
option_rom_offset = qemu_ram_alloc(PC_ROM_SIZE); |
887 |
cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset); |
888 |
|
889 |
/* map all the bios at the top of memory */
|
890 |
cpu_register_physical_memory((uint32_t)(-bios_size), |
891 |
bios_size, bios_offset | IO_MEM_ROM); |
892 |
|
893 |
fw_cfg = bochs_bios_init(); |
894 |
rom_set_fw(fw_cfg); |
895 |
|
896 |
if (linux_boot) {
|
897 |
load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); |
898 |
} |
899 |
|
900 |
for (i = 0; i < nb_option_roms; i++) { |
901 |
rom_add_option(option_rom[i]); |
902 |
} |
903 |
|
904 |
cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1); |
905 |
i8259 = i8259_init(cpu_irq[0]);
|
906 |
isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
|
907 |
isa_irq_state->i8259 = i8259; |
908 |
isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
|
909 |
|
910 |
if (pci_enabled) {
|
911 |
pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq); |
912 |
} else {
|
913 |
pci_bus = NULL;
|
914 |
isa_bus_new(NULL);
|
915 |
} |
916 |
isa_bus_irqs(isa_irq); |
917 |
|
918 |
ferr_irq = isa_reserve_irq(13);
|
919 |
|
920 |
/* init basic PC hardware */
|
921 |
register_ioport_write(0x80, 1, 1, ioport80_write, NULL); |
922 |
|
923 |
register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); |
924 |
|
925 |
if (cirrus_vga_enabled) {
|
926 |
if (pci_enabled) {
|
927 |
pci_cirrus_vga_init(pci_bus); |
928 |
} else {
|
929 |
isa_cirrus_vga_init(); |
930 |
} |
931 |
} else if (vmsvga_enabled) { |
932 |
if (pci_enabled)
|
933 |
pci_vmsvga_init(pci_bus); |
934 |
else
|
935 |
fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
|
936 |
} else if (std_vga_enabled) { |
937 |
if (pci_enabled) {
|
938 |
pci_vga_init(pci_bus, 0, 0); |
939 |
} else {
|
940 |
isa_vga_init(); |
941 |
} |
942 |
} |
943 |
|
944 |
rtc_state = rtc_init(2000);
|
945 |
|
946 |
qemu_register_boot_set(pc_boot_set, rtc_state); |
947 |
|
948 |
register_ioport_read(0x92, 1, 1, ioport92_read, NULL); |
949 |
register_ioport_write(0x92, 1, 1, ioport92_write, NULL); |
950 |
|
951 |
if (pci_enabled) {
|
952 |
isa_irq_state->ioapic = ioapic_init(); |
953 |
} |
954 |
pit = pit_init(0x40, isa_reserve_irq(0)); |
955 |
pcspk_init(pit); |
956 |
if (!no_hpet) {
|
957 |
hpet_init(isa_irq); |
958 |
} |
959 |
|
960 |
for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
961 |
if (serial_hds[i]) {
|
962 |
serial_isa_init(i, serial_hds[i]); |
963 |
} |
964 |
} |
965 |
|
966 |
for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
967 |
if (parallel_hds[i]) {
|
968 |
parallel_init(i, parallel_hds[i]); |
969 |
} |
970 |
} |
971 |
|
972 |
for(i = 0; i < nb_nics; i++) { |
973 |
NICInfo *nd = &nd_table[i]; |
974 |
|
975 |
if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) |
976 |
pc_init_ne2k_isa(nd); |
977 |
else
|
978 |
pci_nic_init_nofail(nd, "e1000", NULL); |
979 |
} |
980 |
|
981 |
if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
982 |
fprintf(stderr, "qemu: too many IDE bus\n");
|
983 |
exit(1);
|
984 |
} |
985 |
|
986 |
for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
987 |
hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
988 |
} |
989 |
|
990 |
if (pci_enabled) {
|
991 |
pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1);
|
992 |
} else {
|
993 |
for(i = 0; i < MAX_IDE_BUS; i++) { |
994 |
isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], |
995 |
hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
|
996 |
} |
997 |
} |
998 |
|
999 |
isa_dev = isa_create_simple("i8042");
|
1000 |
DMA_init(0);
|
1001 |
#ifdef HAS_AUDIO
|
1002 |
audio_init(pci_enabled ? pci_bus : NULL, isa_irq);
|
1003 |
#endif
|
1004 |
|
1005 |
for(i = 0; i < MAX_FD; i++) { |
1006 |
fd[i] = drive_get(IF_FLOPPY, 0, i);
|
1007 |
} |
1008 |
floppy_controller = fdctrl_init_isa(fd); |
1009 |
|
1010 |
cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd); |
1011 |
|
1012 |
if (pci_enabled && usb_enabled) {
|
1013 |
usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
|
1014 |
} |
1015 |
|
1016 |
if (pci_enabled && acpi_enabled) {
|
1017 |
uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */ |
1018 |
i2c_bus *smbus; |
1019 |
|
1020 |
/* TODO: Populate SPD eeprom data. */
|
1021 |
smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, |
1022 |
isa_reserve_irq(9));
|
1023 |
for (i = 0; i < 8; i++) { |
1024 |
DeviceState *eeprom; |
1025 |
eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
|
1026 |
qdev_prop_set_uint8(eeprom, "address", 0x50 + i); |
1027 |
qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256)); |
1028 |
qdev_init_nofail(eeprom); |
1029 |
} |
1030 |
piix4_acpi_system_hot_add_init(pci_bus); |
1031 |
} |
1032 |
|
1033 |
if (i440fx_state) {
|
1034 |
i440fx_init_memory_mappings(i440fx_state); |
1035 |
} |
1036 |
|
1037 |
if (pci_enabled) {
|
1038 |
int max_bus;
|
1039 |
int bus;
|
1040 |
|
1041 |
max_bus = drive_get_max_bus(IF_SCSI); |
1042 |
for (bus = 0; bus <= max_bus; bus++) { |
1043 |
pci_create_simple(pci_bus, -1, "lsi53c895a"); |
1044 |
} |
1045 |
} |
1046 |
} |
1047 |
|
1048 |
static void pc_init_pci(ram_addr_t ram_size, |
1049 |
const char *boot_device, |
1050 |
const char *kernel_filename, |
1051 |
const char *kernel_cmdline, |
1052 |
const char *initrd_filename, |
1053 |
const char *cpu_model) |
1054 |
{ |
1055 |
pc_init1(ram_size, boot_device, |
1056 |
kernel_filename, kernel_cmdline, |
1057 |
initrd_filename, cpu_model, 1);
|
1058 |
} |
1059 |
|
1060 |
static void pc_init_isa(ram_addr_t ram_size, |
1061 |
const char *boot_device, |
1062 |
const char *kernel_filename, |
1063 |
const char *kernel_cmdline, |
1064 |
const char *initrd_filename, |
1065 |
const char *cpu_model) |
1066 |
{ |
1067 |
if (cpu_model == NULL) |
1068 |
cpu_model = "486";
|
1069 |
pc_init1(ram_size, boot_device, |
1070 |
kernel_filename, kernel_cmdline, |
1071 |
initrd_filename, cpu_model, 0);
|
1072 |
} |
1073 |
|
1074 |
/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
|
1075 |
BIOS will read it and start S3 resume at POST Entry */
|
1076 |
void cmos_set_s3_resume(void) |
1077 |
{ |
1078 |
if (rtc_state)
|
1079 |
rtc_set_memory(rtc_state, 0xF, 0xFE); |
1080 |
} |
1081 |
|
1082 |
static QEMUMachine pc_machine = {
|
1083 |
.name = "pc-0.13",
|
1084 |
.alias = "pc",
|
1085 |
.desc = "Standard PC",
|
1086 |
.init = pc_init_pci, |
1087 |
.max_cpus = 255,
|
1088 |
.is_default = 1,
|
1089 |
}; |
1090 |
|
1091 |
static QEMUMachine pc_machine_v0_12 = {
|
1092 |
.name = "pc-0.12",
|
1093 |
.desc = "Standard PC",
|
1094 |
.init = pc_init_pci, |
1095 |
.max_cpus = 255,
|
1096 |
.compat_props = (GlobalProperty[]) { |
1097 |
{ |
1098 |
.driver = "virtio-serial-pci",
|
1099 |
.property = "max_nr_ports",
|
1100 |
.value = stringify(1),
|
1101 |
},{ |
1102 |
.driver = "virtio-serial-pci",
|
1103 |
.property = "vectors",
|
1104 |
.value = stringify(0),
|
1105 |
}, |
1106 |
{ /* end of list */ }
|
1107 |
} |
1108 |
}; |
1109 |
|
1110 |
static QEMUMachine pc_machine_v0_11 = {
|
1111 |
.name = "pc-0.11",
|
1112 |
.desc = "Standard PC, qemu 0.11",
|
1113 |
.init = pc_init_pci, |
1114 |
.max_cpus = 255,
|
1115 |
.compat_props = (GlobalProperty[]) { |
1116 |
{ |
1117 |
.driver = "virtio-blk-pci",
|
1118 |
.property = "vectors",
|
1119 |
.value = stringify(0),
|
1120 |
},{ |
1121 |
.driver = "virtio-serial-pci",
|
1122 |
.property = "max_nr_ports",
|
1123 |
.value = stringify(1),
|
1124 |
},{ |
1125 |
.driver = "virtio-serial-pci",
|
1126 |
.property = "vectors",
|
1127 |
.value = stringify(0),
|
1128 |
},{ |
1129 |
.driver = "ide-drive",
|
1130 |
.property = "ver",
|
1131 |
.value = "0.11",
|
1132 |
},{ |
1133 |
.driver = "scsi-disk",
|
1134 |
.property = "ver",
|
1135 |
.value = "0.11",
|
1136 |
},{ |
1137 |
.driver = "PCI",
|
1138 |
.property = "rombar",
|
1139 |
.value = stringify(0),
|
1140 |
}, |
1141 |
{ /* end of list */ }
|
1142 |
} |
1143 |
}; |
1144 |
|
1145 |
static QEMUMachine pc_machine_v0_10 = {
|
1146 |
.name = "pc-0.10",
|
1147 |
.desc = "Standard PC, qemu 0.10",
|
1148 |
.init = pc_init_pci, |
1149 |
.max_cpus = 255,
|
1150 |
.compat_props = (GlobalProperty[]) { |
1151 |
{ |
1152 |
.driver = "virtio-blk-pci",
|
1153 |
.property = "class",
|
1154 |
.value = stringify(PCI_CLASS_STORAGE_OTHER), |
1155 |
},{ |
1156 |
.driver = "virtio-serial-pci",
|
1157 |
.property = "class",
|
1158 |
.value = stringify(PCI_CLASS_DISPLAY_OTHER), |
1159 |
},{ |
1160 |
.driver = "virtio-serial-pci",
|
1161 |
.property = "max_nr_ports",
|
1162 |
.value = stringify(1),
|
1163 |
},{ |
1164 |
.driver = "virtio-serial-pci",
|
1165 |
.property = "vectors",
|
1166 |
.value = stringify(0),
|
1167 |
},{ |
1168 |
.driver = "virtio-net-pci",
|
1169 |
.property = "vectors",
|
1170 |
.value = stringify(0),
|
1171 |
},{ |
1172 |
.driver = "virtio-blk-pci",
|
1173 |
.property = "vectors",
|
1174 |
.value = stringify(0),
|
1175 |
},{ |
1176 |
.driver = "ide-drive",
|
1177 |
.property = "ver",
|
1178 |
.value = "0.10",
|
1179 |
},{ |
1180 |
.driver = "scsi-disk",
|
1181 |
.property = "ver",
|
1182 |
.value = "0.10",
|
1183 |
},{ |
1184 |
.driver = "PCI",
|
1185 |
.property = "rombar",
|
1186 |
.value = stringify(0),
|
1187 |
}, |
1188 |
{ /* end of list */ }
|
1189 |
}, |
1190 |
}; |
1191 |
|
1192 |
static QEMUMachine isapc_machine = {
|
1193 |
.name = "isapc",
|
1194 |
.desc = "ISA-only PC",
|
1195 |
.init = pc_init_isa, |
1196 |
.max_cpus = 1,
|
1197 |
}; |
1198 |
|
1199 |
static void pc_machine_init(void) |
1200 |
{ |
1201 |
qemu_register_machine(&pc_machine); |
1202 |
qemu_register_machine(&pc_machine_v0_12); |
1203 |
qemu_register_machine(&pc_machine_v0_11); |
1204 |
qemu_register_machine(&pc_machine_v0_10); |
1205 |
qemu_register_machine(&isapc_machine); |
1206 |
} |
1207 |
|
1208 |
machine_init(pc_machine_init); |