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/*
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 * TI OMAP L4 interconnect emulation.
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 *
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 * Copyright (C) 2007-2009 Nokia Corporation
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 * Written by Andrzej Zaborowski <andrew@openedhand.com>
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 or
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 * (at your option) any later version of the License.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License along
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 * with this program; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include "hw.h"
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#include "omap.h"
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#ifdef L4_MUX_HACK
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static int omap_l4_io_entries;
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static int omap_cpu_io_entry;
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static struct omap_l4_entry {
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        CPUReadMemoryFunc * const *mem_read;
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        CPUWriteMemoryFunc * const *mem_write;
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        void *opaque;
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} *omap_l4_io_entry;
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static CPUReadMemoryFunc * const *omap_l4_io_readb_fn;
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static CPUReadMemoryFunc * const *omap_l4_io_readh_fn;
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static CPUReadMemoryFunc * const *omap_l4_io_readw_fn;
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static CPUWriteMemoryFunc * const *omap_l4_io_writeb_fn;
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static CPUWriteMemoryFunc * const *omap_l4_io_writeh_fn;
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static CPUWriteMemoryFunc * const *omap_l4_io_writew_fn;
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static void **omap_l4_io_opaque;
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int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
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                CPUWriteMemoryFunc * const *mem_write, void *opaque)
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{
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    omap_l4_io_entry[omap_l4_io_entries].mem_read = mem_read;
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    omap_l4_io_entry[omap_l4_io_entries].mem_write = mem_write;
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    omap_l4_io_entry[omap_l4_io_entries].opaque = opaque;
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    return omap_l4_io_entries ++;
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}
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static uint32_t omap_l4_io_readb(void *opaque, target_phys_addr_t addr)
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{
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    unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
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    return omap_l4_io_readb_fn[i](omap_l4_io_opaque[i], addr);
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}
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static uint32_t omap_l4_io_readh(void *opaque, target_phys_addr_t addr)
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{
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    unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
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    return omap_l4_io_readh_fn[i](omap_l4_io_opaque[i], addr);
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}
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static uint32_t omap_l4_io_readw(void *opaque, target_phys_addr_t addr)
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{
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    unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
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    return omap_l4_io_readw_fn[i](omap_l4_io_opaque[i], addr);
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}
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static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr,
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                uint32_t value)
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{
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    unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
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    return omap_l4_io_writeb_fn[i](omap_l4_io_opaque[i], addr, value);
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}
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static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr,
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                uint32_t value)
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{
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    unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
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    return omap_l4_io_writeh_fn[i](omap_l4_io_opaque[i], addr, value);
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}
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static void omap_l4_io_writew(void *opaque, target_phys_addr_t addr,
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                uint32_t value)
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{
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    unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
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    return omap_l4_io_writew_fn[i](omap_l4_io_opaque[i], addr, value);
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}
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static CPUReadMemoryFunc * const omap_l4_io_readfn[] = {
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    omap_l4_io_readb,
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    omap_l4_io_readh,
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    omap_l4_io_readw,
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};
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static CPUWriteMemoryFunc * const omap_l4_io_writefn[] = {
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    omap_l4_io_writeb,
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    omap_l4_io_writeh,
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    omap_l4_io_writew,
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};
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#else
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int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
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                          CPUWriteMemoryFunc * const *mem_write,
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                          void *opaque)
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{
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    return cpu_register_io_memory(mem_read, mem_write, opaque);
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}
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#endif
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struct omap_l4_s {
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    target_phys_addr_t base;
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    int ta_num;
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    struct omap_target_agent_s ta[0];
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};
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struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num)
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{
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    struct omap_l4_s *bus = qemu_mallocz(
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                    sizeof(*bus) + ta_num * sizeof(*bus->ta));
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    bus->ta_num = ta_num;
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    bus->base = base;
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#ifdef L4_MUX_HACK
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    omap_l4_io_entries = 1;
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    omap_l4_io_entry = qemu_mallocz(125 * sizeof(*omap_l4_io_entry));
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    omap_cpu_io_entry =
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            cpu_register_io_memory(omap_l4_io_readfn,
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                            omap_l4_io_writefn, bus);
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# define L4_PAGES        (0xb4000 / TARGET_PAGE_SIZE)
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    omap_l4_io_readb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
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    omap_l4_io_readh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
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    omap_l4_io_readw_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
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    omap_l4_io_writeb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
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    omap_l4_io_writeh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
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    omap_l4_io_writew_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
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    omap_l4_io_opaque = qemu_mallocz(sizeof(void *) * L4_PAGES);
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#endif
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    return bus;
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}
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static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr)
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{
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    struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
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    switch (addr) {
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    case 0x00:        /* COMPONENT */
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        return s->component;
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    case 0x20:        /* AGENT_CONTROL */
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        return s->control;
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    case 0x28:        /* AGENT_STATUS */
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        return s->status;
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    }
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    OMAP_BAD_REG(addr);
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    return 0;
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}
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static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
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                uint32_t value)
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{
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    struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
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    switch (addr) {
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    case 0x00:        /* COMPONENT */
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    case 0x28:        /* AGENT_STATUS */
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        OMAP_RO_REG(addr);
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        break;
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    case 0x20:        /* AGENT_CONTROL */
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        s->control = value & 0x01000700;
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        if (value & 1)                                        /* OCP_RESET */
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            s->status &= ~1;                                /* REQ_TIMEOUT */
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        break;
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    default:
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        OMAP_BAD_REG(addr);
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    }
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}
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static CPUReadMemoryFunc * const omap_l4ta_readfn[] = {
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    omap_badwidth_read16,
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    omap_l4ta_read,
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    omap_badwidth_read16,
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};
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static CPUWriteMemoryFunc * const omap_l4ta_writefn[] = {
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    omap_badwidth_write32,
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    omap_badwidth_write32,
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    omap_l4ta_write,
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};
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struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus,
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        const struct omap_l4_region_s *regions,
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        const struct omap_l4_agent_info_s *agents,
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        int cs)
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{
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    int i, iomemtype;
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    struct omap_target_agent_s *ta = NULL;
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    const struct omap_l4_agent_info_s *info = NULL;
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    for (i = 0; i < bus->ta_num; i ++)
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        if (agents[i].ta == cs) {
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            ta = &bus->ta[i];
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            info = &agents[i];
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            break;
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        }
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    if (!ta) {
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        fprintf(stderr, "%s: bad target agent (%i)\n", __FUNCTION__, cs);
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        exit(-1);
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    }
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    ta->bus = bus;
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    ta->start = &regions[info->region];
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    ta->regions = info->regions;
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    ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
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    ta->status = 0x00000000;
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    ta->control = 0x00000200;        /* XXX 01000200 for L4TAO */
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    iomemtype = l4_register_io_memory(omap_l4ta_readfn,
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                    omap_l4ta_writefn, ta);
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    ta->base = omap_l4_attach(ta, info->ta_region, iomemtype);
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    return ta;
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}
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target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
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                int iotype)
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{
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    target_phys_addr_t base;
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    ssize_t size;
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#ifdef L4_MUX_HACK
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    int i;
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#endif
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    if (region < 0 || region >= ta->regions) {
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        fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region);
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        exit(-1);
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    }
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    base = ta->bus->base + ta->start[region].offset;
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    size = ta->start[region].size;
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    if (iotype) {
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#ifndef L4_MUX_HACK
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        cpu_register_physical_memory(base, size, iotype);
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#else
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        cpu_register_physical_memory(base, size, omap_cpu_io_entry);
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        i = (base - ta->bus->base) / TARGET_PAGE_SIZE;
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        for (; size > 0; size -= TARGET_PAGE_SIZE, i ++) {
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            omap_l4_io_readb_fn[i] = omap_l4_io_entry[iotype].mem_read[0];
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            omap_l4_io_readh_fn[i] = omap_l4_io_entry[iotype].mem_read[1];
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            omap_l4_io_readw_fn[i] = omap_l4_io_entry[iotype].mem_read[2];
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            omap_l4_io_writeb_fn[i] = omap_l4_io_entry[iotype].mem_write[0];
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            omap_l4_io_writeh_fn[i] = omap_l4_io_entry[iotype].mem_write[1];
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            omap_l4_io_writew_fn[i] = omap_l4_io_entry[iotype].mem_write[2];
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            omap_l4_io_opaque[i] = omap_l4_io_entry[iotype].opaque;
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        }
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#endif
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    }
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    return base;
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}