root / hw / openpic.h @ 8af7a3ab
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| 1 | b7169916 | aurel32 | #if !defined(__OPENPIC_H__)
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| 2 | b7169916 | aurel32 | #define __OPENPIC_H__
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| 3 | b7169916 | aurel32 | |
| 4 | b7169916 | aurel32 | /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
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| 5 | b7169916 | aurel32 | enum {
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| 6 | b7169916 | aurel32 | OPENPIC_OUTPUT_INT = 0, /* IRQ */ |
| 7 | b7169916 | aurel32 | OPENPIC_OUTPUT_CINT, /* critical IRQ */
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| 8 | b7169916 | aurel32 | OPENPIC_OUTPUT_MCK, /* Machine check event */
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| 9 | b7169916 | aurel32 | OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
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| 10 | b7169916 | aurel32 | OPENPIC_OUTPUT_RESET, /* Core reset event */
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| 11 | b7169916 | aurel32 | OPENPIC_OUTPUT_NB, |
| 12 | b7169916 | aurel32 | }; |
| 13 | b7169916 | aurel32 | |
| 14 | b7169916 | aurel32 | qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, |
| 15 | b7169916 | aurel32 | qemu_irq **irqs, qemu_irq irq_out); |
| 16 | c227f099 | Anthony Liguori | qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
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| 17 | b7169916 | aurel32 | qemu_irq **irqs, qemu_irq irq_out); |
| 18 | b7169916 | aurel32 | #endif /* __OPENPIC_H__ */ |