Revision 8bb6e981 target-alpha/translate.c
| b/target-alpha/translate.c | ||
|---|---|---|
| 51 | 51 |
static TCGv cpu_pc; |
| 52 | 52 |
static TCGv cpu_lock; |
| 53 | 53 |
|
| 54 |
/* dyngen register indexes */ |
|
| 55 |
static TCGv cpu_T[2]; |
|
| 56 |
|
|
| 57 | 54 |
/* register names */ |
| 58 | 55 |
static char cpu_reg_names[10*4+21*5 + 10*5+21*6]; |
| 59 | 56 |
|
| ... | ... | |
| 70 | 67 |
|
| 71 | 68 |
cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env"); |
| 72 | 69 |
|
| 73 |
#if TARGET_LONG_BITS > HOST_LONG_BITS |
|
| 74 |
cpu_T[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
|
| 75 |
offsetof(CPUState, t0), "T0"); |
|
| 76 |
cpu_T[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
|
| 77 |
offsetof(CPUState, t1), "T1"); |
|
| 78 |
#else |
|
| 79 |
cpu_T[0] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG1, "T0"); |
|
| 80 |
cpu_T[1] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG2, "T1"); |
|
| 81 |
#endif |
|
| 82 |
|
|
| 83 | 70 |
p = cpu_reg_names; |
| 84 | 71 |
for (i = 0; i < 31; i++) {
|
| 85 | 72 |
sprintf(p, "ir%d", i); |
| ... | ... | |
| 107 | 94 |
done_init = 1; |
| 108 | 95 |
} |
| 109 | 96 |
|
| 110 |
/* Memory moves */ |
|
| 111 |
#if defined(CONFIG_USER_ONLY) |
|
| 112 |
#define OP_LD_TABLE(width) \ |
|
| 113 |
static GenOpFunc *gen_op_ld##width[] = { \
|
|
| 114 |
&gen_op_ld##width##_raw, \ |
|
| 115 |
} |
|
| 116 |
#define OP_ST_TABLE(width) \ |
|
| 117 |
static GenOpFunc *gen_op_st##width[] = { \
|
|
| 118 |
&gen_op_st##width##_raw, \ |
|
| 119 |
} |
|
| 120 |
#else |
|
| 121 |
#define OP_LD_TABLE(width) \ |
|
| 122 |
static GenOpFunc *gen_op_ld##width[] = { \
|
|
| 123 |
&gen_op_ld##width##_kernel, \ |
|
| 124 |
&gen_op_ld##width##_executive, \ |
|
| 125 |
&gen_op_ld##width##_supervisor, \ |
|
| 126 |
&gen_op_ld##width##_user, \ |
|
| 127 |
} |
|
| 128 |
#define OP_ST_TABLE(width) \ |
|
| 129 |
static GenOpFunc *gen_op_st##width[] = { \
|
|
| 130 |
&gen_op_st##width##_kernel, \ |
|
| 131 |
&gen_op_st##width##_executive, \ |
|
| 132 |
&gen_op_st##width##_supervisor, \ |
|
| 133 |
&gen_op_st##width##_user, \ |
|
| 134 |
} |
|
| 135 |
#endif |
|
| 136 |
|
|
| 137 |
#define GEN_LD(width) \ |
|
| 138 |
OP_LD_TABLE(width); \ |
|
| 139 |
static always_inline void gen_ld##width (DisasContext *ctx) \ |
|
| 140 |
{ \
|
|
| 141 |
(*gen_op_ld##width[ctx->mem_idx])(); \ |
|
| 142 |
} |
|
| 143 |
|
|
| 144 |
#define GEN_ST(width) \ |
|
| 145 |
OP_ST_TABLE(width); \ |
|
| 146 |
static always_inline void gen_st##width (DisasContext *ctx) \ |
|
| 147 |
{ \
|
|
| 148 |
(*gen_op_st##width[ctx->mem_idx])(); \ |
|
| 149 |
} |
|
| 150 |
|
|
| 151 |
GEN_LD(l); |
|
| 152 |
GEN_ST(l); |
|
| 153 |
GEN_LD(q); |
|
| 154 |
GEN_ST(q); |
|
| 155 |
GEN_LD(l_l); |
|
| 156 |
GEN_ST(l_c); |
|
| 157 |
GEN_LD(q_l); |
|
| 158 |
GEN_ST(q_c); |
|
| 159 |
|
|
| 160 | 97 |
static always_inline void gen_excp (DisasContext *ctx, |
| 161 | 98 |
int exception, int error_code) |
| 162 | 99 |
{
|
| ... | ... | |
| 1027 | 964 |
if (ra != 31) {
|
| 1028 | 965 |
if (islit) |
| 1029 | 966 |
tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], lit); |
| 1030 |
else
|
|
| 967 |
else
|
|
| 1031 | 968 |
tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
| 1032 | 969 |
} else {
|
| 1033 | 970 |
if (islit) |
| ... | ... | |
| 1701 | 1638 |
#else |
| 1702 | 1639 |
if (!ctx->pal_mode) |
| 1703 | 1640 |
goto invalid_opc; |
| 1704 |
gen_op_mfpr(insn & 0xFF); |
|
| 1705 |
if (ra != 31) |
|
| 1706 |
tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]); |
|
| 1641 |
if (ra != 31) {
|
|
| 1642 |
TCGv tmp = tcg_const_i32(insn & 0xFF); |
|
| 1643 |
tcg_gen_helper_1_2(helper_mfpr, cpu_ir[ra], tmp, cpu_ir[ra]); |
|
| 1644 |
tcg_temp_free(tmp); |
|
| 1645 |
} |
|
| 1707 | 1646 |
break; |
| 1708 | 1647 |
#endif |
| 1709 | 1648 |
case 0x1A: |
| ... | ... | |
| 1737 | 1676 |
#else |
| 1738 | 1677 |
if (!ctx->pal_mode) |
| 1739 | 1678 |
goto invalid_opc; |
| 1740 |
if (rb != 31) |
|
| 1741 |
tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]); |
|
| 1742 |
else |
|
| 1743 |
tcg_gen_movi_i64(cpu_T[0], 0); |
|
| 1744 |
tcg_gen_movi_i64(cpu_T[1], disp12); |
|
| 1745 |
tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
|
| 1746 |
switch ((insn >> 12) & 0xF) {
|
|
| 1747 |
case 0x0: |
|
| 1748 |
/* Longword physical access */ |
|
| 1749 |
gen_op_ldl_raw(); |
|
| 1750 |
break; |
|
| 1751 |
case 0x1: |
|
| 1752 |
/* Quadword physical access */ |
|
| 1753 |
gen_op_ldq_raw(); |
|
| 1754 |
break; |
|
| 1755 |
case 0x2: |
|
| 1756 |
/* Longword physical access with lock */ |
|
| 1757 |
gen_op_ldl_l_raw(); |
|
| 1758 |
break; |
|
| 1759 |
case 0x3: |
|
| 1760 |
/* Quadword physical access with lock */ |
|
| 1761 |
gen_op_ldq_l_raw(); |
|
| 1762 |
break; |
|
| 1763 |
case 0x4: |
|
| 1764 |
/* Longword virtual PTE fetch */ |
|
| 1765 |
gen_op_ldl_kernel(); |
|
| 1766 |
break; |
|
| 1767 |
case 0x5: |
|
| 1768 |
/* Quadword virtual PTE fetch */ |
|
| 1769 |
gen_op_ldq_kernel(); |
|
| 1770 |
break; |
|
| 1771 |
case 0x6: |
|
| 1772 |
/* Invalid */ |
|
| 1773 |
goto invalid_opc; |
|
| 1774 |
case 0x7: |
|
| 1775 |
/* Invalid */ |
|
| 1776 |
goto invalid_opc; |
|
| 1777 |
case 0x8: |
|
| 1778 |
/* Longword virtual access */ |
|
| 1779 |
gen_op_ld_phys_to_virt(); |
|
| 1780 |
gen_op_ldl_raw(); |
|
| 1781 |
break; |
|
| 1782 |
case 0x9: |
|
| 1783 |
/* Quadword virtual access */ |
|
| 1784 |
gen_op_ld_phys_to_virt(); |
|
| 1785 |
gen_op_ldq_raw(); |
|
| 1786 |
break; |
|
| 1787 |
case 0xA: |
|
| 1788 |
/* Longword virtual access with protection check */ |
|
| 1789 |
gen_ldl(ctx); |
|
| 1790 |
break; |
|
| 1791 |
case 0xB: |
|
| 1792 |
/* Quadword virtual access with protection check */ |
|
| 1793 |
gen_ldq(ctx); |
|
| 1794 |
break; |
|
| 1795 |
case 0xC: |
|
| 1796 |
/* Longword virtual access with altenate access mode */ |
|
| 1797 |
gen_op_set_alt_mode(); |
|
| 1798 |
gen_op_ld_phys_to_virt(); |
|
| 1799 |
gen_op_ldl_raw(); |
|
| 1800 |
gen_op_restore_mode(); |
|
| 1801 |
break; |
|
| 1802 |
case 0xD: |
|
| 1803 |
/* Quadword virtual access with altenate access mode */ |
|
| 1804 |
gen_op_set_alt_mode(); |
|
| 1805 |
gen_op_ld_phys_to_virt(); |
|
| 1806 |
gen_op_ldq_raw(); |
|
| 1807 |
gen_op_restore_mode(); |
|
| 1808 |
break; |
|
| 1809 |
case 0xE: |
|
| 1810 |
/* Longword virtual access with alternate access mode and |
|
| 1811 |
* protection checks |
|
| 1812 |
*/ |
|
| 1813 |
gen_op_set_alt_mode(); |
|
| 1814 |
gen_op_ldl_data(); |
|
| 1815 |
gen_op_restore_mode(); |
|
| 1816 |
break; |
|
| 1817 |
case 0xF: |
|
| 1818 |
/* Quadword virtual access with alternate access mode and |
|
| 1819 |
* protection checks |
|
| 1820 |
*/ |
|
| 1821 |
gen_op_set_alt_mode(); |
|
| 1822 |
gen_op_ldq_data(); |
|
| 1823 |
gen_op_restore_mode(); |
|
| 1824 |
break; |
|
| 1679 |
if (ra != 31) {
|
|
| 1680 |
TCGv addr = tcg_temp_new(TCG_TYPE_I64); |
|
| 1681 |
if (rb != 31) |
|
| 1682 |
tcg_gen_addi_i64(addr, cpu_ir[rb], disp12); |
|
| 1683 |
else |
|
| 1684 |
tcg_gen_movi_i64(addr, disp12); |
|
| 1685 |
switch ((insn >> 12) & 0xF) {
|
|
| 1686 |
case 0x0: |
|
| 1687 |
/* Longword physical access */ |
|
| 1688 |
tcg_gen_helper_0_2(helper_ldl_raw, cpu_ir[ra], addr); |
|
| 1689 |
break; |
|
| 1690 |
case 0x1: |
|
| 1691 |
/* Quadword physical access */ |
|
| 1692 |
tcg_gen_helper_0_2(helper_ldq_raw, cpu_ir[ra], addr); |
|
| 1693 |
break; |
|
| 1694 |
case 0x2: |
|
| 1695 |
/* Longword physical access with lock */ |
|
| 1696 |
tcg_gen_helper_0_2(helper_ldl_l_raw, cpu_ir[ra], addr); |
|
| 1697 |
break; |
|
| 1698 |
case 0x3: |
|
| 1699 |
/* Quadword physical access with lock */ |
|
| 1700 |
tcg_gen_helper_0_2(helper_ldq_l_raw, cpu_ir[ra], addr); |
|
| 1701 |
break; |
|
| 1702 |
case 0x4: |
|
| 1703 |
/* Longword virtual PTE fetch */ |
|
| 1704 |
tcg_gen_helper_0_2(helper_ldl_kernel, cpu_ir[ra], addr); |
|
| 1705 |
break; |
|
| 1706 |
case 0x5: |
|
| 1707 |
/* Quadword virtual PTE fetch */ |
|
| 1708 |
tcg_gen_helper_0_2(helper_ldq_kernel, cpu_ir[ra], addr); |
|
| 1709 |
break; |
|
| 1710 |
case 0x6: |
|
| 1711 |
/* Incpu_ir[ra]id */ |
|
| 1712 |
goto incpu_ir[ra]id_opc; |
|
| 1713 |
case 0x7: |
|
| 1714 |
/* Incpu_ir[ra]id */ |
|
| 1715 |
goto incpu_ir[ra]id_opc; |
|
| 1716 |
case 0x8: |
|
| 1717 |
/* Longword virtual access */ |
|
| 1718 |
tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); |
|
| 1719 |
tcg_gen_helper_0_2(helper_ldl_raw, cpu_ir[ra], addr); |
|
| 1720 |
break; |
|
| 1721 |
case 0x9: |
|
| 1722 |
/* Quadword virtual access */ |
|
| 1723 |
tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); |
|
| 1724 |
tcg_gen_helper_0_2(helper_ldq_raw, cpu_ir[ra], addr); |
|
| 1725 |
break; |
|
| 1726 |
case 0xA: |
|
| 1727 |
/* Longword virtual access with protection check */ |
|
| 1728 |
tcg_gen_qemu_ld32s(cpu_ir[ra], addr, ctx->flags); |
|
| 1729 |
break; |
|
| 1730 |
case 0xB: |
|
| 1731 |
/* Quadword virtual access with protection check */ |
|
| 1732 |
tcg_gen_qemu_ld64(cpu_ir[ra], addr, ctx->flags); |
|
| 1733 |
break; |
|
| 1734 |
case 0xC: |
|
| 1735 |
/* Longword virtual access with altenate access mode */ |
|
| 1736 |
tcg_gen_helper_0_0(helper_set_alt_mode); |
|
| 1737 |
tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); |
|
| 1738 |
tcg_gen_helper_0_2(helper_ldl_raw, cpu_ir[ra], addr); |
|
| 1739 |
tcg_gen_helper_0_0(helper_restore_mode); |
|
| 1740 |
break; |
|
| 1741 |
case 0xD: |
|
| 1742 |
/* Quadword virtual access with altenate access mode */ |
|
| 1743 |
tcg_gen_helper_0_0(helper_set_alt_mode); |
|
| 1744 |
tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); |
|
| 1745 |
tcg_gen_helper_0_2(helper_ldq_raw, cpu_ir[ra], addr); |
|
| 1746 |
tcg_gen_helper_0_0(helper_restore_mode); |
|
| 1747 |
break; |
|
| 1748 |
case 0xE: |
|
| 1749 |
/* Longword virtual access with alternate access mode and |
|
| 1750 |
* protection checks |
|
| 1751 |
*/ |
|
| 1752 |
tcg_gen_helper_0_0(helper_set_alt_mode); |
|
| 1753 |
tcg_gen_helper_0_2(helper_ldl_data, cpu_ir[ra], addr); |
|
| 1754 |
tcg_gen_helper_0_0(helper_restore_mode); |
|
| 1755 |
break; |
|
| 1756 |
case 0xF: |
|
| 1757 |
/* Quadword virtual access with alternate access mode and |
|
| 1758 |
* protection checks |
|
| 1759 |
*/ |
|
| 1760 |
tcg_gen_helper_0_0(helper_set_alt_mode); |
|
| 1761 |
tcg_gen_helper_0_2(helper_ldq_data, cpu_ir[ra], addr); |
|
| 1762 |
tcg_gen_helper_0_0(helper_restore_mode); |
|
| 1763 |
break; |
|
| 1764 |
} |
|
| 1765 |
tcg_temp_free(addr); |
|
| 1825 | 1766 |
} |
| 1826 |
if (ra != 31) |
|
| 1827 |
tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]); |
|
| 1828 | 1767 |
break; |
| 1829 | 1768 |
#endif |
| 1830 | 1769 |
case 0x1C: |
| ... | ... | |
| 2014 | 1953 |
#else |
| 2015 | 1954 |
if (!ctx->pal_mode) |
| 2016 | 1955 |
goto invalid_opc; |
| 2017 |
if (ra != 31) |
|
| 2018 |
tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]); |
|
| 2019 |
else |
|
| 2020 |
tcg_gen_movi_i64(cpu_T[0], 0); |
|
| 2021 |
gen_op_mtpr(insn & 0xFF); |
|
| 2022 |
ret = 2; |
|
| 1956 |
else {
|
|
| 1957 |
TCGv tmp1 = tcg_const_i32(insn & 0xFF); |
|
| 1958 |
if (ra != 31) |
|
| 1959 |
tcg_gen_helper(helper_mtpr, tmp1, cpu_ir[ra]); |
|
| 1960 |
else {
|
|
| 1961 |
TCGv tmp2 = tcg_const_i64(0); |
|
| 1962 |
tcg_gen_helper(helper_mtpr, tmp1, tmp2); |
|
| 1963 |
tcg_temp_free(tmp2); |
|
| 1964 |
} |
|
| 1965 |
tcg_temp_free(tmp1); |
|
| 1966 |
ret = 2; |
|
| 1967 |
} |
|
| 2023 | 1968 |
break; |
| 2024 | 1969 |
#endif |
| 2025 | 1970 |
case 0x1E: |
| ... | ... | |
| 2031 | 1976 |
goto invalid_opc; |
| 2032 | 1977 |
if (rb == 31) {
|
| 2033 | 1978 |
/* "Old" alpha */ |
| 2034 |
gen_op_hw_rei();
|
|
| 1979 |
tcg_gen_helper_0_0(helper_hw_rei);
|
|
| 2035 | 1980 |
} else {
|
| 2036 |
if (ra != 31) |
|
| 2037 |
tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]); |
|
| 2038 |
else |
|
| 2039 |
tcg_gen_movi_i64(cpu_T[0], 0); |
|
| 2040 |
tcg_gen_movi_i64(cpu_T[1], (((int64_t)insn << 51) >> 51)); |
|
| 2041 |
tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
|
| 2042 |
gen_op_hw_ret(); |
|
| 1981 |
TCGv tmp; |
|
| 1982 |
|
|
| 1983 |
if (ra != 31) {
|
|
| 1984 |
tmp = tcg_temp_new(TCG_TYPE_I64); |
|
| 1985 |
tcg_gen_addi_i64(tmp, cpu_ir[rb], (((int64_t)insn << 51) >> 51)); |
|
| 1986 |
} else |
|
| 1987 |
tmp = tcg_const_i64(((int64_t)insn << 51) >> 51); |
|
| 1988 |
tcg_gen_helper_0_1(helper_hw_ret, tmp); |
|
| 1989 |
tcg_temp_free(tmp); |
|
| 2043 | 1990 |
} |
| 2044 | 1991 |
ret = 2; |
| 2045 | 1992 |
break; |
| ... | ... | |
| 2051 | 1998 |
#else |
| 2052 | 1999 |
if (!ctx->pal_mode) |
| 2053 | 2000 |
goto invalid_opc; |
| 2054 |
if (ra != 31) |
|
| 2055 |
tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp12); |
|
| 2056 |
else |
|
| 2057 |
tcg_gen_movi_i64(cpu_T[0], disp12); |
|
| 2058 |
if (ra != 31) |
|
| 2059 |
tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]); |
|
| 2060 |
else |
|
| 2061 |
tcg_gen_movi_i64(cpu_T[1], 0); |
|
| 2062 |
switch ((insn >> 12) & 0xF) {
|
|
| 2063 |
case 0x0: |
|
| 2064 |
/* Longword physical access */ |
|
| 2065 |
gen_op_stl_raw(); |
|
| 2066 |
break; |
|
| 2067 |
case 0x1: |
|
| 2068 |
/* Quadword physical access */ |
|
| 2069 |
gen_op_stq_raw(); |
|
| 2070 |
break; |
|
| 2071 |
case 0x2: |
|
| 2072 |
/* Longword physical access with lock */ |
|
| 2073 |
gen_op_stl_c_raw(); |
|
| 2074 |
break; |
|
| 2075 |
case 0x3: |
|
| 2076 |
/* Quadword physical access with lock */ |
|
| 2077 |
gen_op_stq_c_raw(); |
|
| 2078 |
break; |
|
| 2079 |
case 0x4: |
|
| 2080 |
/* Longword virtual access */ |
|
| 2081 |
gen_op_st_phys_to_virt(); |
|
| 2082 |
gen_op_stl_raw(); |
|
| 2083 |
break; |
|
| 2084 |
case 0x5: |
|
| 2085 |
/* Quadword virtual access */ |
|
| 2086 |
gen_op_st_phys_to_virt(); |
|
| 2087 |
gen_op_stq_raw(); |
|
| 2088 |
break; |
|
| 2089 |
case 0x6: |
|
| 2090 |
/* Invalid */ |
|
| 2091 |
goto invalid_opc; |
|
| 2092 |
case 0x7: |
|
| 2093 |
/* Invalid */ |
|
| 2094 |
goto invalid_opc; |
|
| 2095 |
case 0x8: |
|
| 2096 |
/* Invalid */ |
|
| 2097 |
goto invalid_opc; |
|
| 2098 |
case 0x9: |
|
| 2099 |
/* Invalid */ |
|
| 2100 |
goto invalid_opc; |
|
| 2101 |
case 0xA: |
|
| 2102 |
/* Invalid */ |
|
| 2103 |
goto invalid_opc; |
|
| 2104 |
case 0xB: |
|
| 2105 |
/* Invalid */ |
|
| 2106 |
goto invalid_opc; |
|
| 2107 |
case 0xC: |
|
| 2108 |
/* Longword virtual access with alternate access mode */ |
|
| 2109 |
gen_op_set_alt_mode(); |
|
| 2110 |
gen_op_st_phys_to_virt(); |
|
| 2111 |
gen_op_ldl_raw(); |
|
| 2112 |
gen_op_restore_mode(); |
|
| 2113 |
break; |
|
| 2114 |
case 0xD: |
|
| 2115 |
/* Quadword virtual access with alternate access mode */ |
|
| 2116 |
gen_op_set_alt_mode(); |
|
| 2117 |
gen_op_st_phys_to_virt(); |
|
| 2118 |
gen_op_ldq_raw(); |
|
| 2119 |
gen_op_restore_mode(); |
|
| 2120 |
break; |
|
| 2121 |
case 0xE: |
|
| 2122 |
/* Invalid */ |
|
| 2123 |
goto invalid_opc; |
|
| 2124 |
case 0xF: |
|
| 2125 |
/* Invalid */ |
|
| 2126 |
goto invalid_opc; |
|
| 2001 |
else {
|
|
| 2002 |
TCGv addr, val; |
|
| 2003 |
addr = tcg_temp_new(TCG_TYPE_I64); |
|
| 2004 |
if (rb != 31) |
|
| 2005 |
tcg_gen_addi_i64(addr, cpu_ir[rb], disp12); |
|
| 2006 |
else |
|
| 2007 |
tcg_gen_movi_i64(addr, disp12); |
|
| 2008 |
if (ra != 31) |
|
| 2009 |
val = cpu_ir[ra]; |
|
| 2010 |
else {
|
|
| 2011 |
val = tcg_temp_new(TCG_TYPE_I64); |
|
| 2012 |
tcg_gen_movi_i64(val, 0); |
|
| 2013 |
} |
|
| 2014 |
switch ((insn >> 12) & 0xF) {
|
|
| 2015 |
case 0x0: |
|
| 2016 |
/* Longword physical access */ |
|
| 2017 |
tcg_gen_helper_0_2(helper_stl_raw, val, addr); |
|
| 2018 |
break; |
|
| 2019 |
case 0x1: |
|
| 2020 |
/* Quadword physical access */ |
|
| 2021 |
tcg_gen_helper_0_2(helper_stq_raw, val, addr); |
|
| 2022 |
break; |
|
| 2023 |
case 0x2: |
|
| 2024 |
/* Longword physical access with lock */ |
|
| 2025 |
tcg_gen_helper_1_2(helper_stl_c_raw, val, val, addr); |
|
| 2026 |
break; |
|
| 2027 |
case 0x3: |
|
| 2028 |
/* Quadword physical access with lock */ |
|
| 2029 |
tcg_gen_helper_1_2(helper_stq_c_raw, val, val, addr); |
|
| 2030 |
break; |
|
| 2031 |
case 0x4: |
|
| 2032 |
/* Longword virtual access */ |
|
| 2033 |
tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); |
|
| 2034 |
tcg_gen_helper_0_2(helper_stl_raw, val, addr); |
|
| 2035 |
break; |
|
| 2036 |
case 0x5: |
|
| 2037 |
/* Quadword virtual access */ |
|
| 2038 |
tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); |
|
| 2039 |
tcg_gen_helper_0_2(helper_stq_raw, val, addr); |
|
| 2040 |
break; |
|
| 2041 |
case 0x6: |
|
| 2042 |
/* Invalid */ |
|
| 2043 |
goto invalid_opc; |
|
| 2044 |
case 0x7: |
|
| 2045 |
/* Invalid */ |
|
| 2046 |
goto invalid_opc; |
|
| 2047 |
case 0x8: |
|
| 2048 |
/* Invalid */ |
|
| 2049 |
goto invalid_opc; |
|
| 2050 |
case 0x9: |
|
| 2051 |
/* Invalid */ |
|
| 2052 |
goto invalid_opc; |
|
| 2053 |
case 0xA: |
|
| 2054 |
/* Invalid */ |
|
| 2055 |
goto invalid_opc; |
|
| 2056 |
case 0xB: |
|
| 2057 |
/* Invalid */ |
|
| 2058 |
goto invalid_opc; |
|
| 2059 |
case 0xC: |
|
| 2060 |
/* Longword virtual access with alternate access mode */ |
|
| 2061 |
tcg_gen_helper_0_0(helper_set_alt_mode); |
|
| 2062 |
tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); |
|
| 2063 |
tcg_gen_helper_0_2(helper_stl_raw, val, addr); |
|
| 2064 |
tcg_gen_helper_0_0(helper_restore_mode); |
|
| 2065 |
break; |
|
| 2066 |
case 0xD: |
|
| 2067 |
/* Quadword virtual access with alternate access mode */ |
|
| 2068 |
tcg_gen_helper_0_0(helper_set_alt_mode); |
|
| 2069 |
tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); |
|
| 2070 |
tcg_gen_helper_0_2(helper_stl_raw, val, addr); |
|
| 2071 |
tcg_gen_helper_0_0(helper_restore_mode); |
|
| 2072 |
break; |
|
| 2073 |
case 0xE: |
|
| 2074 |
/* Invalid */ |
|
| 2075 |
goto invalid_opc; |
|
| 2076 |
case 0xF: |
|
| 2077 |
/* Invalid */ |
|
| 2078 |
goto invalid_opc; |
|
| 2079 |
} |
|
| 2080 |
if (ra != 31) |
|
| 2081 |
tcg_temp_free(val); |
|
| 2082 |
tcg_temp_free(addr); |
|
| 2127 | 2083 |
} |
| 2128 | 2084 |
ret = 2; |
| 2129 | 2085 |
break; |
Also available in: Unified diff