root / hw / pc.c @ 8bfbde6d
History | View | Annotate | Download (33.1 kB)
| 1 |
/*
|
|---|---|
| 2 |
* QEMU PC System Emulator
|
| 3 |
*
|
| 4 |
* Copyright (c) 2003-2004 Fabrice Bellard
|
| 5 |
*
|
| 6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
| 7 |
* of this software and associated documentation files (the "Software"), to deal
|
| 8 |
* in the Software without restriction, including without limitation the rights
|
| 9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
| 10 |
* copies of the Software, and to permit persons to whom the Software is
|
| 11 |
* furnished to do so, subject to the following conditions:
|
| 12 |
*
|
| 13 |
* The above copyright notice and this permission notice shall be included in
|
| 14 |
* all copies or substantial portions of the Software.
|
| 15 |
*
|
| 16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
| 17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
| 18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
| 19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
| 20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
| 21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
| 22 |
* THE SOFTWARE.
|
| 23 |
*/
|
| 24 |
#include "hw.h" |
| 25 |
#include "pc.h" |
| 26 |
#include "fdc.h" |
| 27 |
#include "pci.h" |
| 28 |
#include "vmware_vga.h" |
| 29 |
#include "usb-uhci.h" |
| 30 |
#include "usb-ohci.h" |
| 31 |
#include "prep_pci.h" |
| 32 |
#include "apb_pci.h" |
| 33 |
#include "block.h" |
| 34 |
#include "sysemu.h" |
| 35 |
#include "audio/audio.h" |
| 36 |
#include "net.h" |
| 37 |
#include "smbus.h" |
| 38 |
#include "boards.h" |
| 39 |
#include "monitor.h" |
| 40 |
#include "fw_cfg.h" |
| 41 |
#include "hpet_emul.h" |
| 42 |
#include "watchdog.h" |
| 43 |
#include "smbios.h" |
| 44 |
#include "ide.h" |
| 45 |
#include "loader.h" |
| 46 |
#include "elf.h" |
| 47 |
#include "multiboot.h" |
| 48 |
|
| 49 |
/* output Bochs bios info messages */
|
| 50 |
//#define DEBUG_BIOS
|
| 51 |
|
| 52 |
#define BIOS_FILENAME "bios.bin" |
| 53 |
|
| 54 |
#define PC_MAX_BIOS_SIZE (4 * 1024 * 1024) |
| 55 |
|
| 56 |
/* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
|
| 57 |
#define ACPI_DATA_SIZE 0x10000 |
| 58 |
#define BIOS_CFG_IOPORT 0x510 |
| 59 |
#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
| 60 |
#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
| 61 |
#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
| 62 |
|
| 63 |
#define MAX_IDE_BUS 2 |
| 64 |
|
| 65 |
static FDCtrl *floppy_controller;
|
| 66 |
static RTCState *rtc_state;
|
| 67 |
static PITState *pit;
|
| 68 |
static PCII440FXState *i440fx_state;
|
| 69 |
|
| 70 |
typedef struct isa_irq_state { |
| 71 |
qemu_irq *i8259; |
| 72 |
qemu_irq *ioapic; |
| 73 |
} IsaIrqState; |
| 74 |
|
| 75 |
static void isa_irq_handler(void *opaque, int n, int level) |
| 76 |
{
|
| 77 |
IsaIrqState *isa = (IsaIrqState *)opaque; |
| 78 |
|
| 79 |
if (n < 16) { |
| 80 |
qemu_set_irq(isa->i8259[n], level); |
| 81 |
} |
| 82 |
if (isa->ioapic)
|
| 83 |
qemu_set_irq(isa->ioapic[n], level); |
| 84 |
}; |
| 85 |
|
| 86 |
static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
| 87 |
{
|
| 88 |
} |
| 89 |
|
| 90 |
/* MSDOS compatibility mode FPU exception support */
|
| 91 |
static qemu_irq ferr_irq;
|
| 92 |
/* XXX: add IGNNE support */
|
| 93 |
void cpu_set_ferr(CPUX86State *s)
|
| 94 |
{
|
| 95 |
qemu_irq_raise(ferr_irq); |
| 96 |
} |
| 97 |
|
| 98 |
static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) |
| 99 |
{
|
| 100 |
qemu_irq_lower(ferr_irq); |
| 101 |
} |
| 102 |
|
| 103 |
/* TSC handling */
|
| 104 |
uint64_t cpu_get_tsc(CPUX86State *env) |
| 105 |
{
|
| 106 |
return cpu_get_ticks();
|
| 107 |
} |
| 108 |
|
| 109 |
/* SMM support */
|
| 110 |
void cpu_smm_update(CPUState *env)
|
| 111 |
{
|
| 112 |
if (i440fx_state && env == first_cpu)
|
| 113 |
i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
|
| 114 |
} |
| 115 |
|
| 116 |
|
| 117 |
/* IRQ handling */
|
| 118 |
int cpu_get_pic_interrupt(CPUState *env)
|
| 119 |
{
|
| 120 |
int intno;
|
| 121 |
|
| 122 |
intno = apic_get_interrupt(env); |
| 123 |
if (intno >= 0) { |
| 124 |
/* set irq request if a PIC irq is still pending */
|
| 125 |
/* XXX: improve that */
|
| 126 |
pic_update_irq(isa_pic); |
| 127 |
return intno;
|
| 128 |
} |
| 129 |
/* read the irq from the PIC */
|
| 130 |
if (!apic_accept_pic_intr(env))
|
| 131 |
return -1; |
| 132 |
|
| 133 |
intno = pic_read_irq(isa_pic); |
| 134 |
return intno;
|
| 135 |
} |
| 136 |
|
| 137 |
static void pic_irq_request(void *opaque, int irq, int level) |
| 138 |
{
|
| 139 |
CPUState *env = first_cpu; |
| 140 |
|
| 141 |
if (env->apic_state) {
|
| 142 |
while (env) {
|
| 143 |
if (apic_accept_pic_intr(env))
|
| 144 |
apic_deliver_pic_intr(env, level); |
| 145 |
env = env->next_cpu; |
| 146 |
} |
| 147 |
} else {
|
| 148 |
if (level)
|
| 149 |
cpu_interrupt(env, CPU_INTERRUPT_HARD); |
| 150 |
else
|
| 151 |
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
| 152 |
} |
| 153 |
} |
| 154 |
|
| 155 |
/* PC cmos mappings */
|
| 156 |
|
| 157 |
#define REG_EQUIPMENT_BYTE 0x14 |
| 158 |
|
| 159 |
static int cmos_get_fd_drive_type(int fd0) |
| 160 |
{
|
| 161 |
int val;
|
| 162 |
|
| 163 |
switch (fd0) {
|
| 164 |
case 0: |
| 165 |
/* 1.44 Mb 3"5 drive */
|
| 166 |
val = 4;
|
| 167 |
break;
|
| 168 |
case 1: |
| 169 |
/* 2.88 Mb 3"5 drive */
|
| 170 |
val = 5;
|
| 171 |
break;
|
| 172 |
case 2: |
| 173 |
/* 1.2 Mb 5"5 drive */
|
| 174 |
val = 2;
|
| 175 |
break;
|
| 176 |
default:
|
| 177 |
val = 0;
|
| 178 |
break;
|
| 179 |
} |
| 180 |
return val;
|
| 181 |
} |
| 182 |
|
| 183 |
static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd) |
| 184 |
{
|
| 185 |
RTCState *s = rtc_state; |
| 186 |
int cylinders, heads, sectors;
|
| 187 |
bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors); |
| 188 |
rtc_set_memory(s, type_ofs, 47);
|
| 189 |
rtc_set_memory(s, info_ofs, cylinders); |
| 190 |
rtc_set_memory(s, info_ofs + 1, cylinders >> 8); |
| 191 |
rtc_set_memory(s, info_ofs + 2, heads);
|
| 192 |
rtc_set_memory(s, info_ofs + 3, 0xff); |
| 193 |
rtc_set_memory(s, info_ofs + 4, 0xff); |
| 194 |
rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); |
| 195 |
rtc_set_memory(s, info_ofs + 6, cylinders);
|
| 196 |
rtc_set_memory(s, info_ofs + 7, cylinders >> 8); |
| 197 |
rtc_set_memory(s, info_ofs + 8, sectors);
|
| 198 |
} |
| 199 |
|
| 200 |
/* convert boot_device letter to something recognizable by the bios */
|
| 201 |
static int boot_device2nibble(char boot_device) |
| 202 |
{
|
| 203 |
switch(boot_device) {
|
| 204 |
case 'a': |
| 205 |
case 'b': |
| 206 |
return 0x01; /* floppy boot */ |
| 207 |
case 'c': |
| 208 |
return 0x02; /* hard drive boot */ |
| 209 |
case 'd': |
| 210 |
return 0x03; /* CD-ROM boot */ |
| 211 |
case 'n': |
| 212 |
return 0x04; /* Network boot */ |
| 213 |
} |
| 214 |
return 0; |
| 215 |
} |
| 216 |
|
| 217 |
/* copy/pasted from cmos_init, should be made a general function
|
| 218 |
and used there as well */
|
| 219 |
static int pc_boot_set(void *opaque, const char *boot_device) |
| 220 |
{
|
| 221 |
Monitor *mon = cur_mon; |
| 222 |
#define PC_MAX_BOOT_DEVICES 3 |
| 223 |
RTCState *s = (RTCState *)opaque; |
| 224 |
int nbds, bds[3] = { 0, }; |
| 225 |
int i;
|
| 226 |
|
| 227 |
nbds = strlen(boot_device); |
| 228 |
if (nbds > PC_MAX_BOOT_DEVICES) {
|
| 229 |
monitor_printf(mon, "Too many boot devices for PC\n");
|
| 230 |
return(1); |
| 231 |
} |
| 232 |
for (i = 0; i < nbds; i++) { |
| 233 |
bds[i] = boot_device2nibble(boot_device[i]); |
| 234 |
if (bds[i] == 0) { |
| 235 |
monitor_printf(mon, "Invalid boot device for PC: '%c'\n",
|
| 236 |
boot_device[i]); |
| 237 |
return(1); |
| 238 |
} |
| 239 |
} |
| 240 |
rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); |
| 241 |
rtc_set_memory(s, 0x38, (bds[2] << 4)); |
| 242 |
return(0); |
| 243 |
} |
| 244 |
|
| 245 |
/* hd_table must contain 4 block drivers */
|
| 246 |
static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, |
| 247 |
const char *boot_device, DriveInfo **hd_table) |
| 248 |
{
|
| 249 |
RTCState *s = rtc_state; |
| 250 |
int nbds, bds[3] = { 0, }; |
| 251 |
int val;
|
| 252 |
int fd0, fd1, nb;
|
| 253 |
int i;
|
| 254 |
|
| 255 |
/* various important CMOS locations needed by PC/Bochs bios */
|
| 256 |
|
| 257 |
/* memory size */
|
| 258 |
val = 640; /* base memory in K */ |
| 259 |
rtc_set_memory(s, 0x15, val);
|
| 260 |
rtc_set_memory(s, 0x16, val >> 8); |
| 261 |
|
| 262 |
val = (ram_size / 1024) - 1024; |
| 263 |
if (val > 65535) |
| 264 |
val = 65535;
|
| 265 |
rtc_set_memory(s, 0x17, val);
|
| 266 |
rtc_set_memory(s, 0x18, val >> 8); |
| 267 |
rtc_set_memory(s, 0x30, val);
|
| 268 |
rtc_set_memory(s, 0x31, val >> 8); |
| 269 |
|
| 270 |
if (above_4g_mem_size) {
|
| 271 |
rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); |
| 272 |
rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); |
| 273 |
rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); |
| 274 |
} |
| 275 |
|
| 276 |
if (ram_size > (16 * 1024 * 1024)) |
| 277 |
val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); |
| 278 |
else
|
| 279 |
val = 0;
|
| 280 |
if (val > 65535) |
| 281 |
val = 65535;
|
| 282 |
rtc_set_memory(s, 0x34, val);
|
| 283 |
rtc_set_memory(s, 0x35, val >> 8); |
| 284 |
|
| 285 |
/* set the number of CPU */
|
| 286 |
rtc_set_memory(s, 0x5f, smp_cpus - 1); |
| 287 |
|
| 288 |
/* set boot devices, and disable floppy signature check if requested */
|
| 289 |
#define PC_MAX_BOOT_DEVICES 3 |
| 290 |
nbds = strlen(boot_device); |
| 291 |
if (nbds > PC_MAX_BOOT_DEVICES) {
|
| 292 |
fprintf(stderr, "Too many boot devices for PC\n");
|
| 293 |
exit(1);
|
| 294 |
} |
| 295 |
for (i = 0; i < nbds; i++) { |
| 296 |
bds[i] = boot_device2nibble(boot_device[i]); |
| 297 |
if (bds[i] == 0) { |
| 298 |
fprintf(stderr, "Invalid boot device for PC: '%c'\n",
|
| 299 |
boot_device[i]); |
| 300 |
exit(1);
|
| 301 |
} |
| 302 |
} |
| 303 |
rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); |
| 304 |
rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
| 305 |
|
| 306 |
/* floppy type */
|
| 307 |
|
| 308 |
fd0 = fdctrl_get_drive_type(floppy_controller, 0);
|
| 309 |
fd1 = fdctrl_get_drive_type(floppy_controller, 1);
|
| 310 |
|
| 311 |
val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
|
| 312 |
rtc_set_memory(s, 0x10, val);
|
| 313 |
|
| 314 |
val = 0;
|
| 315 |
nb = 0;
|
| 316 |
if (fd0 < 3) |
| 317 |
nb++; |
| 318 |
if (fd1 < 3) |
| 319 |
nb++; |
| 320 |
switch (nb) {
|
| 321 |
case 0: |
| 322 |
break;
|
| 323 |
case 1: |
| 324 |
val |= 0x01; /* 1 drive, ready for boot */ |
| 325 |
break;
|
| 326 |
case 2: |
| 327 |
val |= 0x41; /* 2 drives, ready for boot */ |
| 328 |
break;
|
| 329 |
} |
| 330 |
val |= 0x02; /* FPU is there */ |
| 331 |
val |= 0x04; /* PS/2 mouse installed */ |
| 332 |
rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); |
| 333 |
|
| 334 |
/* hard drives */
|
| 335 |
|
| 336 |
rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0)); |
| 337 |
if (hd_table[0]) |
| 338 |
cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv); |
| 339 |
if (hd_table[1]) |
| 340 |
cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv); |
| 341 |
|
| 342 |
val = 0;
|
| 343 |
for (i = 0; i < 4; i++) { |
| 344 |
if (hd_table[i]) {
|
| 345 |
int cylinders, heads, sectors, translation;
|
| 346 |
/* NOTE: bdrv_get_geometry_hint() returns the physical
|
| 347 |
geometry. It is always such that: 1 <= sects <= 63, 1
|
| 348 |
<= heads <= 16, 1 <= cylinders <= 16383. The BIOS
|
| 349 |
geometry can be different if a translation is done. */
|
| 350 |
translation = bdrv_get_translation_hint(hd_table[i]->bdrv); |
| 351 |
if (translation == BIOS_ATA_TRANSLATION_AUTO) {
|
| 352 |
bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, §ors); |
| 353 |
if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { |
| 354 |
/* No translation. */
|
| 355 |
translation = 0;
|
| 356 |
} else {
|
| 357 |
/* LBA translation. */
|
| 358 |
translation = 1;
|
| 359 |
} |
| 360 |
} else {
|
| 361 |
translation--; |
| 362 |
} |
| 363 |
val |= translation << (i * 2);
|
| 364 |
} |
| 365 |
} |
| 366 |
rtc_set_memory(s, 0x39, val);
|
| 367 |
} |
| 368 |
|
| 369 |
void ioport_set_a20(int enable) |
| 370 |
{
|
| 371 |
/* XXX: send to all CPUs ? */
|
| 372 |
cpu_x86_set_a20(first_cpu, enable); |
| 373 |
} |
| 374 |
|
| 375 |
int ioport_get_a20(void) |
| 376 |
{
|
| 377 |
return ((first_cpu->a20_mask >> 20) & 1); |
| 378 |
} |
| 379 |
|
| 380 |
static void ioport92_write(void *opaque, uint32_t addr, uint32_t val) |
| 381 |
{
|
| 382 |
ioport_set_a20((val >> 1) & 1); |
| 383 |
/* XXX: bit 0 is fast reset */
|
| 384 |
} |
| 385 |
|
| 386 |
static uint32_t ioport92_read(void *opaque, uint32_t addr) |
| 387 |
{
|
| 388 |
return ioport_get_a20() << 1; |
| 389 |
} |
| 390 |
|
| 391 |
/***********************************************************/
|
| 392 |
/* Bochs BIOS debug ports */
|
| 393 |
|
| 394 |
static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) |
| 395 |
{
|
| 396 |
static const char shutdown_str[8] = "Shutdown"; |
| 397 |
static int shutdown_index = 0; |
| 398 |
|
| 399 |
switch(addr) {
|
| 400 |
/* Bochs BIOS messages */
|
| 401 |
case 0x400: |
| 402 |
case 0x401: |
| 403 |
fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
|
| 404 |
exit(1);
|
| 405 |
case 0x402: |
| 406 |
case 0x403: |
| 407 |
#ifdef DEBUG_BIOS
|
| 408 |
fprintf(stderr, "%c", val);
|
| 409 |
#endif
|
| 410 |
break;
|
| 411 |
case 0x8900: |
| 412 |
/* same as Bochs power off */
|
| 413 |
if (val == shutdown_str[shutdown_index]) {
|
| 414 |
shutdown_index++; |
| 415 |
if (shutdown_index == 8) { |
| 416 |
shutdown_index = 0;
|
| 417 |
qemu_system_shutdown_request(); |
| 418 |
} |
| 419 |
} else {
|
| 420 |
shutdown_index = 0;
|
| 421 |
} |
| 422 |
break;
|
| 423 |
|
| 424 |
/* LGPL'ed VGA BIOS messages */
|
| 425 |
case 0x501: |
| 426 |
case 0x502: |
| 427 |
fprintf(stderr, "VGA BIOS panic, line %d\n", val);
|
| 428 |
exit(1);
|
| 429 |
case 0x500: |
| 430 |
case 0x503: |
| 431 |
#ifdef DEBUG_BIOS
|
| 432 |
fprintf(stderr, "%c", val);
|
| 433 |
#endif
|
| 434 |
break;
|
| 435 |
} |
| 436 |
} |
| 437 |
|
| 438 |
static void *bochs_bios_init(void) |
| 439 |
{
|
| 440 |
void *fw_cfg;
|
| 441 |
uint8_t *smbios_table; |
| 442 |
size_t smbios_len; |
| 443 |
uint64_t *numa_fw_cfg; |
| 444 |
int i, j;
|
| 445 |
|
| 446 |
register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); |
| 447 |
register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); |
| 448 |
register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); |
| 449 |
register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); |
| 450 |
register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); |
| 451 |
|
| 452 |
register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); |
| 453 |
register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); |
| 454 |
register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); |
| 455 |
register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); |
| 456 |
|
| 457 |
fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
| 458 |
|
| 459 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
| 460 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
| 461 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, |
| 462 |
acpi_tables_len); |
| 463 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
|
| 464 |
|
| 465 |
smbios_table = smbios_get_table(&smbios_len); |
| 466 |
if (smbios_table)
|
| 467 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, |
| 468 |
smbios_table, smbios_len); |
| 469 |
|
| 470 |
/* allocate memory for the NUMA channel: one (64bit) word for the number
|
| 471 |
* of nodes, one word for each VCPU->node and one word for each node to
|
| 472 |
* hold the amount of memory.
|
| 473 |
*/
|
| 474 |
numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8); |
| 475 |
numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
|
| 476 |
for (i = 0; i < smp_cpus; i++) { |
| 477 |
for (j = 0; j < nb_numa_nodes; j++) { |
| 478 |
if (node_cpumask[j] & (1 << i)) { |
| 479 |
numa_fw_cfg[i + 1] = cpu_to_le64(j);
|
| 480 |
break;
|
| 481 |
} |
| 482 |
} |
| 483 |
} |
| 484 |
for (i = 0; i < nb_numa_nodes; i++) { |
| 485 |
numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
|
| 486 |
} |
| 487 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, |
| 488 |
(1 + smp_cpus + nb_numa_nodes) * 8); |
| 489 |
|
| 490 |
return fw_cfg;
|
| 491 |
} |
| 492 |
|
| 493 |
static long get_file_size(FILE *f) |
| 494 |
{
|
| 495 |
long where, size;
|
| 496 |
|
| 497 |
/* XXX: on Unix systems, using fstat() probably makes more sense */
|
| 498 |
|
| 499 |
where = ftell(f); |
| 500 |
fseek(f, 0, SEEK_END);
|
| 501 |
size = ftell(f); |
| 502 |
fseek(f, where, SEEK_SET); |
| 503 |
|
| 504 |
return size;
|
| 505 |
} |
| 506 |
|
| 507 |
static void load_linux(void *fw_cfg, |
| 508 |
const char *kernel_filename, |
| 509 |
const char *initrd_filename, |
| 510 |
const char *kernel_cmdline, |
| 511 |
target_phys_addr_t max_ram_size) |
| 512 |
{
|
| 513 |
uint16_t protocol; |
| 514 |
int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
| 515 |
uint32_t initrd_max; |
| 516 |
uint8_t header[8192], *setup, *kernel, *initrd_data;
|
| 517 |
target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
|
| 518 |
FILE *f; |
| 519 |
char *vmode;
|
| 520 |
|
| 521 |
/* Align to 16 bytes as a paranoia measure */
|
| 522 |
cmdline_size = (strlen(kernel_cmdline)+16) & ~15; |
| 523 |
|
| 524 |
/* load the kernel header */
|
| 525 |
f = fopen(kernel_filename, "rb");
|
| 526 |
if (!f || !(kernel_size = get_file_size(f)) ||
|
| 527 |
fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
|
| 528 |
MIN(ARRAY_SIZE(header), kernel_size)) {
|
| 529 |
fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
|
| 530 |
kernel_filename, strerror(errno)); |
| 531 |
exit(1);
|
| 532 |
} |
| 533 |
|
| 534 |
/* kernel protocol version */
|
| 535 |
#if 0
|
| 536 |
fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
|
| 537 |
#endif
|
| 538 |
if (ldl_p(header+0x202) == 0x53726448) |
| 539 |
protocol = lduw_p(header+0x206);
|
| 540 |
else {
|
| 541 |
/* This looks like a multiboot kernel. If it is, let's stop
|
| 542 |
treating it like a Linux kernel. */
|
| 543 |
if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
|
| 544 |
kernel_cmdline, kernel_size, header)) |
| 545 |
return;
|
| 546 |
protocol = 0;
|
| 547 |
} |
| 548 |
|
| 549 |
if (protocol < 0x200 || !(header[0x211] & 0x01)) { |
| 550 |
/* Low kernel */
|
| 551 |
real_addr = 0x90000;
|
| 552 |
cmdline_addr = 0x9a000 - cmdline_size;
|
| 553 |
prot_addr = 0x10000;
|
| 554 |
} else if (protocol < 0x202) { |
| 555 |
/* High but ancient kernel */
|
| 556 |
real_addr = 0x90000;
|
| 557 |
cmdline_addr = 0x9a000 - cmdline_size;
|
| 558 |
prot_addr = 0x100000;
|
| 559 |
} else {
|
| 560 |
/* High and recent kernel */
|
| 561 |
real_addr = 0x10000;
|
| 562 |
cmdline_addr = 0x20000;
|
| 563 |
prot_addr = 0x100000;
|
| 564 |
} |
| 565 |
|
| 566 |
#if 0
|
| 567 |
fprintf(stderr,
|
| 568 |
"qemu: real_addr = 0x" TARGET_FMT_plx "\n"
|
| 569 |
"qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
|
| 570 |
"qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
|
| 571 |
real_addr,
|
| 572 |
cmdline_addr,
|
| 573 |
prot_addr);
|
| 574 |
#endif
|
| 575 |
|
| 576 |
/* highest address for loading the initrd */
|
| 577 |
if (protocol >= 0x203) |
| 578 |
initrd_max = ldl_p(header+0x22c);
|
| 579 |
else
|
| 580 |
initrd_max = 0x37ffffff;
|
| 581 |
|
| 582 |
if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
|
| 583 |
initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
|
| 584 |
|
| 585 |
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); |
| 586 |
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
|
| 587 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
| 588 |
(uint8_t*)strdup(kernel_cmdline), |
| 589 |
strlen(kernel_cmdline)+1);
|
| 590 |
|
| 591 |
if (protocol >= 0x202) { |
| 592 |
stl_p(header+0x228, cmdline_addr);
|
| 593 |
} else {
|
| 594 |
stw_p(header+0x20, 0xA33F); |
| 595 |
stw_p(header+0x22, cmdline_addr-real_addr);
|
| 596 |
} |
| 597 |
|
| 598 |
/* handle vga= parameter */
|
| 599 |
vmode = strstr(kernel_cmdline, "vga=");
|
| 600 |
if (vmode) {
|
| 601 |
unsigned int video_mode; |
| 602 |
/* skip "vga=" */
|
| 603 |
vmode += 4;
|
| 604 |
if (!strncmp(vmode, "normal", 6)) { |
| 605 |
video_mode = 0xffff;
|
| 606 |
} else if (!strncmp(vmode, "ext", 3)) { |
| 607 |
video_mode = 0xfffe;
|
| 608 |
} else if (!strncmp(vmode, "ask", 3)) { |
| 609 |
video_mode = 0xfffd;
|
| 610 |
} else {
|
| 611 |
video_mode = strtol(vmode, NULL, 0); |
| 612 |
} |
| 613 |
stw_p(header+0x1fa, video_mode);
|
| 614 |
} |
| 615 |
|
| 616 |
/* loader type */
|
| 617 |
/* High nybble = B reserved for Qemu; low nybble is revision number.
|
| 618 |
If this code is substantially changed, you may want to consider
|
| 619 |
incrementing the revision. */
|
| 620 |
if (protocol >= 0x200) |
| 621 |
header[0x210] = 0xB0; |
| 622 |
|
| 623 |
/* heap */
|
| 624 |
if (protocol >= 0x201) { |
| 625 |
header[0x211] |= 0x80; /* CAN_USE_HEAP */ |
| 626 |
stw_p(header+0x224, cmdline_addr-real_addr-0x200); |
| 627 |
} |
| 628 |
|
| 629 |
/* load initrd */
|
| 630 |
if (initrd_filename) {
|
| 631 |
if (protocol < 0x200) { |
| 632 |
fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
|
| 633 |
exit(1);
|
| 634 |
} |
| 635 |
|
| 636 |
initrd_size = get_image_size(initrd_filename); |
| 637 |
initrd_addr = (initrd_max-initrd_size) & ~4095;
|
| 638 |
|
| 639 |
initrd_data = qemu_malloc(initrd_size); |
| 640 |
load_image(initrd_filename, initrd_data); |
| 641 |
|
| 642 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); |
| 643 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
| 644 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); |
| 645 |
|
| 646 |
stl_p(header+0x218, initrd_addr);
|
| 647 |
stl_p(header+0x21c, initrd_size);
|
| 648 |
} |
| 649 |
|
| 650 |
/* load kernel and setup */
|
| 651 |
setup_size = header[0x1f1];
|
| 652 |
if (setup_size == 0) |
| 653 |
setup_size = 4;
|
| 654 |
setup_size = (setup_size+1)*512; |
| 655 |
kernel_size -= setup_size; |
| 656 |
|
| 657 |
setup = qemu_malloc(setup_size); |
| 658 |
kernel = qemu_malloc(kernel_size); |
| 659 |
fseek(f, 0, SEEK_SET);
|
| 660 |
if (fread(setup, 1, setup_size, f) != setup_size) { |
| 661 |
fprintf(stderr, "fread() failed\n");
|
| 662 |
exit(1);
|
| 663 |
} |
| 664 |
if (fread(kernel, 1, kernel_size, f) != kernel_size) { |
| 665 |
fprintf(stderr, "fread() failed\n");
|
| 666 |
exit(1);
|
| 667 |
} |
| 668 |
fclose(f); |
| 669 |
memcpy(setup, header, MIN(sizeof(header), setup_size));
|
| 670 |
|
| 671 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); |
| 672 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
| 673 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); |
| 674 |
|
| 675 |
fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); |
| 676 |
fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); |
| 677 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); |
| 678 |
|
| 679 |
option_rom[nb_option_roms] = "linuxboot.bin";
|
| 680 |
nb_option_roms++; |
| 681 |
} |
| 682 |
|
| 683 |
static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
| 684 |
static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
| 685 |
static const int ide_irq[2] = { 14, 15 }; |
| 686 |
|
| 687 |
#define NE2000_NB_MAX 6 |
| 688 |
|
| 689 |
static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
| 690 |
0x280, 0x380 }; |
| 691 |
static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
| 692 |
|
| 693 |
static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
| 694 |
static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; |
| 695 |
|
| 696 |
#ifdef HAS_AUDIO
|
| 697 |
static void audio_init (PCIBus *pci_bus, qemu_irq *pic) |
| 698 |
{
|
| 699 |
struct soundhw *c;
|
| 700 |
|
| 701 |
for (c = soundhw; c->name; ++c) {
|
| 702 |
if (c->enabled) {
|
| 703 |
if (c->isa) {
|
| 704 |
c->init.init_isa(pic); |
| 705 |
} else {
|
| 706 |
if (pci_bus) {
|
| 707 |
c->init.init_pci(pci_bus); |
| 708 |
} |
| 709 |
} |
| 710 |
} |
| 711 |
} |
| 712 |
} |
| 713 |
#endif
|
| 714 |
|
| 715 |
static void pc_init_ne2k_isa(NICInfo *nd) |
| 716 |
{
|
| 717 |
static int nb_ne2k = 0; |
| 718 |
|
| 719 |
if (nb_ne2k == NE2000_NB_MAX)
|
| 720 |
return;
|
| 721 |
isa_ne2000_init(ne2000_io[nb_ne2k], |
| 722 |
ne2000_irq[nb_ne2k], nd); |
| 723 |
nb_ne2k++; |
| 724 |
} |
| 725 |
|
| 726 |
int cpu_is_bsp(CPUState *env)
|
| 727 |
{
|
| 728 |
return env->cpuid_apic_id == 0; |
| 729 |
} |
| 730 |
|
| 731 |
static CPUState *pc_new_cpu(const char *cpu_model) |
| 732 |
{
|
| 733 |
CPUState *env; |
| 734 |
|
| 735 |
env = cpu_init(cpu_model); |
| 736 |
if (!env) {
|
| 737 |
fprintf(stderr, "Unable to find x86 CPU definition\n");
|
| 738 |
exit(1);
|
| 739 |
} |
| 740 |
if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) { |
| 741 |
env->cpuid_apic_id = env->cpu_index; |
| 742 |
/* APIC reset callback resets cpu */
|
| 743 |
apic_init(env); |
| 744 |
} else {
|
| 745 |
qemu_register_reset((QEMUResetHandler*)cpu_reset, env); |
| 746 |
} |
| 747 |
return env;
|
| 748 |
} |
| 749 |
|
| 750 |
/* PC hardware initialisation */
|
| 751 |
static void pc_init1(ram_addr_t ram_size, |
| 752 |
const char *boot_device, |
| 753 |
const char *kernel_filename, |
| 754 |
const char *kernel_cmdline, |
| 755 |
const char *initrd_filename, |
| 756 |
const char *cpu_model, |
| 757 |
int pci_enabled)
|
| 758 |
{
|
| 759 |
char *filename;
|
| 760 |
int ret, linux_boot, i;
|
| 761 |
ram_addr_t ram_addr, bios_offset, option_rom_offset; |
| 762 |
ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
|
| 763 |
int bios_size, isa_bios_size;
|
| 764 |
PCIBus *pci_bus; |
| 765 |
ISADevice *isa_dev; |
| 766 |
int piix3_devfn = -1; |
| 767 |
CPUState *env; |
| 768 |
qemu_irq *cpu_irq; |
| 769 |
qemu_irq *isa_irq; |
| 770 |
qemu_irq *i8259; |
| 771 |
IsaIrqState *isa_irq_state; |
| 772 |
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
| 773 |
DriveInfo *fd[MAX_FD]; |
| 774 |
void *fw_cfg;
|
| 775 |
|
| 776 |
if (ram_size >= 0xe0000000 ) { |
| 777 |
above_4g_mem_size = ram_size - 0xe0000000;
|
| 778 |
below_4g_mem_size = 0xe0000000;
|
| 779 |
} else {
|
| 780 |
below_4g_mem_size = ram_size; |
| 781 |
} |
| 782 |
|
| 783 |
linux_boot = (kernel_filename != NULL);
|
| 784 |
|
| 785 |
/* init CPUs */
|
| 786 |
if (cpu_model == NULL) { |
| 787 |
#ifdef TARGET_X86_64
|
| 788 |
cpu_model = "qemu64";
|
| 789 |
#else
|
| 790 |
cpu_model = "qemu32";
|
| 791 |
#endif
|
| 792 |
} |
| 793 |
|
| 794 |
for (i = 0; i < smp_cpus; i++) { |
| 795 |
env = pc_new_cpu(cpu_model); |
| 796 |
} |
| 797 |
|
| 798 |
vmport_init(); |
| 799 |
|
| 800 |
/* allocate RAM */
|
| 801 |
ram_addr = qemu_ram_alloc(0xa0000);
|
| 802 |
cpu_register_physical_memory(0, 0xa0000, ram_addr); |
| 803 |
|
| 804 |
/* Allocate, even though we won't register, so we don't break the
|
| 805 |
* phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
|
| 806 |
* and some bios areas, which will be registered later
|
| 807 |
*/
|
| 808 |
ram_addr = qemu_ram_alloc(0x100000 - 0xa0000); |
| 809 |
ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
|
| 810 |
cpu_register_physical_memory(0x100000,
|
| 811 |
below_4g_mem_size - 0x100000,
|
| 812 |
ram_addr); |
| 813 |
|
| 814 |
/* above 4giga memory allocation */
|
| 815 |
if (above_4g_mem_size > 0) { |
| 816 |
#if TARGET_PHYS_ADDR_BITS == 32 |
| 817 |
hw_error("To much RAM for 32-bit physical address");
|
| 818 |
#else
|
| 819 |
ram_addr = qemu_ram_alloc(above_4g_mem_size); |
| 820 |
cpu_register_physical_memory(0x100000000ULL,
|
| 821 |
above_4g_mem_size, |
| 822 |
ram_addr); |
| 823 |
#endif
|
| 824 |
} |
| 825 |
|
| 826 |
|
| 827 |
/* BIOS load */
|
| 828 |
if (bios_name == NULL) |
| 829 |
bios_name = BIOS_FILENAME; |
| 830 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
| 831 |
if (filename) {
|
| 832 |
bios_size = get_image_size(filename); |
| 833 |
} else {
|
| 834 |
bios_size = -1;
|
| 835 |
} |
| 836 |
if (bios_size <= 0 || |
| 837 |
(bios_size % 65536) != 0) { |
| 838 |
goto bios_error;
|
| 839 |
} |
| 840 |
bios_offset = qemu_ram_alloc(bios_size); |
| 841 |
ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size)); |
| 842 |
if (ret != 0) { |
| 843 |
bios_error:
|
| 844 |
fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
|
| 845 |
exit(1);
|
| 846 |
} |
| 847 |
if (filename) {
|
| 848 |
qemu_free(filename); |
| 849 |
} |
| 850 |
/* map the last 128KB of the BIOS in ISA space */
|
| 851 |
isa_bios_size = bios_size; |
| 852 |
if (isa_bios_size > (128 * 1024)) |
| 853 |
isa_bios_size = 128 * 1024; |
| 854 |
cpu_register_physical_memory(0x100000 - isa_bios_size,
|
| 855 |
isa_bios_size, |
| 856 |
(bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); |
| 857 |
|
| 858 |
option_rom_offset = qemu_ram_alloc(PC_ROM_SIZE); |
| 859 |
cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset); |
| 860 |
|
| 861 |
/* map all the bios at the top of memory */
|
| 862 |
cpu_register_physical_memory((uint32_t)(-bios_size), |
| 863 |
bios_size, bios_offset | IO_MEM_ROM); |
| 864 |
|
| 865 |
fw_cfg = bochs_bios_init(); |
| 866 |
rom_set_fw(fw_cfg); |
| 867 |
|
| 868 |
if (linux_boot) {
|
| 869 |
load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); |
| 870 |
} |
| 871 |
|
| 872 |
for (i = 0; i < nb_option_roms; i++) { |
| 873 |
rom_add_option(option_rom[i]); |
| 874 |
} |
| 875 |
|
| 876 |
cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1); |
| 877 |
i8259 = i8259_init(cpu_irq[0]);
|
| 878 |
isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
|
| 879 |
isa_irq_state->i8259 = i8259; |
| 880 |
isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
|
| 881 |
|
| 882 |
if (pci_enabled) {
|
| 883 |
pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq); |
| 884 |
} else {
|
| 885 |
pci_bus = NULL;
|
| 886 |
isa_bus_new(NULL);
|
| 887 |
} |
| 888 |
isa_bus_irqs(isa_irq); |
| 889 |
|
| 890 |
ferr_irq = isa_reserve_irq(13);
|
| 891 |
|
| 892 |
/* init basic PC hardware */
|
| 893 |
register_ioport_write(0x80, 1, 1, ioport80_write, NULL); |
| 894 |
|
| 895 |
register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); |
| 896 |
|
| 897 |
if (cirrus_vga_enabled) {
|
| 898 |
if (pci_enabled) {
|
| 899 |
pci_cirrus_vga_init(pci_bus); |
| 900 |
} else {
|
| 901 |
isa_cirrus_vga_init(); |
| 902 |
} |
| 903 |
} else if (vmsvga_enabled) { |
| 904 |
if (pci_enabled)
|
| 905 |
pci_vmsvga_init(pci_bus); |
| 906 |
else
|
| 907 |
fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
|
| 908 |
} else if (std_vga_enabled) { |
| 909 |
if (pci_enabled) {
|
| 910 |
pci_vga_init(pci_bus, 0, 0); |
| 911 |
} else {
|
| 912 |
isa_vga_init(); |
| 913 |
} |
| 914 |
} |
| 915 |
|
| 916 |
rtc_state = rtc_init(2000);
|
| 917 |
|
| 918 |
qemu_register_boot_set(pc_boot_set, rtc_state); |
| 919 |
|
| 920 |
register_ioport_read(0x92, 1, 1, ioport92_read, NULL); |
| 921 |
register_ioport_write(0x92, 1, 1, ioport92_write, NULL); |
| 922 |
|
| 923 |
if (pci_enabled) {
|
| 924 |
isa_irq_state->ioapic = ioapic_init(); |
| 925 |
} |
| 926 |
pit = pit_init(0x40, isa_reserve_irq(0)); |
| 927 |
pcspk_init(pit); |
| 928 |
if (!no_hpet) {
|
| 929 |
hpet_init(isa_irq); |
| 930 |
} |
| 931 |
|
| 932 |
for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
| 933 |
if (serial_hds[i]) {
|
| 934 |
serial_isa_init(i, serial_hds[i]); |
| 935 |
} |
| 936 |
} |
| 937 |
|
| 938 |
for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
| 939 |
if (parallel_hds[i]) {
|
| 940 |
parallel_init(i, parallel_hds[i]); |
| 941 |
} |
| 942 |
} |
| 943 |
|
| 944 |
for(i = 0; i < nb_nics; i++) { |
| 945 |
NICInfo *nd = &nd_table[i]; |
| 946 |
|
| 947 |
if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) |
| 948 |
pc_init_ne2k_isa(nd); |
| 949 |
else
|
| 950 |
pci_nic_init_nofail(nd, "e1000", NULL); |
| 951 |
} |
| 952 |
|
| 953 |
if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
| 954 |
fprintf(stderr, "qemu: too many IDE bus\n");
|
| 955 |
exit(1);
|
| 956 |
} |
| 957 |
|
| 958 |
for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
| 959 |
hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
| 960 |
} |
| 961 |
|
| 962 |
if (pci_enabled) {
|
| 963 |
pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1);
|
| 964 |
} else {
|
| 965 |
for(i = 0; i < MAX_IDE_BUS; i++) { |
| 966 |
isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], |
| 967 |
hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
|
| 968 |
} |
| 969 |
} |
| 970 |
|
| 971 |
isa_dev = isa_create_simple("i8042");
|
| 972 |
DMA_init(0);
|
| 973 |
#ifdef HAS_AUDIO
|
| 974 |
audio_init(pci_enabled ? pci_bus : NULL, isa_irq);
|
| 975 |
#endif
|
| 976 |
|
| 977 |
for(i = 0; i < MAX_FD; i++) { |
| 978 |
fd[i] = drive_get(IF_FLOPPY, 0, i);
|
| 979 |
} |
| 980 |
floppy_controller = fdctrl_init_isa(fd); |
| 981 |
|
| 982 |
cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd); |
| 983 |
|
| 984 |
if (pci_enabled && usb_enabled) {
|
| 985 |
usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
|
| 986 |
} |
| 987 |
|
| 988 |
if (pci_enabled && acpi_enabled) {
|
| 989 |
uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */ |
| 990 |
i2c_bus *smbus; |
| 991 |
|
| 992 |
/* TODO: Populate SPD eeprom data. */
|
| 993 |
smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, |
| 994 |
isa_reserve_irq(9));
|
| 995 |
for (i = 0; i < 8; i++) { |
| 996 |
DeviceState *eeprom; |
| 997 |
eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
|
| 998 |
qdev_prop_set_uint8(eeprom, "address", 0x50 + i); |
| 999 |
qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256)); |
| 1000 |
qdev_init_nofail(eeprom); |
| 1001 |
} |
| 1002 |
piix4_acpi_system_hot_add_init(pci_bus); |
| 1003 |
} |
| 1004 |
|
| 1005 |
if (i440fx_state) {
|
| 1006 |
i440fx_init_memory_mappings(i440fx_state); |
| 1007 |
} |
| 1008 |
|
| 1009 |
if (pci_enabled) {
|
| 1010 |
int max_bus;
|
| 1011 |
int bus;
|
| 1012 |
|
| 1013 |
max_bus = drive_get_max_bus(IF_SCSI); |
| 1014 |
for (bus = 0; bus <= max_bus; bus++) { |
| 1015 |
pci_create_simple(pci_bus, -1, "lsi53c895a"); |
| 1016 |
} |
| 1017 |
} |
| 1018 |
} |
| 1019 |
|
| 1020 |
static void pc_init_pci(ram_addr_t ram_size, |
| 1021 |
const char *boot_device, |
| 1022 |
const char *kernel_filename, |
| 1023 |
const char *kernel_cmdline, |
| 1024 |
const char *initrd_filename, |
| 1025 |
const char *cpu_model) |
| 1026 |
{
|
| 1027 |
pc_init1(ram_size, boot_device, |
| 1028 |
kernel_filename, kernel_cmdline, |
| 1029 |
initrd_filename, cpu_model, 1);
|
| 1030 |
} |
| 1031 |
|
| 1032 |
static void pc_init_isa(ram_addr_t ram_size, |
| 1033 |
const char *boot_device, |
| 1034 |
const char *kernel_filename, |
| 1035 |
const char *kernel_cmdline, |
| 1036 |
const char *initrd_filename, |
| 1037 |
const char *cpu_model) |
| 1038 |
{
|
| 1039 |
if (cpu_model == NULL) |
| 1040 |
cpu_model = "486";
|
| 1041 |
pc_init1(ram_size, boot_device, |
| 1042 |
kernel_filename, kernel_cmdline, |
| 1043 |
initrd_filename, cpu_model, 0);
|
| 1044 |
} |
| 1045 |
|
| 1046 |
/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
|
| 1047 |
BIOS will read it and start S3 resume at POST Entry */
|
| 1048 |
void cmos_set_s3_resume(void) |
| 1049 |
{
|
| 1050 |
if (rtc_state)
|
| 1051 |
rtc_set_memory(rtc_state, 0xF, 0xFE); |
| 1052 |
} |
| 1053 |
|
| 1054 |
static QEMUMachine pc_machine = {
|
| 1055 |
.name = "pc-0.13",
|
| 1056 |
.alias = "pc",
|
| 1057 |
.desc = "Standard PC",
|
| 1058 |
.init = pc_init_pci, |
| 1059 |
.max_cpus = 255,
|
| 1060 |
.is_default = 1,
|
| 1061 |
}; |
| 1062 |
|
| 1063 |
static QEMUMachine pc_machine_v0_12 = {
|
| 1064 |
.name = "pc-0.12",
|
| 1065 |
.desc = "Standard PC",
|
| 1066 |
.init = pc_init_pci, |
| 1067 |
.max_cpus = 255,
|
| 1068 |
.compat_props = (GlobalProperty[]) {
|
| 1069 |
{
|
| 1070 |
.driver = "virtio-serial-pci",
|
| 1071 |
.property = "max_nr_ports",
|
| 1072 |
.value = stringify(1),
|
| 1073 |
},{
|
| 1074 |
.driver = "virtio-serial-pci",
|
| 1075 |
.property = "vectors",
|
| 1076 |
.value = stringify(0),
|
| 1077 |
}, |
| 1078 |
{ /* end of list */ }
|
| 1079 |
} |
| 1080 |
}; |
| 1081 |
|
| 1082 |
static QEMUMachine pc_machine_v0_11 = {
|
| 1083 |
.name = "pc-0.11",
|
| 1084 |
.desc = "Standard PC, qemu 0.11",
|
| 1085 |
.init = pc_init_pci, |
| 1086 |
.max_cpus = 255,
|
| 1087 |
.compat_props = (GlobalProperty[]) {
|
| 1088 |
{
|
| 1089 |
.driver = "virtio-blk-pci",
|
| 1090 |
.property = "vectors",
|
| 1091 |
.value = stringify(0),
|
| 1092 |
},{
|
| 1093 |
.driver = "virtio-serial-pci",
|
| 1094 |
.property = "max_nr_ports",
|
| 1095 |
.value = stringify(1),
|
| 1096 |
},{
|
| 1097 |
.driver = "virtio-serial-pci",
|
| 1098 |
.property = "vectors",
|
| 1099 |
.value = stringify(0),
|
| 1100 |
},{
|
| 1101 |
.driver = "ide-drive",
|
| 1102 |
.property = "ver",
|
| 1103 |
.value = "0.11",
|
| 1104 |
},{
|
| 1105 |
.driver = "scsi-disk",
|
| 1106 |
.property = "ver",
|
| 1107 |
.value = "0.11",
|
| 1108 |
},{
|
| 1109 |
.driver = "PCI",
|
| 1110 |
.property = "rombar",
|
| 1111 |
.value = stringify(0),
|
| 1112 |
}, |
| 1113 |
{ /* end of list */ }
|
| 1114 |
} |
| 1115 |
}; |
| 1116 |
|
| 1117 |
static QEMUMachine pc_machine_v0_10 = {
|
| 1118 |
.name = "pc-0.10",
|
| 1119 |
.desc = "Standard PC, qemu 0.10",
|
| 1120 |
.init = pc_init_pci, |
| 1121 |
.max_cpus = 255,
|
| 1122 |
.compat_props = (GlobalProperty[]) {
|
| 1123 |
{
|
| 1124 |
.driver = "virtio-blk-pci",
|
| 1125 |
.property = "class",
|
| 1126 |
.value = stringify(PCI_CLASS_STORAGE_OTHER), |
| 1127 |
},{
|
| 1128 |
.driver = "virtio-serial-pci",
|
| 1129 |
.property = "class",
|
| 1130 |
.value = stringify(PCI_CLASS_DISPLAY_OTHER), |
| 1131 |
},{
|
| 1132 |
.driver = "virtio-serial-pci",
|
| 1133 |
.property = "max_nr_ports",
|
| 1134 |
.value = stringify(1),
|
| 1135 |
},{
|
| 1136 |
.driver = "virtio-serial-pci",
|
| 1137 |
.property = "vectors",
|
| 1138 |
.value = stringify(0),
|
| 1139 |
},{
|
| 1140 |
.driver = "virtio-net-pci",
|
| 1141 |
.property = "vectors",
|
| 1142 |
.value = stringify(0),
|
| 1143 |
},{
|
| 1144 |
.driver = "virtio-blk-pci",
|
| 1145 |
.property = "vectors",
|
| 1146 |
.value = stringify(0),
|
| 1147 |
},{
|
| 1148 |
.driver = "ide-drive",
|
| 1149 |
.property = "ver",
|
| 1150 |
.value = "0.10",
|
| 1151 |
},{
|
| 1152 |
.driver = "scsi-disk",
|
| 1153 |
.property = "ver",
|
| 1154 |
.value = "0.10",
|
| 1155 |
},{
|
| 1156 |
.driver = "PCI",
|
| 1157 |
.property = "rombar",
|
| 1158 |
.value = stringify(0),
|
| 1159 |
}, |
| 1160 |
{ /* end of list */ }
|
| 1161 |
}, |
| 1162 |
}; |
| 1163 |
|
| 1164 |
static QEMUMachine isapc_machine = {
|
| 1165 |
.name = "isapc",
|
| 1166 |
.desc = "ISA-only PC",
|
| 1167 |
.init = pc_init_isa, |
| 1168 |
.max_cpus = 1,
|
| 1169 |
}; |
| 1170 |
|
| 1171 |
static void pc_machine_init(void) |
| 1172 |
{
|
| 1173 |
qemu_register_machine(&pc_machine); |
| 1174 |
qemu_register_machine(&pc_machine_v0_12); |
| 1175 |
qemu_register_machine(&pc_machine_v0_11); |
| 1176 |
qemu_register_machine(&pc_machine_v0_10); |
| 1177 |
qemu_register_machine(&isapc_machine); |
| 1178 |
} |
| 1179 |
|
| 1180 |
machine_init(pc_machine_init); |