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/*
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 *  i386 CPUID helper functions
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 *
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include "cpu.h"
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#include "kvm.h"
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#include "qemu-option.h"
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#include "qemu-config.h"
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/* feature flags taken from "Intel Processor Identification and the CPUID
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 * Instruction" and AMD's "CPUID Specification".  In cases of disagreement
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 * between feature naming conventions, aliases may be added.
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 */
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static const char *feature_name[] = {
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    "fpu", "vme", "de", "pse",
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    "tsc", "msr", "pae", "mce",
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    "cx8", "apic", NULL, "sep",
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    "mtrr", "pge", "mca", "cmov",
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    "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
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    NULL, "ds" /* Intel dts */, "acpi", "mmx",
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    "fxsr", "sse", "sse2", "ss",
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    "ht" /* Intel htt */, "tm", "ia64", "pbe",
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};
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static const char *ext_feature_name[] = {
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    "pni|sse3" /* Intel,AMD sse3 */, "pclmuldq", "dtes64", "monitor",
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    "ds_cpl", "vmx", "smx", "est",
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    "tm2", "ssse3", "cid", NULL,
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    "fma", "cx16", "xtpr", "pdcm",
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    NULL, NULL, "dca", "sse4.1|sse4_1",
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    "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
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    NULL, "aes", "xsave", "osxsave",
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    "avx", NULL, NULL, "hypervisor",
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};
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static const char *ext2_feature_name[] = {
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    "fpu", "vme", "de", "pse",
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    "tsc", "msr", "pae", "mce",
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    "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall",
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    "mtrr", "pge", "mca", "cmov",
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    "pat", "pse36", NULL, NULL /* Linux mp */,
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    "nx" /* Intel xd */, NULL, "mmxext", "mmx",
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    "fxsr", "fxsr_opt" /* AMD ffxsr */, "pdpe1gb" /* AMD Page1GB */, "rdtscp",
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    NULL, "lm" /* Intel 64 */, "3dnowext", "3dnow",
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};
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static const char *ext3_feature_name[] = {
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    "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
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    "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
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    "3dnowprefetch", "osvw", "ibs", "xop",
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    "skinit", "wdt", NULL, NULL,
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    "fma4", NULL, "cvt16", "nodeid_msr",
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    NULL, NULL, NULL, NULL,
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    NULL, NULL, NULL, NULL,
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    NULL, NULL, NULL, NULL,
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};
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static const char *kvm_feature_name[] = {
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    "kvmclock", "kvm_nopiodelay", "kvm_mmu", NULL, NULL, NULL, NULL, NULL,
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    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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};
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/* collects per-function cpuid data
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 */
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typedef struct model_features_t {
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    uint32_t *guest_feat;
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    uint32_t *host_feat;
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    uint32_t check_feat;
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    const char **flag_names;
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    uint32_t cpuid;
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    } model_features_t;
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int check_cpuid = 0;
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int enforce_cpuid = 0;
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static void host_cpuid(uint32_t function, uint32_t count,
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                       uint32_t *eax, uint32_t *ebx,
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                       uint32_t *ecx, uint32_t *edx)
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{
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#if defined(CONFIG_KVM)
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    uint32_t vec[4];
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#ifdef __x86_64__
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    asm volatile("cpuid"
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                 : "=a"(vec[0]), "=b"(vec[1]),
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                   "=c"(vec[2]), "=d"(vec[3])
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                 : "0"(function), "c"(count) : "cc");
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#else
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    asm volatile("pusha \n\t"
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                 "cpuid \n\t"
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                 "mov %%eax, 0(%2) \n\t"
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                 "mov %%ebx, 4(%2) \n\t"
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                 "mov %%ecx, 8(%2) \n\t"
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                 "mov %%edx, 12(%2) \n\t"
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                 "popa"
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                 : : "a"(function), "c"(count), "S"(vec)
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                 : "memory", "cc");
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#endif
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    if (eax)
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        *eax = vec[0];
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    if (ebx)
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        *ebx = vec[1];
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    if (ecx)
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        *ecx = vec[2];
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    if (edx)
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        *edx = vec[3];
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#endif
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}
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#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
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/* general substring compare of *[s1..e1) and *[s2..e2).  sx is start of
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 * a substring.  ex if !NULL points to the first char after a substring,
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 * otherwise the string is assumed to sized by a terminating nul.
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 * Return lexical ordering of *s1:*s2.
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 */
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static int sstrcmp(const char *s1, const char *e1, const char *s2,
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    const char *e2)
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{
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    for (;;) {
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        if (!*s1 || !*s2 || *s1 != *s2)
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            return (*s1 - *s2);
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        ++s1, ++s2;
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        if (s1 == e1 && s2 == e2)
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            return (0);
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        else if (s1 == e1)
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            return (*s2);
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        else if (s2 == e2)
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            return (*s1);
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    }
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}
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/* compare *[s..e) to *altstr.  *altstr may be a simple string or multiple
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 * '|' delimited (possibly empty) strings in which case search for a match
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 * within the alternatives proceeds left to right.  Return 0 for success,
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 * non-zero otherwise.
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 */
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static int altcmp(const char *s, const char *e, const char *altstr)
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{
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    const char *p, *q;
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    for (q = p = altstr; ; ) {
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        while (*p && *p != '|')
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            ++p;
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        if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
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            return (0);
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        if (!*p)
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            return (1);
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        else
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            q = ++p;
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    }
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}
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/* search featureset for flag *[s..e), if found set corresponding bit in
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 * *pval and return success, otherwise return zero
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 */
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static int lookup_feature(uint32_t *pval, const char *s, const char *e,
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    const char **featureset)
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{
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    uint32_t mask;
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    const char **ppc;
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    for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc)
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        if (*ppc && !altcmp(s, e, *ppc)) {
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            *pval |= mask;
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            break;
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        }
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    return (mask ? 1 : 0);
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}
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static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
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                                    uint32_t *ext_features,
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                                    uint32_t *ext2_features,
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                                    uint32_t *ext3_features,
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                                    uint32_t *kvm_features)
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{
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    if (!lookup_feature(features, flagname, NULL, feature_name) &&
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        !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
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        !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
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        !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
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        !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name))
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            fprintf(stderr, "CPU feature %s not found\n", flagname);
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}
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typedef struct x86_def_t {
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    struct x86_def_t *next;
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    const char *name;
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    uint32_t level;
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    uint32_t vendor1, vendor2, vendor3;
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    int family;
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    int model;
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    int stepping;
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    uint32_t features, ext_features, ext2_features, ext3_features, kvm_features;
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    uint32_t xlevel;
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    char model_id[48];
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    int vendor_override;
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    uint32_t flags;
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} x86_def_t;
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#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
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#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
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          CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
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#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
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          CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
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          CPUID_PSE36 | CPUID_FXSR)
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#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
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#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
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          CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
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          CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
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          CPUID_PAE | CPUID_SEP | CPUID_APIC)
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#define EXT2_FEATURE_MASK 0x0183F3FF
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#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
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          CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
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          CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
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          CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
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          CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
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          /* partly implemented:
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          CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
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          CPUID_PSE36 (needed for Solaris) */
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          /* missing:
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          CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
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#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
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          CPUID_EXT_CX16 | CPUID_EXT_POPCNT | CPUID_EXT_XSAVE | \
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          CPUID_EXT_HYPERVISOR)
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          /* missing:
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          CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
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          CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM */
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#define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \
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          CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
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          CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
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          /* missing:
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          CPUID_EXT2_PDPE1GB */
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#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
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          CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
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/* maintains list of cpu model definitions
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 */
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static x86_def_t *x86_defs = {NULL};
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/* built-in cpu model definitions (deprecated)
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 */
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static x86_def_t builtin_x86_defs[] = {
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    {
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        .name = "qemu64",
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        .level = 4,
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        .vendor1 = CPUID_VENDOR_AMD_1,
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        .vendor2 = CPUID_VENDOR_AMD_2,
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        .vendor3 = CPUID_VENDOR_AMD_3,
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        .family = 6,
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        .model = 2,
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        .stepping = 3,
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        .features = PPRO_FEATURES |
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            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
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            CPUID_PSE36,
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        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
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        .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
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            CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
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        .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
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            CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
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        .xlevel = 0x8000000A,
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        .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
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    },
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    {
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        .name = "phenom",
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        .level = 5,
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        .vendor1 = CPUID_VENDOR_AMD_1,
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        .vendor2 = CPUID_VENDOR_AMD_2,
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        .vendor3 = CPUID_VENDOR_AMD_3,
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        .family = 16,
291 c6dc6f63 Andre Przywara
        .model = 2,
292 c6dc6f63 Andre Przywara
        .stepping = 3,
293 c6dc6f63 Andre Przywara
        .features = PPRO_FEATURES |
294 c6dc6f63 Andre Przywara
            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
295 8560efed Aurelien Jarno
            CPUID_PSE36 | CPUID_VME | CPUID_HT,
296 c6dc6f63 Andre Przywara
        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
297 c6dc6f63 Andre Przywara
            CPUID_EXT_POPCNT,
298 42673936 Andre Przywara
        .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
299 c6dc6f63 Andre Przywara
            CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
300 c6dc6f63 Andre Przywara
            CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
301 8560efed Aurelien Jarno
            CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
302 c6dc6f63 Andre Przywara
        /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
303 c6dc6f63 Andre Przywara
                    CPUID_EXT3_CR8LEG,
304 c6dc6f63 Andre Przywara
                    CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
305 c6dc6f63 Andre Przywara
                    CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
306 c6dc6f63 Andre Przywara
        .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
307 c6dc6f63 Andre Przywara
            CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
308 c6dc6f63 Andre Przywara
        .xlevel = 0x8000001A,
309 c6dc6f63 Andre Przywara
        .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
310 c6dc6f63 Andre Przywara
    },
311 c6dc6f63 Andre Przywara
    {
312 c6dc6f63 Andre Przywara
        .name = "core2duo",
313 c6dc6f63 Andre Przywara
        .level = 10,
314 c6dc6f63 Andre Przywara
        .family = 6,
315 c6dc6f63 Andre Przywara
        .model = 15,
316 c6dc6f63 Andre Przywara
        .stepping = 11,
317 c6dc6f63 Andre Przywara
        .features = PPRO_FEATURES |
318 c6dc6f63 Andre Przywara
            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
319 8560efed Aurelien Jarno
            CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
320 8560efed Aurelien Jarno
            CPUID_HT | CPUID_TM | CPUID_PBE,
321 8560efed Aurelien Jarno
        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
322 8560efed Aurelien Jarno
            CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
323 8560efed Aurelien Jarno
            CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
324 c6dc6f63 Andre Przywara
        .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
325 c6dc6f63 Andre Przywara
        .ext3_features = CPUID_EXT3_LAHF_LM,
326 c6dc6f63 Andre Przywara
        .xlevel = 0x80000008,
327 c6dc6f63 Andre Przywara
        .model_id = "Intel(R) Core(TM)2 Duo CPU     T7700  @ 2.40GHz",
328 c6dc6f63 Andre Przywara
    },
329 c6dc6f63 Andre Przywara
    {
330 c6dc6f63 Andre Przywara
        .name = "kvm64",
331 c6dc6f63 Andre Przywara
        .level = 5,
332 c6dc6f63 Andre Przywara
        .vendor1 = CPUID_VENDOR_INTEL_1,
333 c6dc6f63 Andre Przywara
        .vendor2 = CPUID_VENDOR_INTEL_2,
334 c6dc6f63 Andre Przywara
        .vendor3 = CPUID_VENDOR_INTEL_3,
335 c6dc6f63 Andre Przywara
        .family = 15,
336 c6dc6f63 Andre Przywara
        .model = 6,
337 c6dc6f63 Andre Przywara
        .stepping = 1,
338 c6dc6f63 Andre Przywara
        /* Missing: CPUID_VME, CPUID_HT */
339 c6dc6f63 Andre Przywara
        .features = PPRO_FEATURES |
340 c6dc6f63 Andre Przywara
            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
341 c6dc6f63 Andre Przywara
            CPUID_PSE36,
342 c6dc6f63 Andre Przywara
        /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
343 c6dc6f63 Andre Przywara
        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
344 c6dc6f63 Andre Przywara
        /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
345 42673936 Andre Przywara
        .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
346 c6dc6f63 Andre Przywara
            CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
347 c6dc6f63 Andre Przywara
        /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
348 c6dc6f63 Andre Przywara
                    CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
349 c6dc6f63 Andre Przywara
                    CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
350 c6dc6f63 Andre Przywara
                    CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
351 c6dc6f63 Andre Przywara
        .ext3_features = 0,
352 c6dc6f63 Andre Przywara
        .xlevel = 0x80000008,
353 c6dc6f63 Andre Przywara
        .model_id = "Common KVM processor"
354 c6dc6f63 Andre Przywara
    },
355 c6dc6f63 Andre Przywara
    {
356 c6dc6f63 Andre Przywara
        .name = "qemu32",
357 c6dc6f63 Andre Przywara
        .level = 4,
358 c6dc6f63 Andre Przywara
        .family = 6,
359 c6dc6f63 Andre Przywara
        .model = 3,
360 c6dc6f63 Andre Przywara
        .stepping = 3,
361 c6dc6f63 Andre Przywara
        .features = PPRO_FEATURES,
362 c6dc6f63 Andre Przywara
        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
363 58012d66 Andre Przywara
        .xlevel = 0x80000004,
364 c6dc6f63 Andre Przywara
        .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
365 c6dc6f63 Andre Przywara
    },
366 c6dc6f63 Andre Przywara
    {
367 c6dc6f63 Andre Przywara
        .name = "coreduo",
368 c6dc6f63 Andre Przywara
        .level = 10,
369 c6dc6f63 Andre Przywara
        .family = 6,
370 c6dc6f63 Andre Przywara
        .model = 14,
371 c6dc6f63 Andre Przywara
        .stepping = 8,
372 c6dc6f63 Andre Przywara
        .features = PPRO_FEATURES | CPUID_VME |
373 8560efed Aurelien Jarno
            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
374 8560efed Aurelien Jarno
            CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
375 8560efed Aurelien Jarno
        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
376 8560efed Aurelien Jarno
            CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
377 c6dc6f63 Andre Przywara
        .ext2_features = CPUID_EXT2_NX,
378 c6dc6f63 Andre Przywara
        .xlevel = 0x80000008,
379 c6dc6f63 Andre Przywara
        .model_id = "Genuine Intel(R) CPU           T2600  @ 2.16GHz",
380 c6dc6f63 Andre Przywara
    },
381 c6dc6f63 Andre Przywara
    {
382 c6dc6f63 Andre Przywara
        .name = "486",
383 58012d66 Andre Przywara
        .level = 1,
384 c6dc6f63 Andre Przywara
        .family = 4,
385 c6dc6f63 Andre Przywara
        .model = 0,
386 c6dc6f63 Andre Przywara
        .stepping = 0,
387 c6dc6f63 Andre Przywara
        .features = I486_FEATURES,
388 c6dc6f63 Andre Przywara
        .xlevel = 0,
389 c6dc6f63 Andre Przywara
    },
390 c6dc6f63 Andre Przywara
    {
391 c6dc6f63 Andre Przywara
        .name = "pentium",
392 c6dc6f63 Andre Przywara
        .level = 1,
393 c6dc6f63 Andre Przywara
        .family = 5,
394 c6dc6f63 Andre Przywara
        .model = 4,
395 c6dc6f63 Andre Przywara
        .stepping = 3,
396 c6dc6f63 Andre Przywara
        .features = PENTIUM_FEATURES,
397 c6dc6f63 Andre Przywara
        .xlevel = 0,
398 c6dc6f63 Andre Przywara
    },
399 c6dc6f63 Andre Przywara
    {
400 c6dc6f63 Andre Przywara
        .name = "pentium2",
401 c6dc6f63 Andre Przywara
        .level = 2,
402 c6dc6f63 Andre Przywara
        .family = 6,
403 c6dc6f63 Andre Przywara
        .model = 5,
404 c6dc6f63 Andre Przywara
        .stepping = 2,
405 c6dc6f63 Andre Przywara
        .features = PENTIUM2_FEATURES,
406 c6dc6f63 Andre Przywara
        .xlevel = 0,
407 c6dc6f63 Andre Przywara
    },
408 c6dc6f63 Andre Przywara
    {
409 c6dc6f63 Andre Przywara
        .name = "pentium3",
410 c6dc6f63 Andre Przywara
        .level = 2,
411 c6dc6f63 Andre Przywara
        .family = 6,
412 c6dc6f63 Andre Przywara
        .model = 7,
413 c6dc6f63 Andre Przywara
        .stepping = 3,
414 c6dc6f63 Andre Przywara
        .features = PENTIUM3_FEATURES,
415 c6dc6f63 Andre Przywara
        .xlevel = 0,
416 c6dc6f63 Andre Przywara
    },
417 c6dc6f63 Andre Przywara
    {
418 c6dc6f63 Andre Przywara
        .name = "athlon",
419 c6dc6f63 Andre Przywara
        .level = 2,
420 c6dc6f63 Andre Przywara
        .vendor1 = CPUID_VENDOR_AMD_1,
421 c6dc6f63 Andre Przywara
        .vendor2 = CPUID_VENDOR_AMD_2,
422 c6dc6f63 Andre Przywara
        .vendor3 = CPUID_VENDOR_AMD_3,
423 c6dc6f63 Andre Przywara
        .family = 6,
424 c6dc6f63 Andre Przywara
        .model = 2,
425 c6dc6f63 Andre Przywara
        .stepping = 3,
426 c6dc6f63 Andre Przywara
        .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,
427 42673936 Andre Przywara
        .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
428 c6dc6f63 Andre Przywara
        .xlevel = 0x80000008,
429 c6dc6f63 Andre Przywara
        /* XXX: put another string ? */
430 c6dc6f63 Andre Przywara
        .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
431 c6dc6f63 Andre Przywara
    },
432 c6dc6f63 Andre Przywara
    {
433 c6dc6f63 Andre Przywara
        .name = "n270",
434 c6dc6f63 Andre Przywara
        /* original is on level 10 */
435 c6dc6f63 Andre Przywara
        .level = 5,
436 c6dc6f63 Andre Przywara
        .family = 6,
437 c6dc6f63 Andre Przywara
        .model = 28,
438 c6dc6f63 Andre Przywara
        .stepping = 2,
439 c6dc6f63 Andre Przywara
        .features = PPRO_FEATURES |
440 8560efed Aurelien Jarno
            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
441 8560efed Aurelien Jarno
            CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
442 c6dc6f63 Andre Przywara
            /* Some CPUs got no CPUID_SEP */
443 8560efed Aurelien Jarno
        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
444 8560efed Aurelien Jarno
            CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
445 42673936 Andre Przywara
        .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_NX,
446 8560efed Aurelien Jarno
        .ext3_features = CPUID_EXT3_LAHF_LM,
447 c6dc6f63 Andre Przywara
        .xlevel = 0x8000000A,
448 c6dc6f63 Andre Przywara
        .model_id = "Intel(R) Atom(TM) CPU N270   @ 1.60GHz",
449 c6dc6f63 Andre Przywara
    },
450 c6dc6f63 Andre Przywara
};
451 c6dc6f63 Andre Przywara
452 c6dc6f63 Andre Przywara
static int cpu_x86_fill_model_id(char *str)
453 c6dc6f63 Andre Przywara
{
454 c6dc6f63 Andre Przywara
    uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
455 c6dc6f63 Andre Przywara
    int i;
456 c6dc6f63 Andre Przywara
457 c6dc6f63 Andre Przywara
    for (i = 0; i < 3; i++) {
458 c6dc6f63 Andre Przywara
        host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
459 c6dc6f63 Andre Przywara
        memcpy(str + i * 16 +  0, &eax, 4);
460 c6dc6f63 Andre Przywara
        memcpy(str + i * 16 +  4, &ebx, 4);
461 c6dc6f63 Andre Przywara
        memcpy(str + i * 16 +  8, &ecx, 4);
462 c6dc6f63 Andre Przywara
        memcpy(str + i * 16 + 12, &edx, 4);
463 c6dc6f63 Andre Przywara
    }
464 c6dc6f63 Andre Przywara
    return 0;
465 c6dc6f63 Andre Przywara
}
466 c6dc6f63 Andre Przywara
467 c6dc6f63 Andre Przywara
static int cpu_x86_fill_host(x86_def_t *x86_cpu_def)
468 c6dc6f63 Andre Przywara
{
469 c6dc6f63 Andre Przywara
    uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
470 c6dc6f63 Andre Przywara
471 c6dc6f63 Andre Przywara
    x86_cpu_def->name = "host";
472 c6dc6f63 Andre Przywara
    host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
473 c6dc6f63 Andre Przywara
    x86_cpu_def->level = eax;
474 c6dc6f63 Andre Przywara
    x86_cpu_def->vendor1 = ebx;
475 c6dc6f63 Andre Przywara
    x86_cpu_def->vendor2 = edx;
476 c6dc6f63 Andre Przywara
    x86_cpu_def->vendor3 = ecx;
477 c6dc6f63 Andre Przywara
478 c6dc6f63 Andre Przywara
    host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
479 c6dc6f63 Andre Przywara
    x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
480 c6dc6f63 Andre Przywara
    x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
481 c6dc6f63 Andre Przywara
    x86_cpu_def->stepping = eax & 0x0F;
482 c6dc6f63 Andre Przywara
    x86_cpu_def->ext_features = ecx;
483 c6dc6f63 Andre Przywara
    x86_cpu_def->features = edx;
484 c6dc6f63 Andre Przywara
485 c6dc6f63 Andre Przywara
    host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
486 c6dc6f63 Andre Przywara
    x86_cpu_def->xlevel = eax;
487 c6dc6f63 Andre Przywara
488 c6dc6f63 Andre Przywara
    host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
489 c6dc6f63 Andre Przywara
    x86_cpu_def->ext2_features = edx;
490 c6dc6f63 Andre Przywara
    x86_cpu_def->ext3_features = ecx;
491 c6dc6f63 Andre Przywara
    cpu_x86_fill_model_id(x86_cpu_def->model_id);
492 c6dc6f63 Andre Przywara
    x86_cpu_def->vendor_override = 0;
493 c6dc6f63 Andre Przywara
494 c6dc6f63 Andre Przywara
    return 0;
495 c6dc6f63 Andre Przywara
}
496 c6dc6f63 Andre Przywara
497 c6dc6f63 Andre Przywara
static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
498 c6dc6f63 Andre Przywara
{
499 c6dc6f63 Andre Przywara
    int i;
500 c6dc6f63 Andre Przywara
501 c6dc6f63 Andre Przywara
    for (i = 0; i < 32; ++i)
502 c6dc6f63 Andre Przywara
        if (1 << i & mask) {
503 c6dc6f63 Andre Przywara
            fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
504 c6dc6f63 Andre Przywara
                " flag '%s' [0x%08x]\n",
505 c6dc6f63 Andre Przywara
                f->cpuid >> 16, f->cpuid & 0xffff,
506 c6dc6f63 Andre Przywara
                f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
507 c6dc6f63 Andre Przywara
            break;
508 c6dc6f63 Andre Przywara
        }
509 c6dc6f63 Andre Przywara
    return 0;
510 c6dc6f63 Andre Przywara
}
511 c6dc6f63 Andre Przywara
512 c6dc6f63 Andre Przywara
/* best effort attempt to inform user requested cpu flags aren't making
513 c6dc6f63 Andre Przywara
 * their way to the guest.  Note: ft[].check_feat ideally should be
514 c6dc6f63 Andre Przywara
 * specified via a guest_def field to suppress report of extraneous flags.
515 c6dc6f63 Andre Przywara
 */
516 c6dc6f63 Andre Przywara
static int check_features_against_host(x86_def_t *guest_def)
517 c6dc6f63 Andre Przywara
{
518 c6dc6f63 Andre Przywara
    x86_def_t host_def;
519 c6dc6f63 Andre Przywara
    uint32_t mask;
520 c6dc6f63 Andre Przywara
    int rv, i;
521 c6dc6f63 Andre Przywara
    struct model_features_t ft[] = {
522 c6dc6f63 Andre Przywara
        {&guest_def->features, &host_def.features,
523 c6dc6f63 Andre Przywara
            ~0, feature_name, 0x00000000},
524 c6dc6f63 Andre Przywara
        {&guest_def->ext_features, &host_def.ext_features,
525 c6dc6f63 Andre Przywara
            ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
526 c6dc6f63 Andre Przywara
        {&guest_def->ext2_features, &host_def.ext2_features,
527 c6dc6f63 Andre Przywara
            ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
528 c6dc6f63 Andre Przywara
        {&guest_def->ext3_features, &host_def.ext3_features,
529 c6dc6f63 Andre Przywara
            ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
530 c6dc6f63 Andre Przywara
531 c6dc6f63 Andre Przywara
    cpu_x86_fill_host(&host_def);
532 c6dc6f63 Andre Przywara
    for (rv = 0, i = 0; i < sizeof (ft) / sizeof (ft[0]); ++i)
533 c6dc6f63 Andre Przywara
        for (mask = 1; mask; mask <<= 1)
534 c6dc6f63 Andre Przywara
            if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
535 c6dc6f63 Andre Przywara
                !(*ft[i].host_feat & mask)) {
536 c6dc6f63 Andre Przywara
                    unavailable_host_feature(&ft[i], mask);
537 c6dc6f63 Andre Przywara
                    rv = 1;
538 c6dc6f63 Andre Przywara
                }
539 c6dc6f63 Andre Przywara
    return rv;
540 c6dc6f63 Andre Przywara
}
541 c6dc6f63 Andre Przywara
542 c6dc6f63 Andre Przywara
static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
543 c6dc6f63 Andre Przywara
{
544 c6dc6f63 Andre Przywara
    unsigned int i;
545 c6dc6f63 Andre Przywara
    x86_def_t *def;
546 c6dc6f63 Andre Przywara
547 c6dc6f63 Andre Przywara
    char *s = strdup(cpu_model);
548 c6dc6f63 Andre Przywara
    char *featurestr, *name = strtok(s, ",");
549 c6dc6f63 Andre Przywara
    uint32_t plus_features = 0, plus_ext_features = 0, plus_ext2_features = 0, plus_ext3_features = 0, plus_kvm_features = 0;
550 c6dc6f63 Andre Przywara
    uint32_t minus_features = 0, minus_ext_features = 0, minus_ext2_features = 0, minus_ext3_features = 0, minus_kvm_features = 0;
551 c6dc6f63 Andre Przywara
    uint32_t numvalue;
552 c6dc6f63 Andre Przywara
553 c6dc6f63 Andre Przywara
    for (def = x86_defs; def; def = def->next)
554 c6dc6f63 Andre Przywara
        if (!strcmp(name, def->name))
555 c6dc6f63 Andre Przywara
            break;
556 c6dc6f63 Andre Przywara
    if (kvm_enabled() && strcmp(name, "host") == 0) {
557 c6dc6f63 Andre Przywara
        cpu_x86_fill_host(x86_cpu_def);
558 c6dc6f63 Andre Przywara
    } else if (!def) {
559 c6dc6f63 Andre Przywara
        goto error;
560 c6dc6f63 Andre Przywara
    } else {
561 c6dc6f63 Andre Przywara
        memcpy(x86_cpu_def, def, sizeof(*def));
562 c6dc6f63 Andre Przywara
    }
563 c6dc6f63 Andre Przywara
564 c6dc6f63 Andre Przywara
    plus_kvm_features = ~0; /* not supported bits will be filtered out later */
565 c6dc6f63 Andre Przywara
566 c6dc6f63 Andre Przywara
    add_flagname_to_bitmaps("hypervisor", &plus_features,
567 c6dc6f63 Andre Przywara
        &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
568 c6dc6f63 Andre Przywara
        &plus_kvm_features);
569 c6dc6f63 Andre Przywara
570 c6dc6f63 Andre Przywara
    featurestr = strtok(NULL, ",");
571 c6dc6f63 Andre Przywara
572 c6dc6f63 Andre Przywara
    while (featurestr) {
573 c6dc6f63 Andre Przywara
        char *val;
574 c6dc6f63 Andre Przywara
        if (featurestr[0] == '+') {
575 c6dc6f63 Andre Przywara
            add_flagname_to_bitmaps(featurestr + 1, &plus_features, &plus_ext_features, &plus_ext2_features, &plus_ext3_features, &plus_kvm_features);
576 c6dc6f63 Andre Przywara
        } else if (featurestr[0] == '-') {
577 c6dc6f63 Andre Przywara
            add_flagname_to_bitmaps(featurestr + 1, &minus_features, &minus_ext_features, &minus_ext2_features, &minus_ext3_features, &minus_kvm_features);
578 c6dc6f63 Andre Przywara
        } else if ((val = strchr(featurestr, '='))) {
579 c6dc6f63 Andre Przywara
            *val = 0; val++;
580 c6dc6f63 Andre Przywara
            if (!strcmp(featurestr, "family")) {
581 c6dc6f63 Andre Przywara
                char *err;
582 c6dc6f63 Andre Przywara
                numvalue = strtoul(val, &err, 0);
583 c6dc6f63 Andre Przywara
                if (!*val || *err) {
584 c6dc6f63 Andre Przywara
                    fprintf(stderr, "bad numerical value %s\n", val);
585 c6dc6f63 Andre Przywara
                    goto error;
586 c6dc6f63 Andre Przywara
                }
587 c6dc6f63 Andre Przywara
                x86_cpu_def->family = numvalue;
588 c6dc6f63 Andre Przywara
            } else if (!strcmp(featurestr, "model")) {
589 c6dc6f63 Andre Przywara
                char *err;
590 c6dc6f63 Andre Przywara
                numvalue = strtoul(val, &err, 0);
591 c6dc6f63 Andre Przywara
                if (!*val || *err || numvalue > 0xff) {
592 c6dc6f63 Andre Przywara
                    fprintf(stderr, "bad numerical value %s\n", val);
593 c6dc6f63 Andre Przywara
                    goto error;
594 c6dc6f63 Andre Przywara
                }
595 c6dc6f63 Andre Przywara
                x86_cpu_def->model = numvalue;
596 c6dc6f63 Andre Przywara
            } else if (!strcmp(featurestr, "stepping")) {
597 c6dc6f63 Andre Przywara
                char *err;
598 c6dc6f63 Andre Przywara
                numvalue = strtoul(val, &err, 0);
599 c6dc6f63 Andre Przywara
                if (!*val || *err || numvalue > 0xf) {
600 c6dc6f63 Andre Przywara
                    fprintf(stderr, "bad numerical value %s\n", val);
601 c6dc6f63 Andre Przywara
                    goto error;
602 c6dc6f63 Andre Przywara
                }
603 c6dc6f63 Andre Przywara
                x86_cpu_def->stepping = numvalue ;
604 c6dc6f63 Andre Przywara
            } else if (!strcmp(featurestr, "level")) {
605 c6dc6f63 Andre Przywara
                char *err;
606 c6dc6f63 Andre Przywara
                numvalue = strtoul(val, &err, 0);
607 c6dc6f63 Andre Przywara
                if (!*val || *err) {
608 c6dc6f63 Andre Przywara
                    fprintf(stderr, "bad numerical value %s\n", val);
609 c6dc6f63 Andre Przywara
                    goto error;
610 c6dc6f63 Andre Przywara
                }
611 c6dc6f63 Andre Przywara
                x86_cpu_def->level = numvalue;
612 c6dc6f63 Andre Przywara
            } else if (!strcmp(featurestr, "xlevel")) {
613 c6dc6f63 Andre Przywara
                char *err;
614 c6dc6f63 Andre Przywara
                numvalue = strtoul(val, &err, 0);
615 c6dc6f63 Andre Przywara
                if (!*val || *err) {
616 c6dc6f63 Andre Przywara
                    fprintf(stderr, "bad numerical value %s\n", val);
617 c6dc6f63 Andre Przywara
                    goto error;
618 c6dc6f63 Andre Przywara
                }
619 c6dc6f63 Andre Przywara
                if (numvalue < 0x80000000) {
620 2f7a21c4 Aurelien Jarno
                    numvalue += 0x80000000;
621 c6dc6f63 Andre Przywara
                }
622 c6dc6f63 Andre Przywara
                x86_cpu_def->xlevel = numvalue;
623 c6dc6f63 Andre Przywara
            } else if (!strcmp(featurestr, "vendor")) {
624 c6dc6f63 Andre Przywara
                if (strlen(val) != 12) {
625 c6dc6f63 Andre Przywara
                    fprintf(stderr, "vendor string must be 12 chars long\n");
626 c6dc6f63 Andre Przywara
                    goto error;
627 c6dc6f63 Andre Przywara
                }
628 c6dc6f63 Andre Przywara
                x86_cpu_def->vendor1 = 0;
629 c6dc6f63 Andre Przywara
                x86_cpu_def->vendor2 = 0;
630 c6dc6f63 Andre Przywara
                x86_cpu_def->vendor3 = 0;
631 c6dc6f63 Andre Przywara
                for(i = 0; i < 4; i++) {
632 c6dc6f63 Andre Przywara
                    x86_cpu_def->vendor1 |= ((uint8_t)val[i    ]) << (8 * i);
633 c6dc6f63 Andre Przywara
                    x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
634 c6dc6f63 Andre Przywara
                    x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
635 c6dc6f63 Andre Przywara
                }
636 c6dc6f63 Andre Przywara
                x86_cpu_def->vendor_override = 1;
637 c6dc6f63 Andre Przywara
            } else if (!strcmp(featurestr, "model_id")) {
638 c6dc6f63 Andre Przywara
                pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
639 c6dc6f63 Andre Przywara
                        val);
640 c6dc6f63 Andre Przywara
            } else {
641 c6dc6f63 Andre Przywara
                fprintf(stderr, "unrecognized feature %s\n", featurestr);
642 c6dc6f63 Andre Przywara
                goto error;
643 c6dc6f63 Andre Przywara
            }
644 c6dc6f63 Andre Przywara
        } else if (!strcmp(featurestr, "check")) {
645 c6dc6f63 Andre Przywara
            check_cpuid = 1;
646 c6dc6f63 Andre Przywara
        } else if (!strcmp(featurestr, "enforce")) {
647 c6dc6f63 Andre Przywara
            check_cpuid = enforce_cpuid = 1;
648 c6dc6f63 Andre Przywara
        } else {
649 c6dc6f63 Andre Przywara
            fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
650 c6dc6f63 Andre Przywara
            goto error;
651 c6dc6f63 Andre Przywara
        }
652 c6dc6f63 Andre Przywara
        featurestr = strtok(NULL, ",");
653 c6dc6f63 Andre Przywara
    }
654 c6dc6f63 Andre Przywara
    x86_cpu_def->features |= plus_features;
655 c6dc6f63 Andre Przywara
    x86_cpu_def->ext_features |= plus_ext_features;
656 c6dc6f63 Andre Przywara
    x86_cpu_def->ext2_features |= plus_ext2_features;
657 c6dc6f63 Andre Przywara
    x86_cpu_def->ext3_features |= plus_ext3_features;
658 c6dc6f63 Andre Przywara
    x86_cpu_def->kvm_features |= plus_kvm_features;
659 c6dc6f63 Andre Przywara
    x86_cpu_def->features &= ~minus_features;
660 c6dc6f63 Andre Przywara
    x86_cpu_def->ext_features &= ~minus_ext_features;
661 c6dc6f63 Andre Przywara
    x86_cpu_def->ext2_features &= ~minus_ext2_features;
662 c6dc6f63 Andre Przywara
    x86_cpu_def->ext3_features &= ~minus_ext3_features;
663 c6dc6f63 Andre Przywara
    x86_cpu_def->kvm_features &= ~minus_kvm_features;
664 c6dc6f63 Andre Przywara
    if (check_cpuid) {
665 c6dc6f63 Andre Przywara
        if (check_features_against_host(x86_cpu_def) && enforce_cpuid)
666 c6dc6f63 Andre Przywara
            goto error;
667 c6dc6f63 Andre Przywara
    }
668 c6dc6f63 Andre Przywara
    free(s);
669 c6dc6f63 Andre Przywara
    return 0;
670 c6dc6f63 Andre Przywara
671 c6dc6f63 Andre Przywara
error:
672 c6dc6f63 Andre Przywara
    free(s);
673 c6dc6f63 Andre Przywara
    return -1;
674 c6dc6f63 Andre Przywara
}
675 c6dc6f63 Andre Przywara
676 c6dc6f63 Andre Przywara
/* generate a composite string into buf of all cpuid names in featureset
677 c6dc6f63 Andre Przywara
 * selected by fbits.  indicate truncation at bufsize in the event of overflow.
678 c6dc6f63 Andre Przywara
 * if flags, suppress names undefined in featureset.
679 c6dc6f63 Andre Przywara
 */
680 c6dc6f63 Andre Przywara
static void listflags(char *buf, int bufsize, uint32_t fbits,
681 c6dc6f63 Andre Przywara
    const char **featureset, uint32_t flags)
682 c6dc6f63 Andre Przywara
{
683 c6dc6f63 Andre Przywara
    const char **p = &featureset[31];
684 c6dc6f63 Andre Przywara
    char *q, *b, bit;
685 c6dc6f63 Andre Przywara
    int nc;
686 c6dc6f63 Andre Przywara
687 c6dc6f63 Andre Przywara
    b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
688 c6dc6f63 Andre Przywara
    *buf = '\0';
689 c6dc6f63 Andre Przywara
    for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
690 c6dc6f63 Andre Przywara
        if (fbits & 1 << bit && (*p || !flags)) {
691 c6dc6f63 Andre Przywara
            if (*p)
692 c6dc6f63 Andre Przywara
                nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
693 c6dc6f63 Andre Przywara
            else
694 c6dc6f63 Andre Przywara
                nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
695 c6dc6f63 Andre Przywara
            if (bufsize <= nc) {
696 c6dc6f63 Andre Przywara
                if (b) {
697 c6dc6f63 Andre Przywara
                    memcpy(b, "...", sizeof("..."));
698 c6dc6f63 Andre Przywara
                }
699 c6dc6f63 Andre Przywara
                return;
700 c6dc6f63 Andre Przywara
            }
701 c6dc6f63 Andre Przywara
            q += nc;
702 c6dc6f63 Andre Przywara
            bufsize -= nc;
703 c6dc6f63 Andre Przywara
        }
704 c6dc6f63 Andre Przywara
}
705 c6dc6f63 Andre Przywara
706 c6dc6f63 Andre Przywara
/* generate CPU information:
707 c6dc6f63 Andre Przywara
 * -?        list model names
708 c6dc6f63 Andre Przywara
 * -?model   list model names/IDs
709 c6dc6f63 Andre Przywara
 * -?dump    output all model (x86_def_t) data
710 c6dc6f63 Andre Przywara
 * -?cpuid   list all recognized cpuid flag names
711 c6dc6f63 Andre Przywara
 */
712 c6dc6f63 Andre Przywara
void x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
713 c6dc6f63 Andre Przywara
                  const char *optarg)
714 c6dc6f63 Andre Przywara
{
715 c6dc6f63 Andre Przywara
    unsigned char model = !strcmp("?model", optarg);
716 c6dc6f63 Andre Przywara
    unsigned char dump = !strcmp("?dump", optarg);
717 c6dc6f63 Andre Przywara
    unsigned char cpuid = !strcmp("?cpuid", optarg);
718 c6dc6f63 Andre Przywara
    x86_def_t *def;
719 c6dc6f63 Andre Przywara
    char buf[256];
720 c6dc6f63 Andre Przywara
721 c6dc6f63 Andre Przywara
    if (cpuid) {
722 c6dc6f63 Andre Przywara
        (*cpu_fprintf)(f, "Recognized CPUID flags:\n");
723 c6dc6f63 Andre Przywara
        listflags(buf, sizeof (buf), (uint32_t)~0, feature_name, 1);
724 c6dc6f63 Andre Przywara
        (*cpu_fprintf)(f, "  f_edx: %s\n", buf);
725 c6dc6f63 Andre Przywara
        listflags(buf, sizeof (buf), (uint32_t)~0, ext_feature_name, 1);
726 c6dc6f63 Andre Przywara
        (*cpu_fprintf)(f, "  f_ecx: %s\n", buf);
727 c6dc6f63 Andre Przywara
        listflags(buf, sizeof (buf), (uint32_t)~0, ext2_feature_name, 1);
728 c6dc6f63 Andre Przywara
        (*cpu_fprintf)(f, "  extf_edx: %s\n", buf);
729 c6dc6f63 Andre Przywara
        listflags(buf, sizeof (buf), (uint32_t)~0, ext3_feature_name, 1);
730 c6dc6f63 Andre Przywara
        (*cpu_fprintf)(f, "  extf_ecx: %s\n", buf);
731 c6dc6f63 Andre Przywara
        return;
732 c6dc6f63 Andre Przywara
    }
733 c6dc6f63 Andre Przywara
    for (def = x86_defs; def; def = def->next) {
734 c6dc6f63 Andre Przywara
        snprintf(buf, sizeof (buf), def->flags ? "[%s]": "%s", def->name);
735 c6dc6f63 Andre Przywara
        if (model || dump) {
736 c6dc6f63 Andre Przywara
            (*cpu_fprintf)(f, "x86 %16s  %-48s\n", buf, def->model_id);
737 c6dc6f63 Andre Przywara
        } else {
738 c6dc6f63 Andre Przywara
            (*cpu_fprintf)(f, "x86 %16s\n", buf);
739 c6dc6f63 Andre Przywara
        }
740 c6dc6f63 Andre Przywara
        if (dump) {
741 c6dc6f63 Andre Przywara
            memcpy(buf, &def->vendor1, sizeof (def->vendor1));
742 c6dc6f63 Andre Przywara
            memcpy(buf + 4, &def->vendor2, sizeof (def->vendor2));
743 c6dc6f63 Andre Przywara
            memcpy(buf + 8, &def->vendor3, sizeof (def->vendor3));
744 c6dc6f63 Andre Przywara
            buf[12] = '\0';
745 c6dc6f63 Andre Przywara
            (*cpu_fprintf)(f,
746 c6dc6f63 Andre Przywara
                "  family %d model %d stepping %d level %d xlevel 0x%x"
747 c6dc6f63 Andre Przywara
                " vendor \"%s\"\n",
748 c6dc6f63 Andre Przywara
                def->family, def->model, def->stepping, def->level,
749 c6dc6f63 Andre Przywara
                def->xlevel, buf);
750 c6dc6f63 Andre Przywara
            listflags(buf, sizeof (buf), def->features, feature_name, 0);
751 c6dc6f63 Andre Przywara
            (*cpu_fprintf)(f, "  feature_edx %08x (%s)\n", def->features,
752 c6dc6f63 Andre Przywara
                buf);
753 c6dc6f63 Andre Przywara
            listflags(buf, sizeof (buf), def->ext_features, ext_feature_name,
754 c6dc6f63 Andre Przywara
                0);
755 c6dc6f63 Andre Przywara
            (*cpu_fprintf)(f, "  feature_ecx %08x (%s)\n", def->ext_features,
756 c6dc6f63 Andre Przywara
                buf);
757 c6dc6f63 Andre Przywara
            listflags(buf, sizeof (buf), def->ext2_features, ext2_feature_name,
758 c6dc6f63 Andre Przywara
                0);
759 c6dc6f63 Andre Przywara
            (*cpu_fprintf)(f, "  extfeature_edx %08x (%s)\n",
760 c6dc6f63 Andre Przywara
                def->ext2_features, buf);
761 c6dc6f63 Andre Przywara
            listflags(buf, sizeof (buf), def->ext3_features, ext3_feature_name,
762 c6dc6f63 Andre Przywara
                0);
763 c6dc6f63 Andre Przywara
            (*cpu_fprintf)(f, "  extfeature_ecx %08x (%s)\n",
764 c6dc6f63 Andre Przywara
                def->ext3_features, buf);
765 c6dc6f63 Andre Przywara
            (*cpu_fprintf)(f, "\n");
766 c6dc6f63 Andre Przywara
        }
767 c6dc6f63 Andre Przywara
    }
768 ed2c54d4 Andre Przywara
    if (kvm_enabled()) {
769 ed2c54d4 Andre Przywara
        (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
770 ed2c54d4 Andre Przywara
    }
771 c6dc6f63 Andre Przywara
}
772 c6dc6f63 Andre Przywara
773 c6dc6f63 Andre Przywara
int cpu_x86_register (CPUX86State *env, const char *cpu_model)
774 c6dc6f63 Andre Przywara
{
775 c6dc6f63 Andre Przywara
    x86_def_t def1, *def = &def1;
776 c6dc6f63 Andre Przywara
777 c6dc6f63 Andre Przywara
    if (cpu_x86_find_by_name(def, cpu_model) < 0)
778 c6dc6f63 Andre Przywara
        return -1;
779 c6dc6f63 Andre Przywara
    if (def->vendor1) {
780 c6dc6f63 Andre Przywara
        env->cpuid_vendor1 = def->vendor1;
781 c6dc6f63 Andre Przywara
        env->cpuid_vendor2 = def->vendor2;
782 c6dc6f63 Andre Przywara
        env->cpuid_vendor3 = def->vendor3;
783 c6dc6f63 Andre Przywara
    } else {
784 c6dc6f63 Andre Przywara
        env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
785 c6dc6f63 Andre Przywara
        env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
786 c6dc6f63 Andre Przywara
        env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
787 c6dc6f63 Andre Przywara
    }
788 c6dc6f63 Andre Przywara
    env->cpuid_vendor_override = def->vendor_override;
789 c6dc6f63 Andre Przywara
    env->cpuid_level = def->level;
790 c6dc6f63 Andre Przywara
    if (def->family > 0x0f)
791 c6dc6f63 Andre Przywara
        env->cpuid_version = 0xf00 | ((def->family - 0x0f) << 20);
792 c6dc6f63 Andre Przywara
    else
793 c6dc6f63 Andre Przywara
        env->cpuid_version = def->family << 8;
794 c6dc6f63 Andre Przywara
    env->cpuid_version |= ((def->model & 0xf) << 4) | ((def->model >> 4) << 16);
795 c6dc6f63 Andre Przywara
    env->cpuid_version |= def->stepping;
796 c6dc6f63 Andre Przywara
    env->cpuid_features = def->features;
797 c6dc6f63 Andre Przywara
    env->pat = 0x0007040600070406ULL;
798 c6dc6f63 Andre Przywara
    env->cpuid_ext_features = def->ext_features;
799 c6dc6f63 Andre Przywara
    env->cpuid_ext2_features = def->ext2_features;
800 4d067ed7 Andre Przywara
    env->cpuid_ext3_features = def->ext3_features;
801 c6dc6f63 Andre Przywara
    env->cpuid_xlevel = def->xlevel;
802 c6dc6f63 Andre Przywara
    env->cpuid_kvm_features = def->kvm_features;
803 551a2dec Andre Przywara
    if (!kvm_enabled()) {
804 551a2dec Andre Przywara
        env->cpuid_features &= TCG_FEATURES;
805 551a2dec Andre Przywara
        env->cpuid_ext_features &= TCG_EXT_FEATURES;
806 551a2dec Andre Przywara
        env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
807 551a2dec Andre Przywara
#ifdef TARGET_X86_64
808 551a2dec Andre Przywara
            | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
809 551a2dec Andre Przywara
#endif
810 551a2dec Andre Przywara
            );
811 551a2dec Andre Przywara
        env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
812 551a2dec Andre Przywara
    }
813 c6dc6f63 Andre Przywara
    {
814 c6dc6f63 Andre Przywara
        const char *model_id = def->model_id;
815 c6dc6f63 Andre Przywara
        int c, len, i;
816 c6dc6f63 Andre Przywara
        if (!model_id)
817 c6dc6f63 Andre Przywara
            model_id = "";
818 c6dc6f63 Andre Przywara
        len = strlen(model_id);
819 c6dc6f63 Andre Przywara
        for(i = 0; i < 48; i++) {
820 c6dc6f63 Andre Przywara
            if (i >= len)
821 c6dc6f63 Andre Przywara
                c = '\0';
822 c6dc6f63 Andre Przywara
            else
823 c6dc6f63 Andre Przywara
                c = (uint8_t)model_id[i];
824 c6dc6f63 Andre Przywara
            env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
825 c6dc6f63 Andre Przywara
        }
826 c6dc6f63 Andre Przywara
    }
827 c6dc6f63 Andre Przywara
    return 0;
828 c6dc6f63 Andre Przywara
}
829 c6dc6f63 Andre Przywara
830 c6dc6f63 Andre Przywara
#if !defined(CONFIG_USER_ONLY)
831 c6dc6f63 Andre Przywara
/* copy vendor id string to 32 bit register, nul pad as needed
832 c6dc6f63 Andre Przywara
 */
833 c6dc6f63 Andre Przywara
static void cpyid(const char *s, uint32_t *id)
834 c6dc6f63 Andre Przywara
{
835 c6dc6f63 Andre Przywara
    char *d = (char *)id;
836 c6dc6f63 Andre Przywara
    char i;
837 c6dc6f63 Andre Przywara
838 c6dc6f63 Andre Przywara
    for (i = sizeof (*id); i--; )
839 c6dc6f63 Andre Przywara
        *d++ = *s ? *s++ : '\0';
840 c6dc6f63 Andre Przywara
}
841 c6dc6f63 Andre Przywara
842 c6dc6f63 Andre Przywara
/* interpret radix and convert from string to arbitrary scalar,
843 c6dc6f63 Andre Przywara
 * otherwise flag failure
844 c6dc6f63 Andre Przywara
 */
845 c6dc6f63 Andre Przywara
#define setscalar(pval, str, perr)                      \
846 c6dc6f63 Andre Przywara
{                                                       \
847 c6dc6f63 Andre Przywara
    char *pend;                                         \
848 c6dc6f63 Andre Przywara
    unsigned long ul;                                   \
849 c6dc6f63 Andre Przywara
                                                        \
850 c6dc6f63 Andre Przywara
    ul = strtoul(str, &pend, 0);                        \
851 c6dc6f63 Andre Przywara
    *str && !*pend ? (*pval = ul) : (*perr = 1);        \
852 c6dc6f63 Andre Przywara
}
853 c6dc6f63 Andre Przywara
854 c6dc6f63 Andre Przywara
/* map cpuid options to feature bits, otherwise return failure
855 c6dc6f63 Andre Przywara
 * (option tags in *str are delimited by whitespace)
856 c6dc6f63 Andre Przywara
 */
857 c6dc6f63 Andre Przywara
static void setfeatures(uint32_t *pval, const char *str,
858 c6dc6f63 Andre Przywara
    const char **featureset, int *perr)
859 c6dc6f63 Andre Przywara
{
860 c6dc6f63 Andre Przywara
    const char *p, *q;
861 c6dc6f63 Andre Przywara
862 c6dc6f63 Andre Przywara
    for (q = p = str; *p || *q; q = p) {
863 c6dc6f63 Andre Przywara
        while (iswhite(*p))
864 c6dc6f63 Andre Przywara
            q = ++p;
865 c6dc6f63 Andre Przywara
        while (*p && !iswhite(*p))
866 c6dc6f63 Andre Przywara
            ++p;
867 c6dc6f63 Andre Przywara
        if (!*q && !*p)
868 c6dc6f63 Andre Przywara
            return;
869 c6dc6f63 Andre Przywara
        if (!lookup_feature(pval, q, p, featureset)) {
870 c6dc6f63 Andre Przywara
            fprintf(stderr, "error: feature \"%.*s\" not available in set\n",
871 c6dc6f63 Andre Przywara
                (int)(p - q), q);
872 c6dc6f63 Andre Przywara
            *perr = 1;
873 c6dc6f63 Andre Przywara
            return;
874 c6dc6f63 Andre Przywara
        }
875 c6dc6f63 Andre Przywara
    }
876 c6dc6f63 Andre Przywara
}
877 c6dc6f63 Andre Przywara
878 c6dc6f63 Andre Przywara
/* map config file options to x86_def_t form
879 c6dc6f63 Andre Przywara
 */
880 c6dc6f63 Andre Przywara
static int cpudef_setfield(const char *name, const char *str, void *opaque)
881 c6dc6f63 Andre Przywara
{
882 c6dc6f63 Andre Przywara
    x86_def_t *def = opaque;
883 c6dc6f63 Andre Przywara
    int err = 0;
884 c6dc6f63 Andre Przywara
885 c6dc6f63 Andre Przywara
    if (!strcmp(name, "name")) {
886 c6dc6f63 Andre Przywara
        def->name = strdup(str);
887 c6dc6f63 Andre Przywara
    } else if (!strcmp(name, "model_id")) {
888 c6dc6f63 Andre Przywara
        strncpy(def->model_id, str, sizeof (def->model_id));
889 c6dc6f63 Andre Przywara
    } else if (!strcmp(name, "level")) {
890 c6dc6f63 Andre Przywara
        setscalar(&def->level, str, &err)
891 c6dc6f63 Andre Przywara
    } else if (!strcmp(name, "vendor")) {
892 c6dc6f63 Andre Przywara
        cpyid(&str[0], &def->vendor1);
893 c6dc6f63 Andre Przywara
        cpyid(&str[4], &def->vendor2);
894 c6dc6f63 Andre Przywara
        cpyid(&str[8], &def->vendor3);
895 c6dc6f63 Andre Przywara
    } else if (!strcmp(name, "family")) {
896 c6dc6f63 Andre Przywara
        setscalar(&def->family, str, &err)
897 c6dc6f63 Andre Przywara
    } else if (!strcmp(name, "model")) {
898 c6dc6f63 Andre Przywara
        setscalar(&def->model, str, &err)
899 c6dc6f63 Andre Przywara
    } else if (!strcmp(name, "stepping")) {
900 c6dc6f63 Andre Przywara
        setscalar(&def->stepping, str, &err)
901 c6dc6f63 Andre Przywara
    } else if (!strcmp(name, "feature_edx")) {
902 c6dc6f63 Andre Przywara
        setfeatures(&def->features, str, feature_name, &err);
903 c6dc6f63 Andre Przywara
    } else if (!strcmp(name, "feature_ecx")) {
904 c6dc6f63 Andre Przywara
        setfeatures(&def->ext_features, str, ext_feature_name, &err);
905 c6dc6f63 Andre Przywara
    } else if (!strcmp(name, "extfeature_edx")) {
906 c6dc6f63 Andre Przywara
        setfeatures(&def->ext2_features, str, ext2_feature_name, &err);
907 c6dc6f63 Andre Przywara
    } else if (!strcmp(name, "extfeature_ecx")) {
908 c6dc6f63 Andre Przywara
        setfeatures(&def->ext3_features, str, ext3_feature_name, &err);
909 c6dc6f63 Andre Przywara
    } else if (!strcmp(name, "xlevel")) {
910 c6dc6f63 Andre Przywara
        setscalar(&def->xlevel, str, &err)
911 c6dc6f63 Andre Przywara
    } else {
912 c6dc6f63 Andre Przywara
        fprintf(stderr, "error: unknown option [%s = %s]\n", name, str);
913 c6dc6f63 Andre Przywara
        return (1);
914 c6dc6f63 Andre Przywara
    }
915 c6dc6f63 Andre Przywara
    if (err) {
916 c6dc6f63 Andre Przywara
        fprintf(stderr, "error: bad option value [%s = %s]\n", name, str);
917 c6dc6f63 Andre Przywara
        return (1);
918 c6dc6f63 Andre Przywara
    }
919 c6dc6f63 Andre Przywara
    return (0);
920 c6dc6f63 Andre Przywara
}
921 c6dc6f63 Andre Przywara
922 c6dc6f63 Andre Przywara
/* register config file entry as x86_def_t
923 c6dc6f63 Andre Przywara
 */
924 c6dc6f63 Andre Przywara
static int cpudef_register(QemuOpts *opts, void *opaque)
925 c6dc6f63 Andre Przywara
{
926 c6dc6f63 Andre Przywara
    x86_def_t *def = qemu_mallocz(sizeof (x86_def_t));
927 c6dc6f63 Andre Przywara
928 c6dc6f63 Andre Przywara
    qemu_opt_foreach(opts, cpudef_setfield, def, 1);
929 c6dc6f63 Andre Przywara
    def->next = x86_defs;
930 c6dc6f63 Andre Przywara
    x86_defs = def;
931 c6dc6f63 Andre Przywara
    return (0);
932 c6dc6f63 Andre Przywara
}
933 c6dc6f63 Andre Przywara
#endif /* !CONFIG_USER_ONLY */
934 c6dc6f63 Andre Przywara
935 c6dc6f63 Andre Przywara
/* register "cpudef" models defined in configuration file.  Here we first
936 c6dc6f63 Andre Przywara
 * preload any built-in definitions
937 c6dc6f63 Andre Przywara
 */
938 c6dc6f63 Andre Przywara
void x86_cpudef_setup(void)
939 c6dc6f63 Andre Przywara
{
940 c6dc6f63 Andre Przywara
    int i;
941 c6dc6f63 Andre Przywara
942 c6dc6f63 Andre Przywara
    for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
943 c6dc6f63 Andre Przywara
        builtin_x86_defs[i].next = x86_defs;
944 c6dc6f63 Andre Przywara
        builtin_x86_defs[i].flags = 1;
945 c6dc6f63 Andre Przywara
        x86_defs = &builtin_x86_defs[i];
946 c6dc6f63 Andre Przywara
    }
947 c6dc6f63 Andre Przywara
#if !defined(CONFIG_USER_ONLY)
948 c6dc6f63 Andre Przywara
    qemu_opts_foreach(&qemu_cpudef_opts, cpudef_register, NULL, 0);
949 c6dc6f63 Andre Przywara
#endif
950 c6dc6f63 Andre Przywara
}
951 c6dc6f63 Andre Przywara
952 c6dc6f63 Andre Przywara
static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
953 c6dc6f63 Andre Przywara
                             uint32_t *ecx, uint32_t *edx)
954 c6dc6f63 Andre Przywara
{
955 c6dc6f63 Andre Przywara
    *ebx = env->cpuid_vendor1;
956 c6dc6f63 Andre Przywara
    *edx = env->cpuid_vendor2;
957 c6dc6f63 Andre Przywara
    *ecx = env->cpuid_vendor3;
958 c6dc6f63 Andre Przywara
959 c6dc6f63 Andre Przywara
    /* sysenter isn't supported on compatibility mode on AMD, syscall
960 c6dc6f63 Andre Przywara
     * isn't supported in compatibility mode on Intel.
961 c6dc6f63 Andre Przywara
     * Normally we advertise the actual cpu vendor, but you can override
962 c6dc6f63 Andre Przywara
     * this if you want to use KVM's sysenter/syscall emulation
963 c6dc6f63 Andre Przywara
     * in compatibility mode and when doing cross vendor migration
964 c6dc6f63 Andre Przywara
     */
965 c6dc6f63 Andre Przywara
    if (kvm_enabled() && env->cpuid_vendor_override) {
966 c6dc6f63 Andre Przywara
        host_cpuid(0, 0, NULL, ebx, ecx, edx);
967 c6dc6f63 Andre Przywara
    }
968 c6dc6f63 Andre Przywara
}
969 c6dc6f63 Andre Przywara
970 c6dc6f63 Andre Przywara
void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
971 c6dc6f63 Andre Przywara
                   uint32_t *eax, uint32_t *ebx,
972 c6dc6f63 Andre Przywara
                   uint32_t *ecx, uint32_t *edx)
973 c6dc6f63 Andre Przywara
{
974 c6dc6f63 Andre Przywara
    /* test if maximum index reached */
975 c6dc6f63 Andre Przywara
    if (index & 0x80000000) {
976 c6dc6f63 Andre Przywara
        if (index > env->cpuid_xlevel)
977 c6dc6f63 Andre Przywara
            index = env->cpuid_level;
978 c6dc6f63 Andre Przywara
    } else {
979 c6dc6f63 Andre Przywara
        if (index > env->cpuid_level)
980 c6dc6f63 Andre Przywara
            index = env->cpuid_level;
981 c6dc6f63 Andre Przywara
    }
982 c6dc6f63 Andre Przywara
983 c6dc6f63 Andre Przywara
    switch(index) {
984 c6dc6f63 Andre Przywara
    case 0:
985 c6dc6f63 Andre Przywara
        *eax = env->cpuid_level;
986 c6dc6f63 Andre Przywara
        get_cpuid_vendor(env, ebx, ecx, edx);
987 c6dc6f63 Andre Przywara
        break;
988 c6dc6f63 Andre Przywara
    case 1:
989 c6dc6f63 Andre Przywara
        *eax = env->cpuid_version;
990 c6dc6f63 Andre Przywara
        *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
991 c6dc6f63 Andre Przywara
        *ecx = env->cpuid_ext_features;
992 c6dc6f63 Andre Przywara
        *edx = env->cpuid_features;
993 c6dc6f63 Andre Przywara
        if (env->nr_cores * env->nr_threads > 1) {
994 c6dc6f63 Andre Przywara
            *ebx |= (env->nr_cores * env->nr_threads) << 16;
995 c6dc6f63 Andre Przywara
            *edx |= 1 << 28;    /* HTT bit */
996 c6dc6f63 Andre Przywara
        }
997 c6dc6f63 Andre Przywara
        break;
998 c6dc6f63 Andre Przywara
    case 2:
999 c6dc6f63 Andre Przywara
        /* cache info: needed for Pentium Pro compatibility */
1000 c6dc6f63 Andre Przywara
        *eax = 1;
1001 c6dc6f63 Andre Przywara
        *ebx = 0;
1002 c6dc6f63 Andre Przywara
        *ecx = 0;
1003 c6dc6f63 Andre Przywara
        *edx = 0x2c307d;
1004 c6dc6f63 Andre Przywara
        break;
1005 c6dc6f63 Andre Przywara
    case 4:
1006 c6dc6f63 Andre Przywara
        /* cache info: needed for Core compatibility */
1007 c6dc6f63 Andre Przywara
        if (env->nr_cores > 1) {
1008 2f7a21c4 Aurelien Jarno
            *eax = (env->nr_cores - 1) << 26;
1009 c6dc6f63 Andre Przywara
        } else {
1010 2f7a21c4 Aurelien Jarno
            *eax = 0;
1011 c6dc6f63 Andre Przywara
        }
1012 c6dc6f63 Andre Przywara
        switch (count) {
1013 c6dc6f63 Andre Przywara
            case 0: /* L1 dcache info */
1014 c6dc6f63 Andre Przywara
                *eax |= 0x0000121;
1015 c6dc6f63 Andre Przywara
                *ebx = 0x1c0003f;
1016 c6dc6f63 Andre Przywara
                *ecx = 0x000003f;
1017 c6dc6f63 Andre Przywara
                *edx = 0x0000001;
1018 c6dc6f63 Andre Przywara
                break;
1019 c6dc6f63 Andre Przywara
            case 1: /* L1 icache info */
1020 c6dc6f63 Andre Przywara
                *eax |= 0x0000122;
1021 c6dc6f63 Andre Przywara
                *ebx = 0x1c0003f;
1022 c6dc6f63 Andre Przywara
                *ecx = 0x000003f;
1023 c6dc6f63 Andre Przywara
                *edx = 0x0000001;
1024 c6dc6f63 Andre Przywara
                break;
1025 c6dc6f63 Andre Przywara
            case 2: /* L2 cache info */
1026 c6dc6f63 Andre Przywara
                *eax |= 0x0000143;
1027 c6dc6f63 Andre Przywara
                if (env->nr_threads > 1) {
1028 c6dc6f63 Andre Przywara
                    *eax |= (env->nr_threads - 1) << 14;
1029 c6dc6f63 Andre Przywara
                }
1030 c6dc6f63 Andre Przywara
                *ebx = 0x3c0003f;
1031 c6dc6f63 Andre Przywara
                *ecx = 0x0000fff;
1032 c6dc6f63 Andre Przywara
                *edx = 0x0000001;
1033 c6dc6f63 Andre Przywara
                break;
1034 c6dc6f63 Andre Przywara
            default: /* end of info */
1035 c6dc6f63 Andre Przywara
                *eax = 0;
1036 c6dc6f63 Andre Przywara
                *ebx = 0;
1037 c6dc6f63 Andre Przywara
                *ecx = 0;
1038 c6dc6f63 Andre Przywara
                *edx = 0;
1039 c6dc6f63 Andre Przywara
                break;
1040 c6dc6f63 Andre Przywara
        }
1041 c6dc6f63 Andre Przywara
        break;
1042 c6dc6f63 Andre Przywara
    case 5:
1043 c6dc6f63 Andre Przywara
        /* mwait info: needed for Core compatibility */
1044 c6dc6f63 Andre Przywara
        *eax = 0; /* Smallest monitor-line size in bytes */
1045 c6dc6f63 Andre Przywara
        *ebx = 0; /* Largest monitor-line size in bytes */
1046 c6dc6f63 Andre Przywara
        *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1047 c6dc6f63 Andre Przywara
        *edx = 0;
1048 c6dc6f63 Andre Przywara
        break;
1049 c6dc6f63 Andre Przywara
    case 6:
1050 c6dc6f63 Andre Przywara
        /* Thermal and Power Leaf */
1051 c6dc6f63 Andre Przywara
        *eax = 0;
1052 c6dc6f63 Andre Przywara
        *ebx = 0;
1053 c6dc6f63 Andre Przywara
        *ecx = 0;
1054 c6dc6f63 Andre Przywara
        *edx = 0;
1055 c6dc6f63 Andre Przywara
        break;
1056 c6dc6f63 Andre Przywara
    case 9:
1057 c6dc6f63 Andre Przywara
        /* Direct Cache Access Information Leaf */
1058 c6dc6f63 Andre Przywara
        *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1059 c6dc6f63 Andre Przywara
        *ebx = 0;
1060 c6dc6f63 Andre Przywara
        *ecx = 0;
1061 c6dc6f63 Andre Przywara
        *edx = 0;
1062 c6dc6f63 Andre Przywara
        break;
1063 c6dc6f63 Andre Przywara
    case 0xA:
1064 c6dc6f63 Andre Przywara
        /* Architectural Performance Monitoring Leaf */
1065 c6dc6f63 Andre Przywara
        *eax = 0;
1066 c6dc6f63 Andre Przywara
        *ebx = 0;
1067 c6dc6f63 Andre Przywara
        *ecx = 0;
1068 c6dc6f63 Andre Przywara
        *edx = 0;
1069 c6dc6f63 Andre Przywara
        break;
1070 c6dc6f63 Andre Przywara
    case 0x80000000:
1071 c6dc6f63 Andre Przywara
        *eax = env->cpuid_xlevel;
1072 c6dc6f63 Andre Przywara
        *ebx = env->cpuid_vendor1;
1073 c6dc6f63 Andre Przywara
        *edx = env->cpuid_vendor2;
1074 c6dc6f63 Andre Przywara
        *ecx = env->cpuid_vendor3;
1075 c6dc6f63 Andre Przywara
        break;
1076 c6dc6f63 Andre Przywara
    case 0x80000001:
1077 c6dc6f63 Andre Przywara
        *eax = env->cpuid_version;
1078 c6dc6f63 Andre Przywara
        *ebx = 0;
1079 c6dc6f63 Andre Przywara
        *ecx = env->cpuid_ext3_features;
1080 c6dc6f63 Andre Przywara
        *edx = env->cpuid_ext2_features;
1081 c6dc6f63 Andre Przywara
1082 c6dc6f63 Andre Przywara
        /* The Linux kernel checks for the CMPLegacy bit and
1083 c6dc6f63 Andre Przywara
         * discards multiple thread information if it is set.
1084 c6dc6f63 Andre Przywara
         * So dont set it here for Intel to make Linux guests happy.
1085 c6dc6f63 Andre Przywara
         */
1086 c6dc6f63 Andre Przywara
        if (env->nr_cores * env->nr_threads > 1) {
1087 c6dc6f63 Andre Przywara
            uint32_t tebx, tecx, tedx;
1088 c6dc6f63 Andre Przywara
            get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1089 c6dc6f63 Andre Przywara
            if (tebx != CPUID_VENDOR_INTEL_1 ||
1090 c6dc6f63 Andre Przywara
                tedx != CPUID_VENDOR_INTEL_2 ||
1091 c6dc6f63 Andre Przywara
                tecx != CPUID_VENDOR_INTEL_3) {
1092 c6dc6f63 Andre Przywara
                *ecx |= 1 << 1;    /* CmpLegacy bit */
1093 c6dc6f63 Andre Przywara
            }
1094 c6dc6f63 Andre Przywara
        }
1095 c6dc6f63 Andre Przywara
1096 c6dc6f63 Andre Przywara
        if (kvm_enabled()) {
1097 c6dc6f63 Andre Przywara
            /* Nested SVM not yet supported in upstream QEMU */
1098 c6dc6f63 Andre Przywara
            *ecx &= ~CPUID_EXT3_SVM;
1099 c6dc6f63 Andre Przywara
        }
1100 c6dc6f63 Andre Przywara
        break;
1101 c6dc6f63 Andre Przywara
    case 0x80000002:
1102 c6dc6f63 Andre Przywara
    case 0x80000003:
1103 c6dc6f63 Andre Przywara
    case 0x80000004:
1104 c6dc6f63 Andre Przywara
        *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1105 c6dc6f63 Andre Przywara
        *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1106 c6dc6f63 Andre Przywara
        *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1107 c6dc6f63 Andre Przywara
        *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1108 c6dc6f63 Andre Przywara
        break;
1109 c6dc6f63 Andre Przywara
    case 0x80000005:
1110 c6dc6f63 Andre Przywara
        /* cache info (L1 cache) */
1111 c6dc6f63 Andre Przywara
        *eax = 0x01ff01ff;
1112 c6dc6f63 Andre Przywara
        *ebx = 0x01ff01ff;
1113 c6dc6f63 Andre Przywara
        *ecx = 0x40020140;
1114 c6dc6f63 Andre Przywara
        *edx = 0x40020140;
1115 c6dc6f63 Andre Przywara
        break;
1116 c6dc6f63 Andre Przywara
    case 0x80000006:
1117 c6dc6f63 Andre Przywara
        /* cache info (L2 cache) */
1118 c6dc6f63 Andre Przywara
        *eax = 0;
1119 c6dc6f63 Andre Przywara
        *ebx = 0x42004200;
1120 c6dc6f63 Andre Przywara
        *ecx = 0x02008140;
1121 c6dc6f63 Andre Przywara
        *edx = 0;
1122 c6dc6f63 Andre Przywara
        break;
1123 c6dc6f63 Andre Przywara
    case 0x80000008:
1124 c6dc6f63 Andre Przywara
        /* virtual & phys address size in low 2 bytes. */
1125 c6dc6f63 Andre Przywara
/* XXX: This value must match the one used in the MMU code. */
1126 c6dc6f63 Andre Przywara
        if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1127 c6dc6f63 Andre Przywara
            /* 64 bit processor */
1128 c6dc6f63 Andre Przywara
/* XXX: The physical address space is limited to 42 bits in exec.c. */
1129 c6dc6f63 Andre Przywara
            *eax = 0x00003028;        /* 48 bits virtual, 40 bits physical */
1130 c6dc6f63 Andre Przywara
        } else {
1131 c6dc6f63 Andre Przywara
            if (env->cpuid_features & CPUID_PSE36)
1132 c6dc6f63 Andre Przywara
                *eax = 0x00000024; /* 36 bits physical */
1133 c6dc6f63 Andre Przywara
            else
1134 c6dc6f63 Andre Przywara
                *eax = 0x00000020; /* 32 bits physical */
1135 c6dc6f63 Andre Przywara
        }
1136 c6dc6f63 Andre Przywara
        *ebx = 0;
1137 c6dc6f63 Andre Przywara
        *ecx = 0;
1138 c6dc6f63 Andre Przywara
        *edx = 0;
1139 c6dc6f63 Andre Przywara
        if (env->nr_cores * env->nr_threads > 1) {
1140 c6dc6f63 Andre Przywara
            *ecx |= (env->nr_cores * env->nr_threads) - 1;
1141 c6dc6f63 Andre Przywara
        }
1142 c6dc6f63 Andre Przywara
        break;
1143 c6dc6f63 Andre Przywara
    case 0x8000000A:
1144 c6dc6f63 Andre Przywara
        *eax = 0x00000001; /* SVM Revision */
1145 c6dc6f63 Andre Przywara
        *ebx = 0x00000010; /* nr of ASIDs */
1146 c6dc6f63 Andre Przywara
        *ecx = 0;
1147 c6dc6f63 Andre Przywara
        *edx = 0; /* optional features */
1148 c6dc6f63 Andre Przywara
        break;
1149 c6dc6f63 Andre Przywara
    default:
1150 c6dc6f63 Andre Przywara
        /* reserved values: zero */
1151 c6dc6f63 Andre Przywara
        *eax = 0;
1152 c6dc6f63 Andre Przywara
        *ebx = 0;
1153 c6dc6f63 Andre Przywara
        *ecx = 0;
1154 c6dc6f63 Andre Przywara
        *edx = 0;
1155 c6dc6f63 Andre Przywara
        break;
1156 c6dc6f63 Andre Przywara
    }
1157 c6dc6f63 Andre Przywara
}