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root / target-sh4 @ 8c0d577e

Name Size
README.sh4 4.8 kB
cpu.h 10.1 kB
exec.h 1.3 kB
helper.c 17.1 kB
helper.h 1.6 kB
machine.c 0 Bytes
op_helper.c 12.1 kB
translate.c 60.7 kB

Latest revisions

# Date Author Comment
1a7ff922 04/08/2010 10:34 pm Paolo Bonzini

remove TARGET_* defines from translate-all.c

Signed-off-by: Paolo Bonzini <>
Signed-off-by: Aurelien Jarno <>

43dc2a64 03/18/2010 08:41 pm Blue Swirl

Replace assert(0) with abort() or cpu_abort()

When building with -DNDEBUG, assert(0) will not stop execution
so it must not be used for abnormal termination.

Use cpu_abort() when in CPU context, abort() otherwise.

Signed-off-by: Blue Swirl <>

d4c430a8 03/17/2010 04:44 am Paul Brook

Large page TLB flush

QEMU uses a fixed page size for the CPU TLB. If the guest uses large
pages then we effectively split these into multiple smaller pages, and
populate the corresponding TLB entries on demand.

When the guest invalidates the TLB by virtual address we must invalidate...

3c7b48b7 03/12/2010 08:44 pm Paul Brook

Target specific usermode cleanup

Disable various target specific code that is only relevant to system emulation.

Signed-off-by: Paul Brook <>

4fcc562b 03/12/2010 08:34 pm Paul Brook

Remove cpu_get_phys_page_debug from userspace emulation

cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.

Signed-off-by: Paul Brook <>

52705890 03/12/2010 06:28 pm Richard Henderson

Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.

Removes a set of ifdefs from exec.c.

Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other
than Alpha. This will be used for page_find_alloc, which is
supposed to be using virtual addresses in the first place....

ee0dc6d3 02/14/2010 09:23 am Blue Swirl

Fix incorrect exception_index use

env->exception_index should be cleared with -1, not 0.

See also 821b19fe923ac49a24cdb4af902584fdd019cee6.

Spotted by Igor Kovalenko.

Signed-off-by: Blue Swirl <>

5a25cc2b 02/09/2010 10:08 pm Aurelien Jarno

target-sh4: MMU: separate execute and read/write permissions

On SH4, the ITLB and UTLB configurations are memory mapped, so loading
ITLB entries from UTLB has to be simulated correctly. For that the QEMU
TLB has to be handle the execute (ITLB) and read/write permissions...

55ff33a4 02/09/2010 10:08 pm Aurelien Jarno

target-sh4: MMU: remove dead code

Signed-off-by: Aurelien Jarno <>

03e3b61e 02/09/2010 10:08 pm Aurelien Jarno

target-sh4: MMU: fix store queue addresses

The store queues are located from 0xe0000000 to 0xe3ffffff.

Signed-off-by: Aurelien Jarno <>

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