Revision 8c0fdd85 target-mips/op_helper.c
| b/target-mips/op_helper.c | ||
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| 141 | 141 |
cpu_abort(env, "mfc0 count\n"); |
| 142 | 142 |
} |
| 143 | 143 |
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void do_mtc0 (int reg, int sel)
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void cpu_mips_store_count(CPUState *env, uint32_t value)
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{
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cpu_abort(env, "mtc0 reg=%d sel=%d\n", reg, sel); |
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cpu_abort(env, "mtc0 count\n"); |
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} |
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void cpu_mips_store_compare(CPUState *env, uint32_t value) |
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{
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cpu_abort(env, "mtc0 compare\n"); |
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} |
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void do_mtc0_status_debug(uint32_t old, uint32_t val) |
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{
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cpu_abort(env, "mtc0 status\n"); |
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} |
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void do_mtc0_status_irqraise_debug(void) |
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{
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cpu_abort(env, "mtc0 status\n"); |
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} |
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void do_tlbwi (void) |
| ... | ... | |
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cpu_abort(env, "tlbr\n"); |
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} |
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void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
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{
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cpu_abort(env, "mips_tlb_flush\n"); |
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} |
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#else |
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/* CP0 helpers */ |
| ... | ... | |
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T0 = cpu_mips_get_count(env); |
| 180 | 200 |
} |
| 181 | 201 |
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void do_mtc0 (int reg, int sel)
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void do_mtc0_status_debug(uint32_t old, uint32_t val)
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{
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const unsigned char *rn; |
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uint32_t val, old, mask; |
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const uint32_t mask = 0x0000FF00; |
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fprintf(logfile, "Status %08x => %08x Cause %08x (%08x %08x %08x)\n", |
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old, val, env->CP0_Cause, old & mask, val & mask, |
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env->CP0_Cause & mask); |
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} |
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if (sel != 0 && reg != 16 && reg != 28) {
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val = -1; |
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old = -1; |
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rn = "invalid"; |
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goto print; |
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} |
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switch (reg) {
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case 0: |
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val = (env->CP0_index & 0x80000000) | (T0 & 0x0000000F); |
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old = env->CP0_index; |
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env->CP0_index = val; |
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rn = "Index"; |
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break; |
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case 2: |
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val = T0 & 0x3FFFFFFF; |
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old = env->CP0_EntryLo0; |
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env->CP0_EntryLo0 = val; |
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rn = "EntryLo0"; |
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break; |
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case 3: |
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val = T0 & 0x3FFFFFFF; |
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old = env->CP0_EntryLo1; |
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env->CP0_EntryLo1 = val; |
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rn = "EntryLo1"; |
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break; |
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case 4: |
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val = (env->CP0_Context & 0xFF800000) | (T0 & 0x007FFFF0); |
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old = env->CP0_Context; |
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env->CP0_Context = val; |
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rn = "Context"; |
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break; |
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case 5: |
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val = T0 & 0x01FFE000; |
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old = env->CP0_PageMask; |
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env->CP0_PageMask = val; |
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rn = "PageMask"; |
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break; |
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case 6: |
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val = T0 & 0x0000000F; |
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old = env->CP0_Wired; |
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env->CP0_Wired = val; |
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rn = "Wired"; |
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break; |
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case 9: |
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val = T0; |
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old = cpu_mips_get_count(env); |
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cpu_mips_store_count(env, val); |
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rn = "Count"; |
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break; |
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case 10: |
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val = T0 & 0xFFFFE0FF; |
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old = env->CP0_EntryHi; |
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env->CP0_EntryHi = val; |
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/* If the ASID changes, flush qemu's TLB. */ |
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if ((old & 0xFF) != (val & 0xFF)) |
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cpu_mips_tlb_flush (env, 1); |
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rn = "EntryHi"; |
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break; |
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case 11: |
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val = T0; |
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old = env->CP0_Compare; |
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cpu_mips_store_compare(env, val); |
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rn = "Compare"; |
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break; |
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case 12: |
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val = T0 & 0xFA78FF01; |
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if (T0 & (1 << CP0St_UM)) |
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env->hflags |= MIPS_HFLAG_UM; |
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else |
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env->hflags &= ~MIPS_HFLAG_UM; |
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if (T0 & (1 << CP0St_ERL)) |
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env->hflags |= MIPS_HFLAG_ERL; |
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else |
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env->hflags &= ~MIPS_HFLAG_ERL; |
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if (T0 & (1 << CP0St_EXL)) |
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env->hflags |= MIPS_HFLAG_EXL; |
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else |
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env->hflags &= ~MIPS_HFLAG_EXL; |
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old = env->CP0_Status; |
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env->CP0_Status = val; |
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/* If we unmasked an asserted IRQ, raise it */ |
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mask = 0x0000FF00; |
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if (loglevel & CPU_LOG_TB_IN_ASM) {
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fprintf(logfile, "Status %08x => %08x Cause %08x (%08x %08x %08x)\n", |
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old, val, env->CP0_Cause, old & mask, val & mask, |
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env->CP0_Cause & mask); |
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} |
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if ((val & (1 << CP0St_IE)) && !(old & (1 << CP0St_IE)) && |
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!(env->hflags & MIPS_HFLAG_EXL) && |
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!(env->hflags & MIPS_HFLAG_ERL) && |
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!(env->hflags & MIPS_HFLAG_DM) && |
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(env->CP0_Status & env->CP0_Cause & mask)) {
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if (logfile) |
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fprintf(logfile, "Raise pending IRQs\n"); |
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env->interrupt_request |= CPU_INTERRUPT_HARD; |
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} else if (!(val & (1 << CP0St_IE)) && (old & (1 << CP0St_IE))) {
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env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
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} |
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rn = "Status"; |
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break; |
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case 13: |
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val = (env->CP0_Cause & 0xB000F87C) | (T0 & 0x000C00300); |
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old = env->CP0_Cause; |
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env->CP0_Cause = val; |
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#if 0 |
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{
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int i; |
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/* Check if we ever asserted a software IRQ */ |
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for (i = 0; i < 2; i++) {
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mask = 0x100 << i; |
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if ((val & mask) & !(old & mask)) |
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mips_set_irq(i); |
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} |
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} |
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#endif |
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rn = "Cause"; |
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break; |
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case 14: |
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val = T0; |
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old = env->CP0_EPC; |
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env->CP0_EPC = val; |
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rn = "EPC"; |
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break; |
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case 16: |
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switch (sel) {
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case 0: |
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#if defined(MIPS_USES_R4K_TLB) |
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val = (env->CP0_Config0 & 0x8017FF80) | (T0 & 0x7E000001); |
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#else |
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val = (env->CP0_Config0 & 0xFE17FF80) | (T0 & 0x00000001); |
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#endif |
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old = env->CP0_Config0; |
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env->CP0_Config0 = val; |
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rn = "Config0"; |
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break; |
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default: |
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val = -1; |
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old = -1; |
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rn = "bad config selector"; |
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break; |
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} |
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break; |
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case 18: |
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val = T0; |
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old = env->CP0_WatchLo; |
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env->CP0_WatchLo = val; |
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rn = "WatchLo"; |
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break; |
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case 19: |
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val = T0 & 0x40FF0FF8; |
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old = env->CP0_WatchHi; |
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env->CP0_WatchHi = val; |
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rn = "WatchHi"; |
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break; |
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case 23: |
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val = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120); |
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if (T0 & (1 << CP0DB_DM)) |
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env->hflags |= MIPS_HFLAG_DM; |
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else |
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env->hflags &= ~MIPS_HFLAG_DM; |
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old = env->CP0_Debug; |
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env->CP0_Debug = val; |
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rn = "Debug"; |
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break; |
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case 24: |
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val = T0; |
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old = env->CP0_DEPC; |
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env->CP0_DEPC = val; |
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rn = "DEPC"; |
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break; |
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case 28: |
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switch (sel) {
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case 0: |
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val = T0 & 0xFFFFFCF6; |
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old = env->CP0_TagLo; |
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env->CP0_TagLo = val; |
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rn = "TagLo"; |
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break; |
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default: |
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val = -1; |
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old = -1; |
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rn = "invalid sel"; |
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break; |
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} |
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break; |
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case 30: |
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val = T0; |
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old = env->CP0_ErrorEPC; |
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env->CP0_ErrorEPC = val; |
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rn = "EPC"; |
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break; |
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case 31: |
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val = T0; |
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old = env->CP0_DESAVE; |
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env->CP0_DESAVE = val; |
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rn = "DESAVE"; |
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break; |
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default: |
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val = -1; |
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old = -1; |
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rn = "unknown"; |
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| 388 |
break; |
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} |
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print: |
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#if defined MIPS_DEBUG_DISAS |
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if (loglevel & CPU_LOG_TB_IN_ASM) {
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fprintf(logfile, "%08x mtc0 %s %08x => %08x (%d %d %08x)\n", |
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env->PC, rn, T0, val, reg, sel, old); |
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} |
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#endif |
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return; |
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void do_mtc0_status_irqraise_debug(void) |
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{
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fprintf(logfile, "Raise pending IRQs\n"); |
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| 398 | 213 |
} |
| 399 | 214 |
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| 400 | 215 |
#ifdef MIPS_USES_FPU |
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